10d5b288cSTim Harvey// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 20d5b288cSTim Harvey/* 30d5b288cSTim Harvey * Copyright 2023 Gateworks Corporation 40d5b288cSTim Harvey */ 50d5b288cSTim Harvey 60d5b288cSTim Harvey#include <dt-bindings/gpio/gpio.h> 70d5b288cSTim Harvey#include <dt-bindings/input/linux-event-codes.h> 80d5b288cSTim Harvey#include <dt-bindings/net/ti-dp83867.h> 90d5b288cSTim Harvey 100d5b288cSTim Harvey/ { 110d5b288cSTim Harvey aliases { 120d5b288cSTim Harvey ethernet0 = &eqos; 130d5b288cSTim Harvey }; 140d5b288cSTim Harvey 150d5b288cSTim Harvey memory@40000000 { 160d5b288cSTim Harvey device_type = "memory"; 170d5b288cSTim Harvey reg = <0x0 0x40000000 0 0x80000000>; 180d5b288cSTim Harvey }; 190d5b288cSTim Harvey 200d5b288cSTim Harvey gpio-keys { 210d5b288cSTim Harvey compatible = "gpio-keys"; 220d5b288cSTim Harvey 230d5b288cSTim Harvey key-user-pb { 240d5b288cSTim Harvey label = "user_pb"; 250d5b288cSTim Harvey gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 260d5b288cSTim Harvey linux,code = <BTN_0>; 270d5b288cSTim Harvey }; 280d5b288cSTim Harvey 290d5b288cSTim Harvey key-user-pb1x { 300d5b288cSTim Harvey label = "user_pb1x"; 310d5b288cSTim Harvey linux,code = <BTN_1>; 320d5b288cSTim Harvey interrupt-parent = <&gsc>; 330d5b288cSTim Harvey interrupts = <0>; 340d5b288cSTim Harvey }; 350d5b288cSTim Harvey 360d5b288cSTim Harvey key-erased { 370d5b288cSTim Harvey label = "key_erased"; 380d5b288cSTim Harvey linux,code = <BTN_2>; 390d5b288cSTim Harvey interrupt-parent = <&gsc>; 400d5b288cSTim Harvey interrupts = <1>; 410d5b288cSTim Harvey }; 420d5b288cSTim Harvey 430d5b288cSTim Harvey key-eeprom-wp { 440d5b288cSTim Harvey label = "eeprom_wp"; 450d5b288cSTim Harvey linux,code = <BTN_3>; 460d5b288cSTim Harvey interrupt-parent = <&gsc>; 470d5b288cSTim Harvey interrupts = <2>; 480d5b288cSTim Harvey }; 490d5b288cSTim Harvey 500d5b288cSTim Harvey key-tamper { 510d5b288cSTim Harvey label = "tamper"; 520d5b288cSTim Harvey linux,code = <BTN_4>; 530d5b288cSTim Harvey interrupt-parent = <&gsc>; 540d5b288cSTim Harvey interrupts = <5>; 550d5b288cSTim Harvey }; 560d5b288cSTim Harvey 570d5b288cSTim Harvey switch-hold { 580d5b288cSTim Harvey label = "switch_hold"; 590d5b288cSTim Harvey linux,code = <BTN_5>; 600d5b288cSTim Harvey interrupt-parent = <&gsc>; 610d5b288cSTim Harvey interrupts = <7>; 620d5b288cSTim Harvey }; 630d5b288cSTim Harvey }; 640d5b288cSTim Harvey}; 650d5b288cSTim Harvey 660d5b288cSTim Harvey&A53_0 { 670d5b288cSTim Harvey cpu-supply = <&buck3_reg>; 680d5b288cSTim Harvey}; 690d5b288cSTim Harvey 700d5b288cSTim Harvey&A53_1 { 710d5b288cSTim Harvey cpu-supply = <&buck3_reg>; 720d5b288cSTim Harvey}; 730d5b288cSTim Harvey 740d5b288cSTim Harvey&A53_2 { 750d5b288cSTim Harvey cpu-supply = <&buck3_reg>; 760d5b288cSTim Harvey}; 770d5b288cSTim Harvey 780d5b288cSTim Harvey&A53_3 { 790d5b288cSTim Harvey cpu-supply = <&buck3_reg>; 800d5b288cSTim Harvey}; 810d5b288cSTim Harvey 820d5b288cSTim Harvey&eqos { 830d5b288cSTim Harvey pinctrl-names = "default"; 840d5b288cSTim Harvey pinctrl-0 = <&pinctrl_eqos>; 850d5b288cSTim Harvey phy-mode = "rgmii-id"; 860d5b288cSTim Harvey phy-handle = <ðphy0>; 870d5b288cSTim Harvey status = "okay"; 880d5b288cSTim Harvey 890d5b288cSTim Harvey mdio { 900d5b288cSTim Harvey compatible = "snps,dwmac-mdio"; 910d5b288cSTim Harvey #address-cells = <1>; 920d5b288cSTim Harvey #size-cells = <0>; 930d5b288cSTim Harvey 940d5b288cSTim Harvey ethphy0: ethernet-phy@0 { 950d5b288cSTim Harvey compatible = "ethernet-phy-ieee802.3-c22"; 960d5b288cSTim Harvey pinctrl-0 = <&pinctrl_ethphy0>; 970d5b288cSTim Harvey pinctrl-names = "default"; 980d5b288cSTim Harvey reg = <0x0>; 990d5b288cSTim Harvey interrupt-parent = <&gpio3>; 1000d5b288cSTim Harvey interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 1010d5b288cSTim Harvey ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 1020d5b288cSTim Harvey ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 1030d5b288cSTim Harvey tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 1040d5b288cSTim Harvey rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 1050d5b288cSTim Harvey }; 1060d5b288cSTim Harvey }; 1070d5b288cSTim Harvey}; 1080d5b288cSTim Harvey 1090d5b288cSTim Harvey&i2c1 { 1100d5b288cSTim Harvey clock-frequency = <100000>; 1110d5b288cSTim Harvey pinctrl-names = "default", "gpio"; 1120d5b288cSTim Harvey pinctrl-0 = <&pinctrl_i2c1>; 1130d5b288cSTim Harvey pinctrl-1 = <&pinctrl_i2c1_gpio>; 1140d5b288cSTim Harvey scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 1150d5b288cSTim Harvey sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 1160d5b288cSTim Harvey status = "okay"; 1170d5b288cSTim Harvey 1180d5b288cSTim Harvey gsc: gsc@20 { 1190d5b288cSTim Harvey compatible = "gw,gsc"; 1200d5b288cSTim Harvey reg = <0x20>; 1210d5b288cSTim Harvey pinctrl-0 = <&pinctrl_gsc>; 1220d5b288cSTim Harvey interrupt-parent = <&gpio2>; 1230d5b288cSTim Harvey interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 1240d5b288cSTim Harvey interrupt-controller; 1250d5b288cSTim Harvey #interrupt-cells = <1>; 1260d5b288cSTim Harvey #address-cells = <1>; 1270d5b288cSTim Harvey #size-cells = <0>; 1280d5b288cSTim Harvey 1290d5b288cSTim Harvey adc { 1300d5b288cSTim Harvey compatible = "gw,gsc-adc"; 1310d5b288cSTim Harvey #address-cells = <1>; 1320d5b288cSTim Harvey #size-cells = <0>; 1330d5b288cSTim Harvey 1340d5b288cSTim Harvey channel@6 { 1350d5b288cSTim Harvey gw,mode = <0>; 1360d5b288cSTim Harvey reg = <0x06>; 1370d5b288cSTim Harvey label = "temp"; 1380d5b288cSTim Harvey }; 1390d5b288cSTim Harvey 1400d5b288cSTim Harvey channel@8 { 141*2e21f19fSTim Harvey gw,mode = <3>; 1420d5b288cSTim Harvey reg = <0x08>; 1430d5b288cSTim Harvey label = "vdd_bat"; 1440d5b288cSTim Harvey }; 1450d5b288cSTim Harvey 1460d5b288cSTim Harvey channel@16 { 1470d5b288cSTim Harvey gw,mode = <4>; 1480d5b288cSTim Harvey reg = <0x16>; 1490d5b288cSTim Harvey label = "fan_tach"; 1500d5b288cSTim Harvey }; 1510d5b288cSTim Harvey 1520d5b288cSTim Harvey channel@82 { 1530d5b288cSTim Harvey gw,mode = <2>; 1540d5b288cSTim Harvey reg = <0x82>; 1550d5b288cSTim Harvey label = "vdd_vin"; 1560d5b288cSTim Harvey gw,voltage-divider-ohms = <22100 1000>; 1570d5b288cSTim Harvey }; 1580d5b288cSTim Harvey 1590d5b288cSTim Harvey channel@84 { 1600d5b288cSTim Harvey gw,mode = <2>; 1610d5b288cSTim Harvey reg = <0x84>; 1620d5b288cSTim Harvey label = "vdd_adc1"; 1630d5b288cSTim Harvey gw,voltage-divider-ohms = <10000 10000>; 1640d5b288cSTim Harvey }; 1650d5b288cSTim Harvey 1660d5b288cSTim Harvey channel@86 { 1670d5b288cSTim Harvey gw,mode = <2>; 1680d5b288cSTim Harvey reg = <0x86>; 1690d5b288cSTim Harvey label = "vdd_adc2"; 1700d5b288cSTim Harvey gw,voltage-divider-ohms = <10000 10000>; 1710d5b288cSTim Harvey }; 1720d5b288cSTim Harvey 1730d5b288cSTim Harvey channel@88 { 1740d5b288cSTim Harvey gw,mode = <2>; 1750d5b288cSTim Harvey reg = <0x88>; 1760d5b288cSTim Harvey label = "vdd_1p0"; 1770d5b288cSTim Harvey }; 1780d5b288cSTim Harvey 1790d5b288cSTim Harvey channel@8c { 1800d5b288cSTim Harvey gw,mode = <2>; 1810d5b288cSTim Harvey reg = <0x8c>; 1820d5b288cSTim Harvey label = "vdd_1p8"; 1830d5b288cSTim Harvey }; 1840d5b288cSTim Harvey 1850d5b288cSTim Harvey channel@8e { 1860d5b288cSTim Harvey gw,mode = <2>; 1870d5b288cSTim Harvey reg = <0x8e>; 1880d5b288cSTim Harvey label = "vdd_2p5"; 1890d5b288cSTim Harvey }; 1900d5b288cSTim Harvey 1910d5b288cSTim Harvey channel@90 { 1920d5b288cSTim Harvey gw,mode = <2>; 1930d5b288cSTim Harvey reg = <0x90>; 1940d5b288cSTim Harvey label = "vdd_3p3"; 1950d5b288cSTim Harvey gw,voltage-divider-ohms = <10000 10000>; 1960d5b288cSTim Harvey }; 1970d5b288cSTim Harvey 1980d5b288cSTim Harvey channel@92 { 1990d5b288cSTim Harvey gw,mode = <2>; 2000d5b288cSTim Harvey reg = <0x92>; 2010d5b288cSTim Harvey label = "vdd_dram"; 2020d5b288cSTim Harvey }; 2030d5b288cSTim Harvey 2040d5b288cSTim Harvey channel@98 { 2050d5b288cSTim Harvey gw,mode = <2>; 2060d5b288cSTim Harvey reg = <0x98>; 2070d5b288cSTim Harvey label = "vdd_soc"; 2080d5b288cSTim Harvey }; 2090d5b288cSTim Harvey 2100d5b288cSTim Harvey channel@9a { 2110d5b288cSTim Harvey gw,mode = <2>; 2120d5b288cSTim Harvey reg = <0x9a>; 2130d5b288cSTim Harvey label = "vdd_arm"; 2140d5b288cSTim Harvey }; 2150d5b288cSTim Harvey 2160d5b288cSTim Harvey channel@a2 { 2170d5b288cSTim Harvey gw,mode = <2>; 2180d5b288cSTim Harvey reg = <0xa2>; 2190d5b288cSTim Harvey label = "vdd_gsc"; 2200d5b288cSTim Harvey gw,voltage-divider-ohms = <10000 10000>; 2210d5b288cSTim Harvey }; 2220d5b288cSTim Harvey }; 2230d5b288cSTim Harvey 2240d5b288cSTim Harvey fan-controller@0 { 2250d5b288cSTim Harvey compatible = "gw,gsc-fan"; 2260d5b288cSTim Harvey reg = <0x0a>; 2270d5b288cSTim Harvey }; 2280d5b288cSTim Harvey }; 2290d5b288cSTim Harvey 2300d5b288cSTim Harvey gpio: gpio@23 { 2310d5b288cSTim Harvey compatible = "nxp,pca9555"; 2320d5b288cSTim Harvey reg = <0x23>; 2330d5b288cSTim Harvey gpio-controller; 2340d5b288cSTim Harvey #gpio-cells = <2>; 2350d5b288cSTim Harvey interrupt-parent = <&gsc>; 2360d5b288cSTim Harvey interrupts = <4>; 2370d5b288cSTim Harvey }; 2380d5b288cSTim Harvey 2390d5b288cSTim Harvey eeprom@50 { 2400d5b288cSTim Harvey compatible = "atmel,24c02"; 2410d5b288cSTim Harvey reg = <0x50>; 2420d5b288cSTim Harvey pagesize = <16>; 2430d5b288cSTim Harvey }; 2440d5b288cSTim Harvey 2450d5b288cSTim Harvey eeprom@51 { 2460d5b288cSTim Harvey compatible = "atmel,24c02"; 2470d5b288cSTim Harvey reg = <0x51>; 2480d5b288cSTim Harvey pagesize = <16>; 2490d5b288cSTim Harvey }; 2500d5b288cSTim Harvey 2510d5b288cSTim Harvey eeprom@52 { 2520d5b288cSTim Harvey compatible = "atmel,24c02"; 2530d5b288cSTim Harvey reg = <0x52>; 2540d5b288cSTim Harvey pagesize = <16>; 2550d5b288cSTim Harvey }; 2560d5b288cSTim Harvey 2570d5b288cSTim Harvey eeprom@53 { 2580d5b288cSTim Harvey compatible = "atmel,24c02"; 2590d5b288cSTim Harvey reg = <0x53>; 2600d5b288cSTim Harvey pagesize = <16>; 2610d5b288cSTim Harvey }; 2620d5b288cSTim Harvey 2630d5b288cSTim Harvey rtc@68 { 2640d5b288cSTim Harvey compatible = "dallas,ds1672"; 2650d5b288cSTim Harvey reg = <0x68>; 2660d5b288cSTim Harvey }; 2670d5b288cSTim Harvey 2680d5b288cSTim Harvey pmic@69 { 2690d5b288cSTim Harvey compatible = "mps,mp5416"; 2700d5b288cSTim Harvey reg = <0x69>; 2710d5b288cSTim Harvey 2720d5b288cSTim Harvey regulators { 2730d5b288cSTim Harvey /* vdd_soc */ 2740d5b288cSTim Harvey buck1 { 2750d5b288cSTim Harvey regulator-name = "buck1"; 2760d5b288cSTim Harvey regulator-min-microvolt = <850000>; 2770d5b288cSTim Harvey regulator-max-microvolt = <1000000>; 2780d5b288cSTim Harvey regulator-always-on; 2790d5b288cSTim Harvey regulator-boot-on; 2800d5b288cSTim Harvey }; 2810d5b288cSTim Harvey 2820d5b288cSTim Harvey /* vdd_dram */ 2830d5b288cSTim Harvey buck2 { 2840d5b288cSTim Harvey regulator-name = "buck2"; 2850d5b288cSTim Harvey regulator-min-microvolt = <1100000>; 2860d5b288cSTim Harvey regulator-max-microvolt = <1100000>; 2870d5b288cSTim Harvey regulator-always-on; 2880d5b288cSTim Harvey regulator-boot-on; 2890d5b288cSTim Harvey }; 2900d5b288cSTim Harvey 2910d5b288cSTim Harvey /* vdd_arm */ 2920d5b288cSTim Harvey buck3_reg: buck3 { 2930d5b288cSTim Harvey regulator-name = "buck3"; 2940d5b288cSTim Harvey regulator-min-microvolt = <850000>; 2950d5b288cSTim Harvey regulator-max-microvolt = <1000000>; 2960d5b288cSTim Harvey regulator-always-on; 2970d5b288cSTim Harvey regulator-boot-on; 2980d5b288cSTim Harvey }; 2990d5b288cSTim Harvey 3000d5b288cSTim Harvey /* vdd_1p8 */ 3010d5b288cSTim Harvey buck4 { 3020d5b288cSTim Harvey regulator-name = "buck4"; 3030d5b288cSTim Harvey regulator-min-microvolt = <1800000>; 3040d5b288cSTim Harvey regulator-max-microvolt = <1800000>; 3050d5b288cSTim Harvey regulator-always-on; 3060d5b288cSTim Harvey regulator-boot-on; 3070d5b288cSTim Harvey }; 3080d5b288cSTim Harvey 3090d5b288cSTim Harvey /* OUT2: nvcc_snvs_1p8 */ 3100d5b288cSTim Harvey ldo1 { 3110d5b288cSTim Harvey regulator-name = "ldo1"; 3120d5b288cSTim Harvey regulator-min-microvolt = <1800000>; 3130d5b288cSTim Harvey regulator-max-microvolt = <1800000>; 3140d5b288cSTim Harvey regulator-always-on; 3150d5b288cSTim Harvey regulator-boot-on; 3160d5b288cSTim Harvey }; 3170d5b288cSTim Harvey 3180d5b288cSTim Harvey /* OUT3: vdd_1p0 */ 3190d5b288cSTim Harvey ldo2 { 3200d5b288cSTim Harvey regulator-name = "ldo2"; 3210d5b288cSTim Harvey regulator-min-microvolt = <1000000>; 3220d5b288cSTim Harvey regulator-max-microvolt = <1000000>; 3230d5b288cSTim Harvey regulator-always-on; 3240d5b288cSTim Harvey regulator-boot-on; 3250d5b288cSTim Harvey }; 3260d5b288cSTim Harvey 3270d5b288cSTim Harvey /* OUT4: vdd_2p5 */ 3280d5b288cSTim Harvey ldo3 { 3290d5b288cSTim Harvey regulator-name = "ldo3"; 3300d5b288cSTim Harvey regulator-min-microvolt = <2500000>; 3310d5b288cSTim Harvey regulator-max-microvolt = <2500000>; 3320d5b288cSTim Harvey regulator-always-on; 3330d5b288cSTim Harvey regulator-boot-on; 3340d5b288cSTim Harvey }; 3350d5b288cSTim Harvey 3360d5b288cSTim Harvey /* OUT5: vdd_3p3 */ 3370d5b288cSTim Harvey ldo4 { 3380d5b288cSTim Harvey regulator-name = "ldo4"; 3390d5b288cSTim Harvey regulator-min-microvolt = <3300000>; 3400d5b288cSTim Harvey regulator-max-microvolt = <3300000>; 3410d5b288cSTim Harvey regulator-always-on; 3420d5b288cSTim Harvey regulator-boot-on; 3430d5b288cSTim Harvey }; 3440d5b288cSTim Harvey }; 3450d5b288cSTim Harvey }; 3460d5b288cSTim Harvey}; 3470d5b288cSTim Harvey 3480d5b288cSTim Harvey/* off-board header */ 3490d5b288cSTim Harvey&i2c2 { 3500d5b288cSTim Harvey clock-frequency = <400000>; 3510d5b288cSTim Harvey pinctrl-names = "default", "gpio"; 3520d5b288cSTim Harvey pinctrl-0 = <&pinctrl_i2c2>; 3530d5b288cSTim Harvey pinctrl-1 = <&pinctrl_i2c2_gpio>; 3540d5b288cSTim Harvey scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 3550d5b288cSTim Harvey sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 3560d5b288cSTim Harvey status = "okay"; 3570d5b288cSTim Harvey 3580d5b288cSTim Harvey eeprom@52 { 3590d5b288cSTim Harvey compatible = "atmel,24c32"; 3600d5b288cSTim Harvey reg = <0x52>; 3610d5b288cSTim Harvey pagesize = <32>; 3620d5b288cSTim Harvey }; 3630d5b288cSTim Harvey}; 3640d5b288cSTim Harvey 3650d5b288cSTim Harvey/* off-board header */ 3660d5b288cSTim Harvey&i2c3 { 3670d5b288cSTim Harvey clock-frequency = <400000>; 3680d5b288cSTim Harvey pinctrl-names = "default", "gpio"; 3690d5b288cSTim Harvey pinctrl-0 = <&pinctrl_i2c3>; 3700d5b288cSTim Harvey pinctrl-1 = <&pinctrl_i2c3_gpio>; 3710d5b288cSTim Harvey scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 3720d5b288cSTim Harvey sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 3730d5b288cSTim Harvey status = "okay"; 3740d5b288cSTim Harvey}; 3750d5b288cSTim Harvey 3760d5b288cSTim Harvey/* off-board header */ 3770d5b288cSTim Harvey&uart1 { 3780d5b288cSTim Harvey pinctrl-names = "default"; 3790d5b288cSTim Harvey pinctrl-0 = <&pinctrl_uart1>; 3800d5b288cSTim Harvey status = "okay"; 3810d5b288cSTim Harvey}; 3820d5b288cSTim Harvey 3830d5b288cSTim Harvey/* console */ 3840d5b288cSTim Harvey&uart2 { 3850d5b288cSTim Harvey pinctrl-names = "default"; 3860d5b288cSTim Harvey pinctrl-0 = <&pinctrl_uart2>; 3870d5b288cSTim Harvey status = "okay"; 3880d5b288cSTim Harvey}; 3890d5b288cSTim Harvey 3900d5b288cSTim Harvey/* off-board header */ 3910d5b288cSTim Harvey&uart3 { 3920d5b288cSTim Harvey pinctrl-names = "default"; 3930d5b288cSTim Harvey pinctrl-0 = <&pinctrl_uart3>; 3940d5b288cSTim Harvey status = "okay"; 3950d5b288cSTim Harvey}; 3960d5b288cSTim Harvey 3970d5b288cSTim Harvey/* off-board */ 3980d5b288cSTim Harvey&usdhc1 { 3990d5b288cSTim Harvey pinctrl-names = "default"; 4000d5b288cSTim Harvey pinctrl-0 = <&pinctrl_usdhc1>; 4010d5b288cSTim Harvey bus-width = <4>; 4020d5b288cSTim Harvey non-removable; 4030d5b288cSTim Harvey status = "okay"; 4040d5b288cSTim Harvey bus-width = <4>; 4050d5b288cSTim Harvey non-removable; 4060d5b288cSTim Harvey status = "okay"; 4070d5b288cSTim Harvey}; 4080d5b288cSTim Harvey 4090d5b288cSTim Harvey/* eMMC */ 4100d5b288cSTim Harvey&usdhc3 { 4110d5b288cSTim Harvey pinctrl-names = "default", "state_100mhz", "state_200mhz"; 4120d5b288cSTim Harvey pinctrl-0 = <&pinctrl_usdhc3>; 4130d5b288cSTim Harvey pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 4140d5b288cSTim Harvey pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 4150d5b288cSTim Harvey bus-width = <8>; 4160d5b288cSTim Harvey non-removable; 4170d5b288cSTim Harvey status = "okay"; 4180d5b288cSTim Harvey}; 4190d5b288cSTim Harvey 4200d5b288cSTim Harvey&wdog1 { 4210d5b288cSTim Harvey pinctrl-names = "default"; 4220d5b288cSTim Harvey pinctrl-0 = <&pinctrl_wdog>; 4230d5b288cSTim Harvey fsl,ext-reset-output; 4240d5b288cSTim Harvey status = "okay"; 4250d5b288cSTim Harvey}; 4260d5b288cSTim Harvey 4270d5b288cSTim Harvey&iomuxc { 4280d5b288cSTim Harvey pinctrl_eqos: eqosgrp { 4290d5b288cSTim Harvey fsl,pins = < 4300d5b288cSTim Harvey MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 4310d5b288cSTim Harvey MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 4320d5b288cSTim Harvey MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 4330d5b288cSTim Harvey MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 4340d5b288cSTim Harvey MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 4350d5b288cSTim Harvey MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 4360d5b288cSTim Harvey MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 4370d5b288cSTim Harvey MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 4380d5b288cSTim Harvey MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 4390d5b288cSTim Harvey MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 4400d5b288cSTim Harvey MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 4410d5b288cSTim Harvey MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 4420d5b288cSTim Harvey MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 4430d5b288cSTim Harvey MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 4440d5b288cSTim Harvey >; 4450d5b288cSTim Harvey }; 4460d5b288cSTim Harvey 4470d5b288cSTim Harvey pinctrl_ethphy0: ethphy0grp { 4480d5b288cSTim Harvey fsl,pins = < 4490d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */ 4500d5b288cSTim Harvey MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */ 4510d5b288cSTim Harvey >; 4520d5b288cSTim Harvey }; 4530d5b288cSTim Harvey 4540d5b288cSTim Harvey pinctrl_gsc: gscgrp { 4550d5b288cSTim Harvey fsl,pins = < 4560d5b288cSTim Harvey MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */ 4570d5b288cSTim Harvey >; 4580d5b288cSTim Harvey }; 4590d5b288cSTim Harvey 4600d5b288cSTim Harvey pinctrl_i2c1: i2c1grp { 4610d5b288cSTim Harvey fsl,pins = < 4620d5b288cSTim Harvey MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 4630d5b288cSTim Harvey MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 4640d5b288cSTim Harvey >; 4650d5b288cSTim Harvey }; 4660d5b288cSTim Harvey 4670d5b288cSTim Harvey pinctrl_i2c1_gpio: i2c1gpiogrp { 4680d5b288cSTim Harvey fsl,pins = < 4690d5b288cSTim Harvey MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 4700d5b288cSTim Harvey MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 4710d5b288cSTim Harvey >; 4720d5b288cSTim Harvey }; 4730d5b288cSTim Harvey 4740d5b288cSTim Harvey pinctrl_i2c2: i2c2grp { 4750d5b288cSTim Harvey fsl,pins = < 4760d5b288cSTim Harvey MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 4770d5b288cSTim Harvey MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 4780d5b288cSTim Harvey >; 4790d5b288cSTim Harvey }; 4800d5b288cSTim Harvey 4810d5b288cSTim Harvey pinctrl_i2c2_gpio: i2c2gpiogrp { 4820d5b288cSTim Harvey fsl,pins = < 4830d5b288cSTim Harvey MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 4840d5b288cSTim Harvey MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 4850d5b288cSTim Harvey >; 4860d5b288cSTim Harvey }; 4870d5b288cSTim Harvey 4880d5b288cSTim Harvey pinctrl_i2c3: i2c3grp { 4890d5b288cSTim Harvey fsl,pins = < 4900d5b288cSTim Harvey MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 4910d5b288cSTim Harvey MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 4920d5b288cSTim Harvey >; 4930d5b288cSTim Harvey }; 4940d5b288cSTim Harvey 4950d5b288cSTim Harvey pinctrl_i2c3_gpio: i2c3gpiogrp { 4960d5b288cSTim Harvey fsl,pins = < 4970d5b288cSTim Harvey MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 4980d5b288cSTim Harvey MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 4990d5b288cSTim Harvey >; 5000d5b288cSTim Harvey }; 5010d5b288cSTim Harvey 5020d5b288cSTim Harvey pinctrl_uart1: uart1grp { 5030d5b288cSTim Harvey fsl,pins = < 5040d5b288cSTim Harvey MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 5050d5b288cSTim Harvey MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 5060d5b288cSTim Harvey >; 5070d5b288cSTim Harvey }; 5080d5b288cSTim Harvey 5090d5b288cSTim Harvey pinctrl_uart2: uart2grp { 5100d5b288cSTim Harvey fsl,pins = < 5110d5b288cSTim Harvey MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 5120d5b288cSTim Harvey MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 5130d5b288cSTim Harvey >; 5140d5b288cSTim Harvey }; 5150d5b288cSTim Harvey 5160d5b288cSTim Harvey pinctrl_uart3: uart3grp { 5170d5b288cSTim Harvey fsl,pins = < 5180d5b288cSTim Harvey MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 5190d5b288cSTim Harvey MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 5200d5b288cSTim Harvey >; 5210d5b288cSTim Harvey }; 5220d5b288cSTim Harvey 5230d5b288cSTim Harvey pinctrl_usdhc1: usdhc1grp { 5240d5b288cSTim Harvey fsl,pins = < 5250d5b288cSTim Harvey MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 5260d5b288cSTim Harvey MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 5270d5b288cSTim Harvey MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 5280d5b288cSTim Harvey MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 5290d5b288cSTim Harvey MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 5300d5b288cSTim Harvey MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 5310d5b288cSTim Harvey >; 5320d5b288cSTim Harvey }; 5330d5b288cSTim Harvey 5340d5b288cSTim Harvey pinctrl_usdhc3: usdhc3grp { 5350d5b288cSTim Harvey fsl,pins = < 5360d5b288cSTim Harvey MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 5370d5b288cSTim Harvey MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 5380d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 5390d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 5400d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 5410d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 5420d5b288cSTim Harvey MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 5430d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 5440d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 5450d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 5460d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 5470d5b288cSTim Harvey >; 5480d5b288cSTim Harvey }; 5490d5b288cSTim Harvey 5500d5b288cSTim Harvey pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 5510d5b288cSTim Harvey fsl,pins = < 5520d5b288cSTim Harvey MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 5530d5b288cSTim Harvey MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 5540d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 5550d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 5560d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 5570d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 5580d5b288cSTim Harvey MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 5590d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 5600d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 5610d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 5620d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 5630d5b288cSTim Harvey >; 5640d5b288cSTim Harvey }; 5650d5b288cSTim Harvey 5660d5b288cSTim Harvey pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 5670d5b288cSTim Harvey fsl,pins = < 5680d5b288cSTim Harvey MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 5690d5b288cSTim Harvey MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 5700d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 5710d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 5720d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 5730d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 5740d5b288cSTim Harvey MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 5750d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 5760d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 5770d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 5780d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 5790d5b288cSTim Harvey >; 5800d5b288cSTim Harvey }; 5810d5b288cSTim Harvey 5820d5b288cSTim Harvey pinctrl_wdog: wdoggrp { 5830d5b288cSTim Harvey fsl,pins = < 5840d5b288cSTim Harvey MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 5850d5b288cSTim Harvey >; 5860d5b288cSTim Harvey }; 5870d5b288cSTim Harvey}; 588