1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2021-2022 TQ-Systems GmbH 4 * Author: Alexander Stein <alexander.stein@tq-group.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/leds/common.h> 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12#include <dt-bindings/pwm/pwm.h> 13#include "imx8mp-tqma8mpql.dtsi" 14 15/ { 16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL"; 17 compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; 18 19 chosen { 20 stdout-path = &uart4; 21 }; 22 23 iio-hwmon { 24 compatible = "iio-hwmon"; 25 io-channels = <&adc 0>, <&adc 1>; 26 }; 27 28 aliases { 29 mmc0 = &usdhc3; 30 mmc1 = &usdhc2; 31 mmc2 = &usdhc1; 32 rtc0 = &pcf85063; 33 rtc1 = &snvs_rtc; 34 spi0 = &flexspi; 35 spi1 = &ecspi1; 36 spi2 = &ecspi2; 37 spi3 = &ecspi3; 38 }; 39 40 backlight_lvds: backlight { 41 compatible = "pwm-backlight"; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_backlight>; 44 pwms = <&pwm2 0 5000000 0>; 45 brightness-levels = <0 4 8 16 32 64 128 255>; 46 default-brightness-level = <7>; 47 power-supply = <®_vcc_12v0>; 48 enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 49 status = "disabled"; 50 }; 51 52 clk_xtal25: clk-xtal25 { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <25000000>; 56 }; 57 58 fan0: pwm-fan { 59 compatible = "pwm-fan"; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_pwmfan>; 62 fan-supply = <®_pwm_fan>; 63 #cooling-cells = <2>; 64 /* typical 25 kHz -> 40.000 nsec */ 65 pwms = <&pwm3 0 40000 PWM_POLARITY_INVERTED>; 66 cooling-levels = <0 32 64 128 196 240>; 67 pulses-per-revolution = <2>; 68 interrupt-parent = <&gpio5>; 69 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 70 status = "disabled"; 71 }; 72 73 gpio-keys { 74 compatible = "gpio-keys"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_gpiobutton>; 77 autorepeat; 78 79 switch-1 { 80 label = "S12"; 81 linux,code = <BTN_0>; 82 gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; 83 wakeup-source; 84 }; 85 86 switch-2 { 87 label = "S13"; 88 linux,code = <BTN_1>; 89 gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; 90 wakeup-source; 91 }; 92 }; 93 94 gpio-leds { 95 compatible = "gpio-leds"; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_gpioled>; 98 99 led-0 { 100 color = <LED_COLOR_ID_GREEN>; 101 function = LED_FUNCTION_STATUS; 102 function-enumerator = <0>; 103 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 104 linux,default-trigger = "default-on"; 105 }; 106 107 led-1 { 108 color = <LED_COLOR_ID_GREEN>; 109 function = LED_FUNCTION_HEARTBEAT; 110 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 111 linux,default-trigger = "heartbeat"; 112 }; 113 114 led-2 { 115 color = <LED_COLOR_ID_YELLOW>; 116 function = LED_FUNCTION_STATUS; 117 function-enumerator = <1>; 118 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 119 }; 120 }; 121 122 display: display { 123 /* 124 * Display is not fixed, so compatible has to be added from 125 * DT overlay 126 */ 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_lvdsdisplay>; 129 power-supply = <®_vcc_3v3>; 130 enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; 131 backlight = <&backlight_lvds>; 132 status = "disabled"; 133 }; 134 135 reg_pwm_fan: regulator-pwm-fan { 136 compatible = "regulator-fixed"; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pinctrl_regpwmfan>; 139 regulator-name = "FAN_PWR"; 140 regulator-min-microvolt = <12000000>; 141 regulator-max-microvolt = <12000000>; 142 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 143 enable-active-high; 144 vin-supply = <®_vcc_12v0>; 145 }; 146 147 reg_usdhc2_vmmc: regulator-usdhc2 { 148 compatible = "regulator-fixed"; 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 151 regulator-name = "VSD_3V3"; 152 regulator-min-microvolt = <3300000>; 153 regulator-max-microvolt = <3300000>; 154 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 155 enable-active-high; 156 startup-delay-us = <100>; 157 off-on-delay-us = <12000>; 158 }; 159 160 reg_vcc_12v0: regulator-12v0 { 161 compatible = "regulator-fixed"; 162 pinctrl-names = "default"; 163 pinctrl-0 = <&pinctrl_reg12v0>; 164 regulator-name = "VCC_12V0"; 165 regulator-min-microvolt = <12000000>; 166 regulator-max-microvolt = <12000000>; 167 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 168 enable-active-high; 169 }; 170 171 reg_vcc_3v3: regulator-3v3 { 172 compatible = "regulator-fixed"; 173 regulator-name = "VCC_3V3"; 174 regulator-min-microvolt = <3300000>; 175 regulator-max-microvolt = <3300000>; 176 }; 177 178 reg_vcc_5v0: regulator-5v0 { 179 compatible = "regulator-fixed"; 180 regulator-name = "VCC_5V0"; 181 regulator-min-microvolt = <5000000>; 182 regulator-max-microvolt = <5000000>; 183 }; 184 185 reserved-memory { 186 #address-cells = <2>; 187 #size-cells = <2>; 188 ranges; 189 190 ocram: ocram@900000 { 191 no-map; 192 reg = <0 0x900000 0 0x70000>; 193 }; 194 195 /* global autoconfigured region for contiguous allocations */ 196 linux,cma { 197 compatible = "shared-dma-pool"; 198 reusable; 199 size = <0 0x38000000>; 200 alloc-ranges = <0 0x40000000 0 0xB0000000>; 201 linux,cma-default; 202 }; 203 }; 204 205 thermal-zones { 206 soc-thermal { 207 trips { 208 soc_active0: trip-active0 { 209 temperature = <40000>; 210 hysteresis = <5000>; 211 type = "active"; 212 }; 213 214 soc_active1: trip-active1 { 215 temperature = <48000>; 216 hysteresis = <3000>; 217 type = "active"; 218 }; 219 220 soc_active2: trip-active2 { 221 temperature = <60000>; 222 hysteresis = <10000>; 223 type = "active"; 224 }; 225 }; 226 227 cooling-maps { 228 map1 { 229 trip = <&soc_active0>; 230 cooling-device = <&fan0 1 1>; 231 }; 232 233 map2 { 234 trip = <&soc_active1>; 235 cooling-device = <&fan0 2 2>; 236 }; 237 238 map3 { 239 trip = <&soc_active2>; 240 cooling-device = <&fan0 3 3>; 241 }; 242 }; 243 }; 244 }; 245}; 246 247&ecspi1 { 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_ecspi1>; 250 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 251 status = "okay"; 252}; 253 254&ecspi2 { 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinctrl_ecspi2>; 257 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 258 status = "okay"; 259}; 260 261&ecspi3 { 262 pinctrl-names = "default"; 263 pinctrl-0 = <&pinctrl_ecspi3>; 264 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 265 status = "okay"; 266 267 adc: adc@0 { 268 reg = <0>; 269 compatible = "microchip,mcp3202"; 270 /* 100 ksps * 18 */ 271 spi-max-frequency = <1800000>; 272 vref-supply = <®_vcc_3v3>; 273 #io-channel-cells = <1>; 274 }; 275}; 276 277&eqos { 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>; 280 phy-mode = "rgmii-id"; 281 phy-handle = <ðphy3>; 282 status = "okay"; 283 284 mdio { 285 compatible = "snps,dwmac-mdio"; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 289 ethphy3: ethernet-phy@3 { 290 compatible = "ethernet-phy-ieee802.3-c22"; 291 reg = <3>; 292 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 293 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 294 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 295 ti,dp83867-rxctrl-strap-quirk; 296 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 297 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 298 reset-assert-us = <500000>; 299 reset-deassert-us = <50000>; 300 enet-phy-lane-no-swap; 301 interrupt-parent = <&gpio4>; 302 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 303 }; 304 }; 305}; 306 307&fec { 308 pinctrl-names = "default"; 309 pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>; 310 phy-mode = "rgmii-id"; 311 phy-handle = <ðphy0>; 312 fsl,magic-packet; 313 status = "okay"; 314 315 mdio { 316 #address-cells = <1>; 317 #size-cells = <0>; 318 319 ethphy0: ethernet-phy@0 { 320 compatible = "ethernet-phy-ieee802.3-c22"; 321 reg = <0>; 322 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 323 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 324 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 325 ti,dp83867-rxctrl-strap-quirk; 326 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 327 reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 328 reset-assert-us = <500000>; 329 reset-deassert-us = <50000>; 330 enet-phy-lane-no-swap; 331 interrupt-parent = <&gpio4>; 332 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 333 }; 334 }; 335}; 336 337&flexcan1 { 338 pinctrl-names = "default"; 339 pinctrl-0 = <&pinctrl_flexcan1>; 340 xceiver-supply = <®_vcc_3v3>; 341 status = "okay"; 342}; 343 344&flexcan2 { 345 pinctrl-names = "default"; 346 pinctrl-0 = <&pinctrl_flexcan2>; 347 xceiver-supply = <®_vcc_3v3>; 348 status = "okay"; 349}; 350 351&gpio1 { 352 pinctrl-names = "default"; 353 pinctrl-0 = <&pinctrl_gpio1>; 354 355 gpio-line-names = "GPO1", "GPO0", "", "GPO3", 356 "", "", "GPO2", "GPI0", 357 "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#", 358 "OTG_PWR", "", "GPI2", "GPI3", 359 "", "", "", "", 360 "", "", "", "", 361 "", "", "", "", 362 "", "", "", ""; 363}; 364 365&gpio2 { 366 pinctrl-names = "default"; 367 pinctrl-0 = <&pinctrl_hoggpio2>; 368 369 gpio-line-names = "", "", "", "", 370 "", "", "VCC12V_EN", "PERST#", 371 "", "", "CLKREQ#", "PEWAKE#", 372 "USDHC2_CD", "", "", "", 373 "", "", "", "V_SD3V3_EN", 374 "", "", "", "", 375 "", "", "", "", 376 "", "", "", ""; 377 378 perst-hog { 379 gpio-hog; 380 gpios = <7 0>; 381 output-high; 382 line-name = "PERST#"; 383 }; 384 385 clkreq-hog { 386 gpio-hog; 387 gpios = <10 0>; 388 input; 389 line-name = "CLKREQ#"; 390 }; 391 392 pewake-hog { 393 gpio-hog; 394 gpios = <11 0>; 395 input; 396 line-name = "PEWAKE#"; 397 }; 398}; 399 400&gpio3 { 401 gpio-line-names = "", "", "", "", 402 "", "", "", "", 403 "", "", "", "", 404 "", "", "LVDS0_RESET#", "", 405 "", "", "", "LVDS0_BLT_EN", 406 "LVDS0_PWR_EN", "", "", "", 407 "", "", "", "", 408 "", "", "", ""; 409}; 410 411&gpio4 { 412 pinctrl-names = "default"; 413 pinctrl-0 = <&pinctrl_gpio4>; 414 415 gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#", 416 "", "", "", "", 417 "", "", "", "", 418 "", "", "", "", 419 "", "", "DP_IRQ", "DSI_EN", 420 "HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "", 421 "", "", "", "FAN_PWR", 422 "RTC_EVENT#", "CODEC_RST#", "", ""; 423 424 pcie-refclkreq-hog { 425 gpio-hog; 426 gpios = <22 0>; 427 output-high; 428 line-name = "PCIE_REFCLK_OE#"; 429 }; 430}; 431 432&gpio5 { 433 gpio-line-names = "", "", "", "LED2", 434 "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC", 435 "CSI0_TRIGGER", "CSI0_ENABLE", "", "", 436 "", "ECSPI2_SS0", "", "", 437 "", "", "", "", 438 "", "", "", "", 439 "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B", 440 "", "", "", ""; 441}; 442 443&i2c2 { 444 clock-frequency = <384000>; 445 pinctrl-names = "default", "gpio"; 446 pinctrl-0 = <&pinctrl_i2c2>; 447 pinctrl-1 = <&pinctrl_i2c2_gpio>; 448 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 449 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 450 status = "okay"; 451 452 se97_1c: temperature-sensor@1c { 453 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 454 reg = <0x1c>; 455 }; 456 457 at24c02_54: eeprom@54 { 458 compatible = "nxp,se97b", "atmel,24c02"; 459 reg = <0x54>; 460 pagesize = <16>; 461 vcc-supply = <®_vcc_3v3>; 462 }; 463 464 pcieclk: clock-generator@6a { 465 compatible = "renesas,9fgv0241"; 466 reg = <0x6a>; 467 clocks = <&clk_xtal25>; 468 #clock-cells = <1>; 469 }; 470}; 471 472&i2c4 { 473 clock-frequency = <384000>; 474 pinctrl-names = "default", "gpio"; 475 pinctrl-0 = <&pinctrl_i2c4>; 476 pinctrl-1 = <&pinctrl_i2c4_gpio>; 477 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 478 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 479 status = "okay"; 480}; 481 482&i2c6 { 483 clock-frequency = <384000>; 484 pinctrl-names = "default", "gpio"; 485 pinctrl-0 = <&pinctrl_i2c6>; 486 pinctrl-1 = <&pinctrl_i2c6_gpio>; 487 scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 488 sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 489 status = "okay"; 490}; 491 492&pcf85063 { 493 /* RTC_EVENT# is connected on MBa8MPxL */ 494 pinctrl-names = "default"; 495 pinctrl-0 = <&pinctrl_pcf85063>; 496 interrupt-parent = <&gpio4>; 497 interrupts = <28 IRQ_TYPE_EDGE_FALLING>; 498}; 499 500&pcie_phy { 501 fsl,clkreq-unsupported; 502 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 503 clocks = <&pcieclk 0>; 504 clock-names = "ref"; 505 status = "okay"; 506}; 507 508&pcie { 509 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 510 <&clk IMX8MP_CLK_HSIO_AXI>, 511 <&clk IMX8MP_CLK_PCIE_ROOT>; 512 clock-names = "pcie", "pcie_bus", "pcie_aux"; 513 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 514 assigned-clock-rates = <10000000>; 515 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 516 status = "okay"; 517}; 518 519&pwm2 { 520 pinctrl-names = "default"; 521 pinctrl-0 = <&pinctrl_pwm2>; 522 status = "disabled"; 523}; 524 525&pwm3 { 526 pinctrl-names = "default"; 527 pinctrl-0 = <&pinctrl_pwm3>; 528 status = "okay"; 529}; 530 531&snvs_pwrkey { 532 status = "okay"; 533}; 534 535&uart1 { 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pinctrl_uart1>; 538 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 539 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 540 status = "okay"; 541}; 542 543&uart2 { 544 pinctrl-names = "default"; 545 pinctrl-0 = <&pinctrl_uart2>; 546 assigned-clocks = <&clk IMX8MP_CLK_UART2>; 547 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 548 status = "okay"; 549}; 550 551&uart3 { 552 pinctrl-names = "default"; 553 pinctrl-0 = <&pinctrl_uart3>; 554 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 555 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 556 status = "okay"; 557}; 558 559&uart4 { 560 /* console */ 561 pinctrl-names = "default"; 562 pinctrl-0 = <&pinctrl_uart4>; 563 status = "okay"; 564}; 565 566&usb3_0 { 567 pinctrl-names = "default"; 568 pinctrl-0 = <&pinctrl_usb0>; 569 fsl,over-current-active-low; 570 status = "okay"; 571}; 572 573&usb3_1 { 574 fsl,disable-port-power-control; 575 fsl,permanently-attached; 576 dr_mode = "host"; 577 status = "okay"; 578}; 579 580&usb3_phy0 { 581 vbus-supply = <®_vcc_5v0>; 582 status = "okay"; 583}; 584 585&usb3_phy1 { 586 vbus-supply = <®_vcc_5v0>; 587 status = "okay"; 588}; 589 590&usb_dwc3_0 { 591 /* dual role is implemented, but not a full featured OTG */ 592 hnp-disable; 593 srp-disable; 594 adp-disable; 595 dr_mode = "otg"; 596 usb-role-switch; 597 role-switch-default-mode = "peripheral"; 598 status = "okay"; 599 600 connector { 601 compatible = "gpio-usb-b-connector", "usb-b-connector"; 602 type = "micro"; 603 label = "X29"; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&pinctrl_usbcon0>; 606 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 607 }; 608}; 609 610&usb_dwc3_1 { 611 dr_mode = "host"; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&pinctrl_usbhub>; 616 status = "okay"; 617 618 hub_2_0: hub@1 { 619 compatible = "usb451,8142"; 620 reg = <1>; 621 peer-hub = <&hub_3_0>; 622 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 623 vdd-supply = <®_vcc_3v3>; 624 }; 625 626 hub_3_0: hub@2 { 627 compatible = "usb451,8140"; 628 reg = <2>; 629 peer-hub = <&hub_2_0>; 630 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 631 vdd-supply = <®_vcc_3v3>; 632 }; 633}; 634 635&usdhc2 { 636 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 637 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 638 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 639 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 640 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 641 vmmc-supply = <®_usdhc2_vmmc>; 642 no-mmc; 643 no-sdio; 644 disable-wp; 645 bus-width = <4>; 646 status = "okay"; 647}; 648 649&iomuxc { 650 pinctrl_backlight: backlightgrp { 651 fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x14>; 652 }; 653 654 pinctrl_flexcan1: flexcan1grp { 655 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>, 656 <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>; 657 }; 658 659 pinctrl_flexcan2: flexcan2grp { 660 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>, 661 <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>; 662 }; 663 664 /* only on X57, primary used as CSI0 control signals */ 665 pinctrl_ecspi1: ecspi1grp { 666 fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>, 667 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>, 668 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>, 669 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>; 670 }; 671 672 /* on X63 and optionally on X57, can also be used as CSI1 control signals */ 673 pinctrl_ecspi2: ecspi2grp { 674 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c0>, 675 <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1c0>, 676 <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1c0>, 677 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c0>; 678 }; 679 680 pinctrl_ecspi3: ecspi3grp { 681 fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x1c0>, 682 <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x1c0>, 683 <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>, 684 <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0>; 685 }; 686 687 pinctrl_eqos: eqosgrp { 688 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>, 689 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>, 690 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, 691 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, 692 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, 693 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, 694 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, 695 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, 696 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>, 697 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>, 698 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>, 699 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>, 700 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>, 701 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>; 702 }; 703 704 pinctrl_eqos_event: eqosevtgrp { 705 fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x100>, 706 <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1c0>; 707 }; 708 709 pinctrl_eqos_phy: eqosphygrp { 710 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>, 711 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>; 712 }; 713 714 pinctrl_fec: fecgrp { 715 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>, 716 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>, 717 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, 718 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, 719 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, 720 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, 721 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, 722 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, 723 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>, 724 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>, 725 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>, 726 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>, 727 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>, 728 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>; 729 }; 730 731 pinctrl_fec_event: fecevtgrp { 732 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x100>, 733 <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1c0>; 734 }; 735 736 pinctrl_fec_phy: fecphygrp { 737 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>, 738 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>; 739 }; 740 741 pinctrl_fec_phyalt: fecphyaltgrp { 742 fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x180>, 743 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>; 744 }; 745 746 pinctrl_gpiobutton: gpiobuttongrp { 747 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>, 748 <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x10>; 749 }; 750 751 pinctrl_gpioled: gpioledgrp { 752 fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x14>, 753 <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x14>, 754 <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x14>; 755 }; 756 757 pinctrl_gpio1: gpio1grp { 758 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>, 759 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>, 760 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>, 761 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>, 762 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>, 763 <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>, 764 <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>, 765 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>; 766 }; 767 768 pinctrl_gpio4: gpio4grp { 769 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x180>, 770 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x180>; 771 }; 772 773 pinctrl_hdmi: hdmigrp { 774 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>, 775 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>, 776 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>, 777 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>; 778 }; 779 780 pinctrl_hoggpio2: hoggpio2grp { 781 fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x140>, 782 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140>, 783 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>; 784 }; 785 786 pinctrl_i2c2: i2c2grp { 787 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>, 788 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>; 789 }; 790 791 pinctrl_i2c2_gpio: i2c2-gpiogrp { 792 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>, 793 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>; 794 }; 795 796 pinctrl_i2c4: i2c4grp { 797 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e2>, 798 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e2>; 799 }; 800 801 pinctrl_i2c4_gpio: i2c4-gpiogrp { 802 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001e2>, 803 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001e2>; 804 }; 805 806 pinctrl_i2c6: i2c6grp { 807 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>, 808 <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>; 809 }; 810 811 pinctrl_i2c6_gpio: i2c6-gpiogrp { 812 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>, 813 <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>; 814 }; 815 816 pinctrl_lvdsdisplay: lvdsdisplaygrp { 817 fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */ 818 }; 819 820 pinctrl_pcf85063: pcf85063grp { 821 fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x80>; 822 }; 823 824 /* LVDS Backlight */ 825 pinctrl_pwm2: pwm2grp { 826 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>; 827 }; 828 829 /* FAN */ 830 pinctrl_pwm3: pwm3grp { 831 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>; 832 }; 833 834 pinctrl_pwmfan: pwmfangrp { 835 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>; /* FAN RPM */ 836 }; 837 838 pinctrl_reg12v0: reg12v0grp { 839 fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */ 840 }; 841 842 pinctrl_regpwmfan: regpwmfangrp { 843 fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x80>; 844 }; 845 846 /* X61 */ 847 pinctrl_uart1: uart1grp { 848 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>, 849 <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140>; 850 }; 851 852 /* X61 */ 853 pinctrl_uart2: uart2grp { 854 fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x140>, 855 <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x140>; 856 }; 857 858 pinctrl_uart3: uart3grp { 859 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>, 860 <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>; 861 }; 862 863 pinctrl_uart4: uart4grp { 864 fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>, 865 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>; 866 }; 867 868 pinctrl_usb0: usb0grp { 869 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0>, 870 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x1c0>; 871 }; 872 873 pinctrl_usbcon0: usb0congrp { 874 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>; 875 }; 876 877 pinctrl_usbhub: usbhubgrp { 878 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x10>; 879 }; 880 881 pinctrl_usdhc2: usdhc2grp { 882 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>, 883 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>, 884 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 885 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 886 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 887 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, 888 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 889 }; 890 891 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 892 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 893 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 894 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 895 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 896 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 897 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 898 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 899 }; 900 901 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 902 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 903 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 904 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 905 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 906 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 907 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 908 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 909 }; 910 911 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 912 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>; 913 }; 914}; 915