1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2021-2022 TQ-Systems GmbH 4 * Author: Alexander Stein <alexander.stein@tq-group.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/leds/common.h> 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12#include <dt-bindings/pwm/pwm.h> 13#include "imx8mp-tqma8mpql.dtsi" 14 15/ { 16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL"; 17 compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; 18 19 chosen { 20 stdout-path = &uart4; 21 }; 22 23 iio-hwmon { 24 compatible = "iio-hwmon"; 25 io-channels = <&adc 0>, <&adc 1>; 26 }; 27 28 aliases { 29 mmc0 = &usdhc3; 30 mmc1 = &usdhc2; 31 mmc2 = &usdhc1; 32 rtc0 = &pcf85063; 33 rtc1 = &snvs_rtc; 34 spi0 = &flexspi; 35 spi1 = &ecspi1; 36 spi2 = &ecspi2; 37 spi3 = &ecspi3; 38 }; 39 40 backlight_lvds: backlight { 41 compatible = "pwm-backlight"; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_backlight>; 44 pwms = <&pwm2 0 5000000 0>; 45 brightness-levels = <0 4 8 16 32 64 128 255>; 46 default-brightness-level = <7>; 47 power-supply = <®_vcc_12v0>; 48 enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 49 status = "disabled"; 50 }; 51 52 clk_xtal25: clk-xtal25 { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <25000000>; 56 }; 57 58 fan0: pwm-fan { 59 compatible = "pwm-fan"; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_pwmfan>; 62 fan-supply = <®_pwm_fan>; 63 #cooling-cells = <2>; 64 /* typical 25 kHz -> 40.000 nsec */ 65 pwms = <&pwm3 0 40000 PWM_POLARITY_INVERTED>; 66 cooling-levels = <0 32 64 128 196 240>; 67 pulses-per-revolution = <2>; 68 interrupt-parent = <&gpio5>; 69 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 70 status = "disabled"; 71 }; 72 73 gpio-keys { 74 compatible = "gpio-keys"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_gpiobutton>; 77 autorepeat; 78 79 switch-1 { 80 label = "S12"; 81 linux,code = <BTN_0>; 82 gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; 83 }; 84 85 switch-2 { 86 label = "S13"; 87 linux,code = <BTN_1>; 88 gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; 89 }; 90 }; 91 92 gpio-leds { 93 compatible = "gpio-leds"; 94 pinctrl-names = "default"; 95 pinctrl-0 = <&pinctrl_gpioled>; 96 97 led-0 { 98 color = <LED_COLOR_ID_GREEN>; 99 function = LED_FUNCTION_STATUS; 100 function-enumerator = <0>; 101 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 102 linux,default-trigger = "default-on"; 103 }; 104 105 led-1 { 106 color = <LED_COLOR_ID_GREEN>; 107 function = LED_FUNCTION_HEARTBEAT; 108 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 109 linux,default-trigger = "heartbeat"; 110 }; 111 112 led-2 { 113 color = <LED_COLOR_ID_YELLOW>; 114 function = LED_FUNCTION_STATUS; 115 function-enumerator = <1>; 116 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 117 }; 118 }; 119 120 display: display { 121 /* 122 * Display is not fixed, so compatible has to be added from 123 * DT overlay 124 */ 125 pinctrl-names = "default"; 126 pinctrl-0 = <&pinctrl_lvdsdisplay>; 127 power-supply = <®_vcc_3v3>; 128 enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; 129 backlight = <&backlight_lvds>; 130 status = "disabled"; 131 }; 132 133 reg_pwm_fan: regulator-pwm-fan { 134 compatible = "regulator-fixed"; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_regpwmfan>; 137 regulator-name = "FAN_PWR"; 138 regulator-min-microvolt = <12000000>; 139 regulator-max-microvolt = <12000000>; 140 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 141 enable-active-high; 142 vin-supply = <®_vcc_12v0>; 143 }; 144 145 reg_usdhc2_vmmc: regulator-usdhc2 { 146 compatible = "regulator-fixed"; 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 149 regulator-name = "VSD_3V3"; 150 regulator-min-microvolt = <3300000>; 151 regulator-max-microvolt = <3300000>; 152 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 153 enable-active-high; 154 startup-delay-us = <100>; 155 off-on-delay-us = <12000>; 156 }; 157 158 reg_vcc_12v0: regulator-12v0 { 159 compatible = "regulator-fixed"; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_reg12v0>; 162 regulator-name = "VCC_12V0"; 163 regulator-min-microvolt = <12000000>; 164 regulator-max-microvolt = <12000000>; 165 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 166 enable-active-high; 167 }; 168 169 reg_vcc_3v3: regulator-3v3 { 170 compatible = "regulator-fixed"; 171 regulator-name = "VCC_3V3"; 172 regulator-min-microvolt = <3300000>; 173 regulator-max-microvolt = <3300000>; 174 }; 175 176 reg_vcc_5v0: regulator-5v0 { 177 compatible = "regulator-fixed"; 178 regulator-name = "VCC_5V0"; 179 regulator-min-microvolt = <5000000>; 180 regulator-max-microvolt = <5000000>; 181 }; 182 183 reserved-memory { 184 #address-cells = <2>; 185 #size-cells = <2>; 186 ranges; 187 188 ocram: ocram@900000 { 189 no-map; 190 reg = <0 0x900000 0 0x70000>; 191 }; 192 193 /* global autoconfigured region for contiguous allocations */ 194 linux,cma { 195 compatible = "shared-dma-pool"; 196 reusable; 197 size = <0 0x38000000>; 198 alloc-ranges = <0 0x40000000 0 0xB0000000>; 199 linux,cma-default; 200 }; 201 }; 202 203 thermal-zones { 204 soc-thermal { 205 trips { 206 soc_active0: trip-active0 { 207 temperature = <40000>; 208 hysteresis = <5000>; 209 type = "active"; 210 }; 211 212 soc_active1: trip-active1 { 213 temperature = <48000>; 214 hysteresis = <3000>; 215 type = "active"; 216 }; 217 218 soc_active2: trip-active2 { 219 temperature = <60000>; 220 hysteresis = <10000>; 221 type = "active"; 222 }; 223 }; 224 225 cooling-maps { 226 map1 { 227 trip = <&soc_active0>; 228 cooling-device = <&fan0 1 1>; 229 }; 230 231 map2 { 232 trip = <&soc_active1>; 233 cooling-device = <&fan0 2 2>; 234 }; 235 236 map3 { 237 trip = <&soc_active2>; 238 cooling-device = <&fan0 3 3>; 239 }; 240 }; 241 }; 242 }; 243}; 244 245&ecspi1 { 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_ecspi1>; 248 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 249 status = "okay"; 250}; 251 252&ecspi2 { 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_ecspi2>; 255 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 256 status = "okay"; 257}; 258 259&ecspi3 { 260 pinctrl-names = "default"; 261 pinctrl-0 = <&pinctrl_ecspi3>; 262 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 263 status = "okay"; 264 265 adc: adc@0 { 266 reg = <0>; 267 compatible = "microchip,mcp3202"; 268 /* 100 ksps * 18 */ 269 spi-max-frequency = <1800000>; 270 vref-supply = <®_vcc_3v3>; 271 #io-channel-cells = <1>; 272 }; 273}; 274 275&eqos { 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>; 278 phy-mode = "rgmii-id"; 279 phy-handle = <ðphy3>; 280 status = "okay"; 281 282 mdio { 283 compatible = "snps,dwmac-mdio"; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 287 ethphy3: ethernet-phy@3 { 288 compatible = "ethernet-phy-ieee802.3-c22"; 289 reg = <3>; 290 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 291 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 292 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 293 ti,dp83867-rxctrl-strap-quirk; 294 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 295 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 296 reset-assert-us = <500000>; 297 reset-deassert-us = <50000>; 298 enet-phy-lane-no-swap; 299 interrupt-parent = <&gpio4>; 300 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 301 }; 302 }; 303}; 304 305&fec { 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>; 308 phy-mode = "rgmii-id"; 309 phy-handle = <ðphy0>; 310 fsl,magic-packet; 311 status = "okay"; 312 313 mdio { 314 #address-cells = <1>; 315 #size-cells = <0>; 316 317 ethphy0: ethernet-phy@0 { 318 compatible = "ethernet-phy-ieee802.3-c22"; 319 reg = <0>; 320 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 321 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 322 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 323 ti,dp83867-rxctrl-strap-quirk; 324 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 325 reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 326 reset-assert-us = <500000>; 327 reset-deassert-us = <50000>; 328 enet-phy-lane-no-swap; 329 interrupt-parent = <&gpio4>; 330 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 331 }; 332 }; 333}; 334 335&flexcan1 { 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_flexcan1>; 338 xceiver-supply = <®_vcc_3v3>; 339 status = "okay"; 340}; 341 342&flexcan2 { 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pinctrl_flexcan2>; 345 xceiver-supply = <®_vcc_3v3>; 346 status = "okay"; 347}; 348 349&gpio1 { 350 pinctrl-names = "default"; 351 pinctrl-0 = <&pinctrl_gpio1>; 352 353 gpio-line-names = "GPO1", "GPO0", "", "GPO3", 354 "", "", "GPO2", "GPI0", 355 "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#", 356 "OTG_PWR", "", "GPI2", "GPI3", 357 "", "", "", "", 358 "", "", "", "", 359 "", "", "", "", 360 "", "", "", ""; 361}; 362 363&gpio2 { 364 pinctrl-names = "default"; 365 pinctrl-0 = <&pinctrl_hoggpio2>; 366 367 gpio-line-names = "", "", "", "", 368 "", "", "VCC12V_EN", "PERST#", 369 "", "", "CLKREQ#", "PEWAKE#", 370 "USDHC2_CD", "", "", "", 371 "", "", "", "V_SD3V3_EN", 372 "", "", "", "", 373 "", "", "", "", 374 "", "", "", ""; 375 376 perst-hog { 377 gpio-hog; 378 gpios = <7 0>; 379 output-high; 380 line-name = "PERST#"; 381 }; 382 383 clkreq-hog { 384 gpio-hog; 385 gpios = <10 0>; 386 input; 387 line-name = "CLKREQ#"; 388 }; 389 390 pewake-hog { 391 gpio-hog; 392 gpios = <11 0>; 393 input; 394 line-name = "PEWAKE#"; 395 }; 396}; 397 398&gpio3 { 399 gpio-line-names = "", "", "", "", 400 "", "", "", "", 401 "", "", "", "", 402 "", "", "LVDS0_RESET#", "", 403 "", "", "", "LVDS0_BLT_EN", 404 "LVDS0_PWR_EN", "", "", "", 405 "", "", "", "", 406 "", "", "", ""; 407}; 408 409&gpio4 { 410 pinctrl-names = "default"; 411 pinctrl-0 = <&pinctrl_gpio4>; 412 413 gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#", 414 "", "", "", "", 415 "", "", "", "", 416 "", "", "", "", 417 "", "", "DP_IRQ", "DSI_EN", 418 "HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "", 419 "", "", "", "FAN_PWR", 420 "RTC_EVENT#", "CODEC_RST#", "", ""; 421 422 pcie-refclkreq-hog { 423 gpio-hog; 424 gpios = <22 0>; 425 output-high; 426 line-name = "PCIE_REFCLK_OE#"; 427 }; 428}; 429 430&gpio5 { 431 gpio-line-names = "", "", "", "LED2", 432 "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC", 433 "CSI0_TRIGGER", "CSI0_ENABLE", "", "", 434 "", "ECSPI2_SS0", "", "", 435 "", "", "", "", 436 "", "", "", "", 437 "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B", 438 "", "", "", ""; 439}; 440 441&i2c2 { 442 clock-frequency = <384000>; 443 pinctrl-names = "default", "gpio"; 444 pinctrl-0 = <&pinctrl_i2c2>; 445 pinctrl-1 = <&pinctrl_i2c2_gpio>; 446 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 447 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 448 status = "okay"; 449 450 /* NXP SE97BTP with temperature sensor + eeprom */ 451 se97_1c: temperature-sensor-eeprom@1c { 452 compatible = "nxp,se97", "jedec,jc-42.4-temp"; 453 reg = <0x1c>; 454 }; 455 456 at24c02_54: eeprom@54 { 457 compatible = "nxp,se97b", "atmel,24c02"; 458 reg = <0x54>; 459 pagesize = <16>; 460 vcc-supply = <®_vcc_3v3>; 461 }; 462 463 pcieclk: clock-generator@6a { 464 compatible = "renesas,9fgv0241"; 465 reg = <0x6a>; 466 clocks = <&clk_xtal25>; 467 #clock-cells = <1>; 468 }; 469}; 470 471&i2c4 { 472 clock-frequency = <384000>; 473 pinctrl-names = "default", "gpio"; 474 pinctrl-0 = <&pinctrl_i2c4>; 475 pinctrl-1 = <&pinctrl_i2c4_gpio>; 476 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 477 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 478 status = "okay"; 479}; 480 481&i2c6 { 482 clock-frequency = <384000>; 483 pinctrl-names = "default", "gpio"; 484 pinctrl-0 = <&pinctrl_i2c6>; 485 pinctrl-1 = <&pinctrl_i2c6_gpio>; 486 scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 487 sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 488 status = "okay"; 489}; 490 491&pcf85063 { 492 /* RTC_EVENT# is connected on MBa8MPxL */ 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pinctrl_pcf85063>; 495 interrupt-parent = <&gpio4>; 496 interrupts = <28 IRQ_TYPE_EDGE_FALLING>; 497}; 498 499&pcie_phy { 500 fsl,clkreq-unsupported; 501 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 502 clocks = <&pcieclk 0>; 503 clock-names = "ref"; 504 status = "okay"; 505}; 506 507&pcie { 508 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 509 <&clk IMX8MP_CLK_HSIO_AXI>, 510 <&clk IMX8MP_CLK_PCIE_ROOT>; 511 clock-names = "pcie", "pcie_bus", "pcie_aux"; 512 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 513 assigned-clock-rates = <10000000>; 514 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 515 status = "okay"; 516}; 517 518&pwm2 { 519 pinctrl-names = "default"; 520 pinctrl-0 = <&pinctrl_pwm2>; 521 status = "disabled"; 522}; 523 524&pwm3 { 525 pinctrl-names = "default"; 526 pinctrl-0 = <&pinctrl_pwm3>; 527 status = "okay"; 528}; 529 530&snvs_pwrkey { 531 status = "okay"; 532}; 533 534&uart1 { 535 pinctrl-names = "default"; 536 pinctrl-0 = <&pinctrl_uart1>; 537 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 538 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 539 status = "okay"; 540}; 541 542&uart2 { 543 pinctrl-names = "default"; 544 pinctrl-0 = <&pinctrl_uart2>; 545 assigned-clocks = <&clk IMX8MP_CLK_UART2>; 546 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 547 status = "okay"; 548}; 549 550&uart3 { 551 pinctrl-names = "default"; 552 pinctrl-0 = <&pinctrl_uart3>; 553 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 554 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 555 status = "okay"; 556}; 557 558&uart4 { 559 /* console */ 560 pinctrl-names = "default"; 561 pinctrl-0 = <&pinctrl_uart4>; 562 status = "okay"; 563}; 564 565&usb3_0 { 566 pinctrl-names = "default"; 567 pinctrl-0 = <&pinctrl_usb0>; 568 fsl,over-current-active-low; 569 status = "okay"; 570}; 571 572&usb3_1 { 573 fsl,disable-port-power-control; 574 fsl,permanently-attached; 575 dr_mode = "host"; 576 status = "okay"; 577}; 578 579&usb3_phy0 { 580 vbus-supply = <®_vcc_5v0>; 581 status = "okay"; 582}; 583 584&usb3_phy1 { 585 vbus-supply = <®_vcc_5v0>; 586 status = "okay"; 587}; 588 589&usb_dwc3_0 { 590 /* dual role is implemented, but not a full featured OTG */ 591 hnp-disable; 592 srp-disable; 593 adp-disable; 594 dr_mode = "otg"; 595 usb-role-switch; 596 role-switch-default-mode = "peripheral"; 597 status = "okay"; 598 599 connector { 600 compatible = "gpio-usb-b-connector", "usb-b-connector"; 601 type = "micro"; 602 label = "X29"; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&pinctrl_usbcon0>; 605 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 606 }; 607}; 608 609&usb_dwc3_1 { 610 dr_mode = "host"; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 pinctrl-names = "default"; 614 pinctrl-0 = <&pinctrl_usbhub>; 615 status = "okay"; 616 617 hub_2_0: hub@1 { 618 compatible = "usb451,8142"; 619 reg = <1>; 620 peer-hub = <&hub_3_0>; 621 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 622 vdd-supply = <®_vcc_3v3>; 623 }; 624 625 hub_3_0: hub@2 { 626 compatible = "usb451,8140"; 627 reg = <2>; 628 peer-hub = <&hub_2_0>; 629 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 630 vdd-supply = <®_vcc_3v3>; 631 }; 632}; 633 634&usdhc2 { 635 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 636 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 637 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 638 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 639 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 640 vmmc-supply = <®_usdhc2_vmmc>; 641 no-mmc; 642 no-sdio; 643 disable-wp; 644 bus-width = <4>; 645 status = "okay"; 646}; 647 648&iomuxc { 649 pinctrl_backlight: backlightgrp { 650 fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x14>; 651 }; 652 653 pinctrl_flexcan1: flexcan1grp { 654 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>, 655 <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>; 656 }; 657 658 pinctrl_flexcan2: flexcan2grp { 659 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>, 660 <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>; 661 }; 662 663 /* only on X57, primary used as CSI0 control signals */ 664 pinctrl_ecspi1: ecspi1grp { 665 fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>, 666 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>, 667 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>, 668 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>; 669 }; 670 671 /* on X63 and optionally on X57, can also be used as CSI1 control signals */ 672 pinctrl_ecspi2: ecspi2grp { 673 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c0>, 674 <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1c0>, 675 <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1c0>, 676 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c0>; 677 }; 678 679 pinctrl_ecspi3: ecspi3grp { 680 fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x1c0>, 681 <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x1c0>, 682 <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>, 683 <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0>; 684 }; 685 686 pinctrl_eqos: eqosgrp { 687 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>, 688 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>, 689 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, 690 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, 691 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, 692 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, 693 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, 694 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, 695 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>, 696 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>, 697 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>, 698 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>, 699 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>, 700 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>; 701 }; 702 703 pinctrl_eqos_event: eqosevtgrp { 704 fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x100>, 705 <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1c0>; 706 }; 707 708 pinctrl_eqos_phy: eqosphygrp { 709 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>, 710 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>; 711 }; 712 713 pinctrl_fec: fecgrp { 714 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>, 715 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>, 716 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, 717 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, 718 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, 719 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, 720 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, 721 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, 722 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>, 723 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>, 724 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>, 725 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>, 726 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>, 727 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>; 728 }; 729 730 pinctrl_fec_event: fecevtgrp { 731 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x100>, 732 <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1c0>; 733 }; 734 735 pinctrl_fec_phy: fecphygrp { 736 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>, 737 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>; 738 }; 739 740 pinctrl_fec_phyalt: fecphyaltgrp { 741 fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x180>, 742 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>; 743 }; 744 745 pinctrl_gpiobutton: gpiobuttongrp { 746 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>, 747 <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x10>; 748 }; 749 750 pinctrl_gpioled: gpioledgrp { 751 fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x14>, 752 <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x14>, 753 <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x14>; 754 }; 755 756 pinctrl_gpio1: gpio1grp { 757 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>, 758 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>, 759 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>, 760 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>, 761 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>, 762 <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>, 763 <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>, 764 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>; 765 }; 766 767 pinctrl_gpio4: gpio4grp { 768 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x180>, 769 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x180>; 770 }; 771 772 pinctrl_hdmi: hdmigrp { 773 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>, 774 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>, 775 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>, 776 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>; 777 }; 778 779 pinctrl_hoggpio2: hoggpio2grp { 780 fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x140>, 781 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140>, 782 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>; 783 }; 784 785 pinctrl_i2c2: i2c2grp { 786 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>, 787 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>; 788 }; 789 790 pinctrl_i2c2_gpio: i2c2-gpiogrp { 791 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>, 792 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>; 793 }; 794 795 pinctrl_i2c4: i2c4grp { 796 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e2>, 797 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e2>; 798 }; 799 800 pinctrl_i2c4_gpio: i2c4-gpiogrp { 801 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001e2>, 802 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001e2>; 803 }; 804 805 pinctrl_i2c6: i2c6grp { 806 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>, 807 <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>; 808 }; 809 810 pinctrl_i2c6_gpio: i2c6-gpiogrp { 811 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>, 812 <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>; 813 }; 814 815 pinctrl_lvdsdisplay: lvdsdisplaygrp { 816 fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */ 817 }; 818 819 pinctrl_pcf85063: pcf85063grp { 820 fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x80>; 821 }; 822 823 /* LVDS Backlight */ 824 pinctrl_pwm2: pwm2grp { 825 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>; 826 }; 827 828 /* FAN */ 829 pinctrl_pwm3: pwm3grp { 830 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>; 831 }; 832 833 pinctrl_pwmfan: pwmfangrp { 834 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>; /* FAN RPM */ 835 }; 836 837 pinctrl_reg12v0: reg12v0grp { 838 fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */ 839 }; 840 841 pinctrl_regpwmfan: regpwmfangrp { 842 fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x80>; 843 }; 844 845 /* X61 */ 846 pinctrl_uart1: uart1grp { 847 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>, 848 <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140>; 849 }; 850 851 /* X61 */ 852 pinctrl_uart2: uart2grp { 853 fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x140>, 854 <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x140>; 855 }; 856 857 pinctrl_uart3: uart3grp { 858 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>, 859 <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>; 860 }; 861 862 pinctrl_uart4: uart4grp { 863 fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>, 864 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>; 865 }; 866 867 pinctrl_usb0: usb0grp { 868 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0>, 869 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x1c0>; 870 }; 871 872 pinctrl_usbcon0: usb0congrp { 873 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>; 874 }; 875 876 pinctrl_usbhub: usbhubgrp { 877 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x10>; 878 }; 879 880 pinctrl_usdhc2: usdhc2grp { 881 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>, 882 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>, 883 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 884 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 885 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 886 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, 887 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 888 }; 889 890 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 891 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 892 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 893 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 894 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 895 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 896 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 897 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 898 }; 899 900 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 901 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 902 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 903 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 904 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 905 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 906 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 907 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 908 }; 909 910 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 911 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>; 912 }; 913}; 914