1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2021-2022 TQ-Systems GmbH 4 * Author: Alexander Stein <alexander.stein@tq-group.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/leds/common.h> 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12#include <dt-bindings/pwm/pwm.h> 13#include "imx8mp-tqma8mpql.dtsi" 14 15/ { 16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL"; 17 compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; 18 19 chosen { 20 stdout-path = &uart4; 21 }; 22 23 iio-hwmon { 24 compatible = "iio-hwmon"; 25 io-channels = <&adc 0>, <&adc 1>; 26 }; 27 28 aliases { 29 mmc0 = &usdhc3; 30 mmc1 = &usdhc2; 31 mmc2 = &usdhc1; 32 rtc0 = &pcf85063; 33 rtc1 = &snvs_rtc; 34 spi0 = &flexspi; 35 spi1 = &ecspi1; 36 spi2 = &ecspi2; 37 spi3 = &ecspi3; 38 }; 39 40 backlight_lvds: backlight { 41 compatible = "pwm-backlight"; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_backlight>; 44 pwms = <&pwm2 0 5000000 0>; 45 brightness-levels = <0 4 8 16 32 64 128 255>; 46 default-brightness-level = <7>; 47 power-supply = <®_vcc_12v0>; 48 enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 49 status = "disabled"; 50 }; 51 52 clk_xtal25: clk-xtal25 { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <25000000>; 56 }; 57 58 fan0: pwm-fan { 59 compatible = "pwm-fan"; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_pwmfan>; 62 fan-supply = <®_pwm_fan>; 63 #cooling-cells = <2>; 64 /* typical 25 kHz -> 40.000 nsec */ 65 pwms = <&pwm3 0 40000 PWM_POLARITY_INVERTED>; 66 cooling-levels = <0 32 64 128 196 240>; 67 pulses-per-revolution = <2>; 68 interrupt-parent = <&gpio5>; 69 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 70 status = "disabled"; 71 }; 72 73 gpio-keys { 74 compatible = "gpio-keys"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_gpiobutton>; 77 autorepeat; 78 79 switch-1 { 80 label = "S12"; 81 linux,code = <BTN_0>; 82 gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; 83 wakeup-source; 84 }; 85 86 switch-2 { 87 label = "S13"; 88 linux,code = <BTN_1>; 89 gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; 90 wakeup-source; 91 }; 92 }; 93 94 gpio-leds { 95 compatible = "gpio-leds"; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_gpioled>; 98 99 led-0 { 100 color = <LED_COLOR_ID_GREEN>; 101 function = LED_FUNCTION_STATUS; 102 function-enumerator = <0>; 103 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 104 linux,default-trigger = "default-on"; 105 }; 106 107 led-1 { 108 color = <LED_COLOR_ID_GREEN>; 109 function = LED_FUNCTION_HEARTBEAT; 110 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 111 linux,default-trigger = "heartbeat"; 112 }; 113 114 led-2 { 115 color = <LED_COLOR_ID_YELLOW>; 116 function = LED_FUNCTION_STATUS; 117 function-enumerator = <1>; 118 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 119 }; 120 }; 121 122 display: display { 123 /* 124 * Display is not fixed, so compatible has to be added from 125 * DT overlay 126 */ 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_lvdsdisplay>; 129 power-supply = <®_vcc_3v3>; 130 enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; 131 backlight = <&backlight_lvds>; 132 status = "disabled"; 133 }; 134 135 reg_pwm_fan: regulator-pwm-fan { 136 compatible = "regulator-fixed"; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pinctrl_regpwmfan>; 139 regulator-name = "FAN_PWR"; 140 regulator-min-microvolt = <12000000>; 141 regulator-max-microvolt = <12000000>; 142 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 143 enable-active-high; 144 vin-supply = <®_vcc_12v0>; 145 }; 146 147 reg_usdhc2_vmmc: regulator-usdhc2 { 148 compatible = "regulator-fixed"; 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 151 regulator-name = "VSD_3V3"; 152 regulator-min-microvolt = <3300000>; 153 regulator-max-microvolt = <3300000>; 154 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 155 enable-active-high; 156 startup-delay-us = <100>; 157 off-on-delay-us = <12000>; 158 }; 159 160 reg_vcc_12v0: regulator-12v0 { 161 compatible = "regulator-fixed"; 162 pinctrl-names = "default"; 163 pinctrl-0 = <&pinctrl_reg12v0>; 164 regulator-name = "VCC_12V0"; 165 regulator-min-microvolt = <12000000>; 166 regulator-max-microvolt = <12000000>; 167 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 168 enable-active-high; 169 }; 170 171 reg_vcc_1v8: regulator-1v8 { 172 compatible = "regulator-fixed"; 173 regulator-name = "VCC_1V8"; 174 regulator-min-microvolt = <1800000>; 175 regulator-max-microvolt = <1800000>; 176 }; 177 178 reg_vcc_3v3: regulator-3v3 { 179 compatible = "regulator-fixed"; 180 regulator-name = "VCC_3V3"; 181 regulator-min-microvolt = <3300000>; 182 regulator-max-microvolt = <3300000>; 183 }; 184 185 reg_vcc_5v0: regulator-5v0 { 186 compatible = "regulator-fixed"; 187 regulator-name = "VCC_5V0"; 188 regulator-min-microvolt = <5000000>; 189 regulator-max-microvolt = <5000000>; 190 }; 191 192 reserved-memory { 193 #address-cells = <2>; 194 #size-cells = <2>; 195 ranges; 196 197 ocram: ocram@900000 { 198 no-map; 199 reg = <0 0x900000 0 0x70000>; 200 }; 201 202 /* global autoconfigured region for contiguous allocations */ 203 linux,cma { 204 compatible = "shared-dma-pool"; 205 reusable; 206 size = <0 0x38000000>; 207 alloc-ranges = <0 0x40000000 0 0xB0000000>; 208 linux,cma-default; 209 }; 210 }; 211 212 sound { 213 compatible = "fsl,imx-audio-tlv320aic32x4"; 214 model = "tq-tlv320aic32x"; 215 audio-cpu = <&sai3>; 216 audio-codec = <&tlv320aic3x04>; 217 }; 218 219 thermal-zones { 220 soc-thermal { 221 trips { 222 soc_active0: trip-active0 { 223 temperature = <40000>; 224 hysteresis = <5000>; 225 type = "active"; 226 }; 227 228 soc_active1: trip-active1 { 229 temperature = <48000>; 230 hysteresis = <3000>; 231 type = "active"; 232 }; 233 234 soc_active2: trip-active2 { 235 temperature = <60000>; 236 hysteresis = <10000>; 237 type = "active"; 238 }; 239 }; 240 241 cooling-maps { 242 map1 { 243 trip = <&soc_active0>; 244 cooling-device = <&fan0 1 1>; 245 }; 246 247 map2 { 248 trip = <&soc_active1>; 249 cooling-device = <&fan0 2 2>; 250 }; 251 252 map3 { 253 trip = <&soc_active2>; 254 cooling-device = <&fan0 3 3>; 255 }; 256 }; 257 }; 258 }; 259}; 260 261&ecspi1 { 262 pinctrl-names = "default"; 263 pinctrl-0 = <&pinctrl_ecspi1>; 264 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 265 status = "okay"; 266}; 267 268&ecspi2 { 269 pinctrl-names = "default"; 270 pinctrl-0 = <&pinctrl_ecspi2>; 271 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 272 status = "okay"; 273}; 274 275&ecspi3 { 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_ecspi3>; 278 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 279 status = "okay"; 280 281 adc: adc@0 { 282 reg = <0>; 283 compatible = "microchip,mcp3202"; 284 /* 100 ksps * 18 */ 285 spi-max-frequency = <1800000>; 286 vref-supply = <®_vcc_3v3>; 287 #io-channel-cells = <1>; 288 }; 289}; 290 291&eqos { 292 pinctrl-names = "default"; 293 pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>; 294 phy-mode = "rgmii-id"; 295 phy-handle = <ðphy3>; 296 status = "okay"; 297 298 mdio { 299 compatible = "snps,dwmac-mdio"; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 303 ethphy3: ethernet-phy@3 { 304 compatible = "ethernet-phy-ieee802.3-c22"; 305 reg = <3>; 306 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 307 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 308 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 309 ti,dp83867-rxctrl-strap-quirk; 310 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 311 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 312 reset-assert-us = <500000>; 313 reset-deassert-us = <50000>; 314 enet-phy-lane-no-swap; 315 interrupt-parent = <&gpio4>; 316 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 317 }; 318 }; 319}; 320 321&fec { 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>; 324 phy-mode = "rgmii-id"; 325 phy-handle = <ðphy0>; 326 fsl,magic-packet; 327 status = "okay"; 328 329 mdio { 330 #address-cells = <1>; 331 #size-cells = <0>; 332 333 ethphy0: ethernet-phy@0 { 334 compatible = "ethernet-phy-ieee802.3-c22"; 335 reg = <0>; 336 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 337 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 338 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 339 ti,dp83867-rxctrl-strap-quirk; 340 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 341 reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 342 reset-assert-us = <500000>; 343 reset-deassert-us = <50000>; 344 enet-phy-lane-no-swap; 345 interrupt-parent = <&gpio4>; 346 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 347 }; 348 }; 349}; 350 351&flexcan1 { 352 pinctrl-names = "default"; 353 pinctrl-0 = <&pinctrl_flexcan1>; 354 xceiver-supply = <®_vcc_3v3>; 355 status = "okay"; 356}; 357 358&flexcan2 { 359 pinctrl-names = "default"; 360 pinctrl-0 = <&pinctrl_flexcan2>; 361 xceiver-supply = <®_vcc_3v3>; 362 status = "okay"; 363}; 364 365&gpio1 { 366 pinctrl-names = "default"; 367 pinctrl-0 = <&pinctrl_gpio1>; 368 369 gpio-line-names = "GPO1", "GPO0", "", "GPO3", 370 "", "", "GPO2", "GPI0", 371 "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#", 372 "OTG_PWR", "", "GPI2", "GPI3", 373 "", "", "", "", 374 "", "", "", "", 375 "", "", "", "", 376 "", "", "", ""; 377}; 378 379&gpio2 { 380 pinctrl-names = "default"; 381 pinctrl-0 = <&pinctrl_hoggpio2>; 382 383 gpio-line-names = "", "", "", "", 384 "", "", "VCC12V_EN", "PERST#", 385 "", "", "CLKREQ#", "PEWAKE#", 386 "USDHC2_CD", "", "", "", 387 "", "", "", "V_SD3V3_EN", 388 "", "", "", "", 389 "", "", "", "", 390 "", "", "", ""; 391 392 perst-hog { 393 gpio-hog; 394 gpios = <7 0>; 395 output-high; 396 line-name = "PERST#"; 397 }; 398 399 clkreq-hog { 400 gpio-hog; 401 gpios = <10 0>; 402 input; 403 line-name = "CLKREQ#"; 404 }; 405 406 pewake-hog { 407 gpio-hog; 408 gpios = <11 0>; 409 input; 410 line-name = "PEWAKE#"; 411 }; 412}; 413 414&gpio3 { 415 gpio-line-names = "", "", "", "", 416 "", "", "", "", 417 "", "", "", "", 418 "", "", "LVDS0_RESET#", "", 419 "", "", "", "LVDS0_BLT_EN", 420 "LVDS0_PWR_EN", "", "", "", 421 "", "", "", "", 422 "", "", "", ""; 423}; 424 425&gpio4 { 426 pinctrl-names = "default"; 427 pinctrl-0 = <&pinctrl_gpio4>; 428 429 gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#", 430 "", "", "", "", 431 "", "", "", "", 432 "", "", "", "", 433 "", "", "DP_IRQ", "DSI_EN", 434 "HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "", 435 "", "", "", "FAN_PWR", 436 "RTC_EVENT#", "CODEC_RST#", "", ""; 437 438 pcie-refclkreq-hog { 439 gpio-hog; 440 gpios = <22 0>; 441 output-high; 442 line-name = "PCIE_REFCLK_OE#"; 443 }; 444}; 445 446&gpio5 { 447 gpio-line-names = "", "", "", "LED2", 448 "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC", 449 "CSI0_TRIGGER", "CSI0_ENABLE", "", "", 450 "", "ECSPI2_SS0", "", "", 451 "", "", "", "", 452 "", "", "", "", 453 "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B", 454 "", "", "", ""; 455}; 456 457&i2c2 { 458 clock-frequency = <384000>; 459 pinctrl-names = "default", "gpio"; 460 pinctrl-0 = <&pinctrl_i2c2>; 461 pinctrl-1 = <&pinctrl_i2c2_gpio>; 462 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 463 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 464 status = "okay"; 465 466 tlv320aic3x04: audio-codec@18 { 467 compatible = "ti,tlv320aic32x4"; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pinctrl_tlv320aic3x04>; 470 reg = <0x18>; 471 clock-names = "mclk"; 472 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; 473 reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; 474 iov-supply = <®_vcc_1v8>; 475 ldoin-supply = <®_vcc_3v3>; 476 }; 477 478 se97_1c: temperature-sensor@1c { 479 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 480 reg = <0x1c>; 481 }; 482 483 at24c02_54: eeprom@54 { 484 compatible = "nxp,se97b", "atmel,24c02"; 485 reg = <0x54>; 486 pagesize = <16>; 487 vcc-supply = <®_vcc_3v3>; 488 }; 489 490 pcieclk: clock-generator@6a { 491 compatible = "renesas,9fgv0241"; 492 reg = <0x6a>; 493 clocks = <&clk_xtal25>; 494 #clock-cells = <1>; 495 }; 496}; 497 498&i2c4 { 499 clock-frequency = <384000>; 500 pinctrl-names = "default", "gpio"; 501 pinctrl-0 = <&pinctrl_i2c4>; 502 pinctrl-1 = <&pinctrl_i2c4_gpio>; 503 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 504 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 505 status = "okay"; 506}; 507 508&i2c6 { 509 clock-frequency = <384000>; 510 pinctrl-names = "default", "gpio"; 511 pinctrl-0 = <&pinctrl_i2c6>; 512 pinctrl-1 = <&pinctrl_i2c6_gpio>; 513 scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 514 sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 515 status = "okay"; 516}; 517 518&pcf85063 { 519 /* RTC_EVENT# is connected on MBa8MPxL */ 520 pinctrl-names = "default"; 521 pinctrl-0 = <&pinctrl_pcf85063>; 522 interrupt-parent = <&gpio4>; 523 interrupts = <28 IRQ_TYPE_EDGE_FALLING>; 524}; 525 526&pcie_phy { 527 fsl,clkreq-unsupported; 528 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 529 clocks = <&pcieclk 0>; 530 clock-names = "ref"; 531 status = "okay"; 532}; 533 534&pcie { 535 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 536 <&clk IMX8MP_CLK_HSIO_AXI>, 537 <&clk IMX8MP_CLK_PCIE_ROOT>; 538 clock-names = "pcie", "pcie_bus", "pcie_aux"; 539 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 540 assigned-clock-rates = <10000000>; 541 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 542 status = "okay"; 543}; 544 545&pwm2 { 546 pinctrl-names = "default"; 547 pinctrl-0 = <&pinctrl_pwm2>; 548 status = "disabled"; 549}; 550 551&pwm3 { 552 pinctrl-names = "default"; 553 pinctrl-0 = <&pinctrl_pwm3>; 554 status = "okay"; 555}; 556 557&sai3 { 558 pinctrl-names = "default"; 559 pinctrl-0 = <&pinctrl_sai3>; 560 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 561 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 562 assigned-clock-rates = <12288000>; 563 fsl,sai-mclk-direction-output; 564 status = "okay"; 565}; 566 567&snvs_pwrkey { 568 status = "okay"; 569}; 570 571&uart1 { 572 pinctrl-names = "default"; 573 pinctrl-0 = <&pinctrl_uart1>; 574 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 575 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 576 status = "okay"; 577}; 578 579&uart2 { 580 pinctrl-names = "default"; 581 pinctrl-0 = <&pinctrl_uart2>; 582 assigned-clocks = <&clk IMX8MP_CLK_UART2>; 583 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 584 status = "okay"; 585}; 586 587&uart3 { 588 pinctrl-names = "default"; 589 pinctrl-0 = <&pinctrl_uart3>; 590 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 591 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 592 status = "okay"; 593}; 594 595&uart4 { 596 /* console */ 597 pinctrl-names = "default"; 598 pinctrl-0 = <&pinctrl_uart4>; 599 status = "okay"; 600}; 601 602&usb3_0 { 603 pinctrl-names = "default"; 604 pinctrl-0 = <&pinctrl_usb0>; 605 fsl,over-current-active-low; 606 status = "okay"; 607}; 608 609&usb3_1 { 610 fsl,disable-port-power-control; 611 fsl,permanently-attached; 612 dr_mode = "host"; 613 status = "okay"; 614}; 615 616&usb3_phy0 { 617 vbus-supply = <®_vcc_5v0>; 618 status = "okay"; 619}; 620 621&usb3_phy1 { 622 vbus-supply = <®_vcc_5v0>; 623 status = "okay"; 624}; 625 626&usb_dwc3_0 { 627 /* dual role is implemented, but not a full featured OTG */ 628 hnp-disable; 629 srp-disable; 630 adp-disable; 631 dr_mode = "otg"; 632 usb-role-switch; 633 role-switch-default-mode = "peripheral"; 634 status = "okay"; 635 636 connector { 637 compatible = "gpio-usb-b-connector", "usb-b-connector"; 638 type = "micro"; 639 label = "X29"; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&pinctrl_usbcon0>; 642 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 643 }; 644}; 645 646&usb_dwc3_1 { 647 dr_mode = "host"; 648 #address-cells = <1>; 649 #size-cells = <0>; 650 pinctrl-names = "default"; 651 pinctrl-0 = <&pinctrl_usbhub>; 652 status = "okay"; 653 654 hub_2_0: hub@1 { 655 compatible = "usb451,8142"; 656 reg = <1>; 657 peer-hub = <&hub_3_0>; 658 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 659 vdd-supply = <®_vcc_3v3>; 660 }; 661 662 hub_3_0: hub@2 { 663 compatible = "usb451,8140"; 664 reg = <2>; 665 peer-hub = <&hub_2_0>; 666 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 667 vdd-supply = <®_vcc_3v3>; 668 }; 669}; 670 671&usdhc2 { 672 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 673 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 674 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 675 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 676 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 677 vmmc-supply = <®_usdhc2_vmmc>; 678 no-mmc; 679 no-sdio; 680 disable-wp; 681 bus-width = <4>; 682 status = "okay"; 683}; 684 685&iomuxc { 686 pinctrl_backlight: backlightgrp { 687 fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x14>; 688 }; 689 690 pinctrl_flexcan1: flexcan1grp { 691 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>, 692 <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>; 693 }; 694 695 pinctrl_flexcan2: flexcan2grp { 696 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>, 697 <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>; 698 }; 699 700 /* only on X57, primary used as CSI0 control signals */ 701 pinctrl_ecspi1: ecspi1grp { 702 fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>, 703 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>, 704 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>, 705 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>; 706 }; 707 708 /* on X63 and optionally on X57, can also be used as CSI1 control signals */ 709 pinctrl_ecspi2: ecspi2grp { 710 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c0>, 711 <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1c0>, 712 <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1c0>, 713 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c0>; 714 }; 715 716 pinctrl_ecspi3: ecspi3grp { 717 fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x1c0>, 718 <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x1c0>, 719 <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>, 720 <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0>; 721 }; 722 723 pinctrl_eqos: eqosgrp { 724 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>, 725 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>, 726 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, 727 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, 728 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, 729 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, 730 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, 731 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, 732 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>, 733 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>, 734 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>, 735 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>, 736 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>, 737 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>; 738 }; 739 740 pinctrl_eqos_event: eqosevtgrp { 741 fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x100>, 742 <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1c0>; 743 }; 744 745 pinctrl_eqos_phy: eqosphygrp { 746 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>, 747 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>; 748 }; 749 750 pinctrl_fec: fecgrp { 751 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>, 752 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>, 753 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, 754 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, 755 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, 756 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, 757 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, 758 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, 759 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>, 760 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>, 761 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>, 762 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>, 763 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>, 764 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>; 765 }; 766 767 pinctrl_fec_event: fecevtgrp { 768 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x100>, 769 <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1c0>; 770 }; 771 772 pinctrl_fec_phy: fecphygrp { 773 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>, 774 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>; 775 }; 776 777 pinctrl_fec_phyalt: fecphyaltgrp { 778 fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x180>, 779 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>; 780 }; 781 782 pinctrl_gpiobutton: gpiobuttongrp { 783 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>, 784 <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x10>; 785 }; 786 787 pinctrl_gpioled: gpioledgrp { 788 fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x14>, 789 <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x14>, 790 <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x14>; 791 }; 792 793 pinctrl_gpio1: gpio1grp { 794 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>, 795 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>, 796 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>, 797 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>, 798 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>, 799 <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>, 800 <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>, 801 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>; 802 }; 803 804 pinctrl_gpio4: gpio4grp { 805 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x180>, 806 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x180>; 807 }; 808 809 pinctrl_hdmi: hdmigrp { 810 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>, 811 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>, 812 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>, 813 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>; 814 }; 815 816 pinctrl_hoggpio2: hoggpio2grp { 817 fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x140>, 818 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140>, 819 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>; 820 }; 821 822 pinctrl_i2c2: i2c2grp { 823 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>, 824 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>; 825 }; 826 827 pinctrl_i2c2_gpio: i2c2-gpiogrp { 828 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>, 829 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>; 830 }; 831 832 pinctrl_i2c4: i2c4grp { 833 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e2>, 834 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e2>; 835 }; 836 837 pinctrl_i2c4_gpio: i2c4-gpiogrp { 838 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001e2>, 839 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001e2>; 840 }; 841 842 pinctrl_i2c6: i2c6grp { 843 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>, 844 <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>; 845 }; 846 847 pinctrl_i2c6_gpio: i2c6-gpiogrp { 848 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>, 849 <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>; 850 }; 851 852 pinctrl_lvdsdisplay: lvdsdisplaygrp { 853 fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */ 854 }; 855 856 pinctrl_pcf85063: pcf85063grp { 857 fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x80>; 858 }; 859 860 /* LVDS Backlight */ 861 pinctrl_pwm2: pwm2grp { 862 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>; 863 }; 864 865 /* FAN */ 866 pinctrl_pwm3: pwm3grp { 867 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>; 868 }; 869 870 pinctrl_pwmfan: pwmfangrp { 871 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>; /* FAN RPM */ 872 }; 873 874 pinctrl_reg12v0: reg12v0grp { 875 fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */ 876 }; 877 878 pinctrl_regpwmfan: regpwmfangrp { 879 fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x80>; 880 }; 881 882 pinctrl_sai3: sai3grp { 883 fsl,pins = < 884 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94 885 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94 886 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94 887 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94 888 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x94 889 >; 890 }; 891 892 pinctrl_tlv320aic3x04: tlv320aic3x04grp { 893 fsl,pins = < 894 /* CODEC RST# */ 895 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x180 896 >; 897 }; 898 899 /* X61 */ 900 pinctrl_uart1: uart1grp { 901 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>, 902 <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140>; 903 }; 904 905 /* X61 */ 906 pinctrl_uart2: uart2grp { 907 fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x140>, 908 <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x140>; 909 }; 910 911 pinctrl_uart3: uart3grp { 912 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>, 913 <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>; 914 }; 915 916 pinctrl_uart4: uart4grp { 917 fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>, 918 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>; 919 }; 920 921 pinctrl_usb0: usb0grp { 922 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0>, 923 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x1c0>; 924 }; 925 926 pinctrl_usbcon0: usb0congrp { 927 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>; 928 }; 929 930 pinctrl_usbhub: usbhubgrp { 931 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x10>; 932 }; 933 934 pinctrl_usdhc2: usdhc2grp { 935 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>, 936 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>, 937 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 938 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 939 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 940 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, 941 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 942 }; 943 944 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 945 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 946 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 947 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 948 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 949 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 950 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 951 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 952 }; 953 954 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 955 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 956 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 957 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 958 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 959 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 960 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 961 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 962 }; 963 964 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 965 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>; 966 }; 967}; 968