188f7f6bcSTeresa Remmet// SPDX-License-Identifier: GPL-2.0 288f7f6bcSTeresa Remmet/* 388f7f6bcSTeresa Remmet * Copyright (C) 2020 PHYTEC Messtechnik GmbH 488f7f6bcSTeresa Remmet * Author: Teresa Remmet <t.remmet@phytec.de> 588f7f6bcSTeresa Remmet */ 688f7f6bcSTeresa Remmet 788f7f6bcSTeresa Remmet/dts-v1/; 888f7f6bcSTeresa Remmet 988f7f6bcSTeresa Remmet#include <dt-bindings/leds/leds-pca9532.h> 1088f7f6bcSTeresa Remmet#include <dt-bindings/pwm/pwm.h> 1188f7f6bcSTeresa Remmet#include "imx8mp-phycore-som.dtsi" 1288f7f6bcSTeresa Remmet 1388f7f6bcSTeresa Remmet/ { 1488f7f6bcSTeresa Remmet model = "PHYTEC phyBOARD-Pollux i.MX8MP"; 1588f7f6bcSTeresa Remmet compatible = "phytec,imx8mp-phyboard-pollux-rdk", 1688f7f6bcSTeresa Remmet "phytec,imx8mp-phycore-som", "fsl,imx8mp"; 1788f7f6bcSTeresa Remmet 1888f7f6bcSTeresa Remmet chosen { 19846f7528STeresa Remmet stdout-path = &uart1; 2088f7f6bcSTeresa Remmet }; 2188f7f6bcSTeresa Remmet 2288f7f6bcSTeresa Remmet reg_usdhc2_vmmc: regulator-usdhc2 { 2388f7f6bcSTeresa Remmet compatible = "regulator-fixed"; 2488f7f6bcSTeresa Remmet pinctrl-names = "default"; 2588f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 2688f7f6bcSTeresa Remmet regulator-name = "VSD_3V3"; 2788f7f6bcSTeresa Remmet regulator-min-microvolt = <3300000>; 2888f7f6bcSTeresa Remmet regulator-max-microvolt = <3300000>; 2988f7f6bcSTeresa Remmet gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 3088f7f6bcSTeresa Remmet enable-active-high; 3188f7f6bcSTeresa Remmet startup-delay-us = <100>; 3288f7f6bcSTeresa Remmet off-on-delay-us = <12000>; 3388f7f6bcSTeresa Remmet }; 3488f7f6bcSTeresa Remmet}; 3588f7f6bcSTeresa Remmet 366f968526SMarek Vasut&eqos { 376f968526SMarek Vasut pinctrl-names = "default"; 386f968526SMarek Vasut pinctrl-0 = <&pinctrl_eqos>; 396f968526SMarek Vasut phy-mode = "rgmii-id"; 406f968526SMarek Vasut phy-handle = <ðphy0>; 416f968526SMarek Vasut status = "okay"; 426f968526SMarek Vasut 436f968526SMarek Vasut mdio { 446f968526SMarek Vasut compatible = "snps,dwmac-mdio"; 456f968526SMarek Vasut #address-cells = <1>; 466f968526SMarek Vasut #size-cells = <0>; 476f968526SMarek Vasut 486f968526SMarek Vasut ethphy0: ethernet-phy@1 { 496f968526SMarek Vasut compatible = "ethernet-phy-ieee802.3-c22"; 506f968526SMarek Vasut reg = <0x1>; 516f968526SMarek Vasut ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; 526f968526SMarek Vasut ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; 536f968526SMarek Vasut ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 546f968526SMarek Vasut ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 556f968526SMarek Vasut enet-phy-lane-no-swap; 566f968526SMarek Vasut }; 576f968526SMarek Vasut }; 586f968526SMarek Vasut}; 596f968526SMarek Vasut 6088f7f6bcSTeresa Remmet&i2c2 { 6188f7f6bcSTeresa Remmet clock-frequency = <400000>; 62412627f6STeresa Remmet pinctrl-names = "default", "gpio"; 6388f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_i2c2>; 6488f7f6bcSTeresa Remmet pinctrl-1 = <&pinctrl_i2c2_gpio>; 6588f7f6bcSTeresa Remmet sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 6688f7f6bcSTeresa Remmet scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 6788f7f6bcSTeresa Remmet status = "okay"; 6888f7f6bcSTeresa Remmet 6988f7f6bcSTeresa Remmet eeprom@51 { 7088f7f6bcSTeresa Remmet compatible = "atmel,24c02"; 7188f7f6bcSTeresa Remmet reg = <0x51>; 7288f7f6bcSTeresa Remmet pagesize = <16>; 7388f7f6bcSTeresa Remmet }; 7488f7f6bcSTeresa Remmet 7588f7f6bcSTeresa Remmet leds@62 { 7688f7f6bcSTeresa Remmet compatible = "nxp,pca9533"; 7788f7f6bcSTeresa Remmet reg = <0x62>; 7888f7f6bcSTeresa Remmet 7988f7f6bcSTeresa Remmet led1 { 8088f7f6bcSTeresa Remmet type = <PCA9532_TYPE_LED>; 8188f7f6bcSTeresa Remmet }; 8288f7f6bcSTeresa Remmet 8388f7f6bcSTeresa Remmet led2 { 8488f7f6bcSTeresa Remmet type = <PCA9532_TYPE_LED>; 8588f7f6bcSTeresa Remmet }; 8688f7f6bcSTeresa Remmet 8788f7f6bcSTeresa Remmet led3 { 8888f7f6bcSTeresa Remmet type = <PCA9532_TYPE_LED>; 8988f7f6bcSTeresa Remmet }; 9088f7f6bcSTeresa Remmet }; 9188f7f6bcSTeresa Remmet}; 9288f7f6bcSTeresa Remmet 9388f7f6bcSTeresa Remmet&snvs_pwrkey { 9488f7f6bcSTeresa Remmet status = "okay"; 9588f7f6bcSTeresa Remmet}; 9688f7f6bcSTeresa Remmet 9788f7f6bcSTeresa Remmet/* debug console */ 98846f7528STeresa Remmet&uart1 { 9988f7f6bcSTeresa Remmet pinctrl-names = "default"; 100846f7528STeresa Remmet pinctrl-0 = <&pinctrl_uart1>; 10188f7f6bcSTeresa Remmet status = "okay"; 10288f7f6bcSTeresa Remmet}; 10388f7f6bcSTeresa Remmet 10488f7f6bcSTeresa Remmet/* SD-Card */ 10588f7f6bcSTeresa Remmet&usdhc2 { 10688f7f6bcSTeresa Remmet pinctrl-names = "default", "state_100mhz", "state_200mhz"; 10788f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; 10888f7f6bcSTeresa Remmet pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>; 10988f7f6bcSTeresa Remmet pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>; 11088f7f6bcSTeresa Remmet cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 11188f7f6bcSTeresa Remmet vmmc-supply = <®_usdhc2_vmmc>; 11288f7f6bcSTeresa Remmet bus-width = <4>; 11388f7f6bcSTeresa Remmet status = "okay"; 11488f7f6bcSTeresa Remmet}; 11588f7f6bcSTeresa Remmet 11688f7f6bcSTeresa Remmet&iomuxc { 1176f968526SMarek Vasut pinctrl_eqos: eqosgrp { 1186f968526SMarek Vasut fsl,pins = < 1196f968526SMarek Vasut MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 1206f968526SMarek Vasut MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 1216f968526SMarek Vasut MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 1226f968526SMarek Vasut MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 1236f968526SMarek Vasut MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 1246f968526SMarek Vasut MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 1256f968526SMarek Vasut MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 1266f968526SMarek Vasut MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 1276f968526SMarek Vasut MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 1286f968526SMarek Vasut MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 1296f968526SMarek Vasut MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 1306f968526SMarek Vasut MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 1316f968526SMarek Vasut MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 1326f968526SMarek Vasut MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 1336f968526SMarek Vasut MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 1346f968526SMarek Vasut >; 1356f968526SMarek Vasut }; 1366f968526SMarek Vasut 13788f7f6bcSTeresa Remmet pinctrl_i2c2: i2c2grp { 13888f7f6bcSTeresa Remmet fsl,pins = < 13988f7f6bcSTeresa Remmet MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 14088f7f6bcSTeresa Remmet MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 14188f7f6bcSTeresa Remmet >; 14288f7f6bcSTeresa Remmet }; 14388f7f6bcSTeresa Remmet 14488f7f6bcSTeresa Remmet pinctrl_i2c2_gpio: i2c2gpiogrp { 14588f7f6bcSTeresa Remmet fsl,pins = < 14688f7f6bcSTeresa Remmet MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3 14788f7f6bcSTeresa Remmet MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3 14888f7f6bcSTeresa Remmet >; 14988f7f6bcSTeresa Remmet }; 15088f7f6bcSTeresa Remmet 15188f7f6bcSTeresa Remmet pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 15288f7f6bcSTeresa Remmet fsl,pins = < 15388f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 15488f7f6bcSTeresa Remmet >; 15588f7f6bcSTeresa Remmet }; 15688f7f6bcSTeresa Remmet 157846f7528STeresa Remmet pinctrl_uart1: uart1grp { 15888f7f6bcSTeresa Remmet fsl,pins = < 159*e266c155SPeng Fan MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 160*e266c155SPeng Fan MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 16188f7f6bcSTeresa Remmet >; 16288f7f6bcSTeresa Remmet }; 16388f7f6bcSTeresa Remmet 16488f7f6bcSTeresa Remmet pinctrl_usdhc2_pins: usdhc2-gpiogrp { 16588f7f6bcSTeresa Remmet fsl,pins = < 16688f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 16788f7f6bcSTeresa Remmet >; 16888f7f6bcSTeresa Remmet }; 16988f7f6bcSTeresa Remmet 17088f7f6bcSTeresa Remmet pinctrl_usdhc2: usdhc2grp { 17188f7f6bcSTeresa Remmet fsl,pins = < 17288f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 17388f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 17488f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 17588f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 17688f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 17788f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 17888f7f6bcSTeresa Remmet MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 17988f7f6bcSTeresa Remmet >; 18088f7f6bcSTeresa Remmet }; 18188f7f6bcSTeresa Remmet 18288f7f6bcSTeresa Remmet pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 18388f7f6bcSTeresa Remmet fsl,pins = < 18488f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 18588f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 18688f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 18788f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 18888f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 18988f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 19088f7f6bcSTeresa Remmet MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 19188f7f6bcSTeresa Remmet >; 19288f7f6bcSTeresa Remmet }; 19388f7f6bcSTeresa Remmet 19488f7f6bcSTeresa Remmet pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 19588f7f6bcSTeresa Remmet fsl,pins = < 19688f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 19788f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 19888f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 19988f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 20088f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 20188f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 20288f7f6bcSTeresa Remmet MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 20388f7f6bcSTeresa Remmet >; 20488f7f6bcSTeresa Remmet }; 20588f7f6bcSTeresa Remmet}; 206