188f7f6bcSTeresa Remmet// SPDX-License-Identifier: GPL-2.0 288f7f6bcSTeresa Remmet/* 388f7f6bcSTeresa Remmet * Copyright (C) 2020 PHYTEC Messtechnik GmbH 488f7f6bcSTeresa Remmet * Author: Teresa Remmet <t.remmet@phytec.de> 588f7f6bcSTeresa Remmet */ 688f7f6bcSTeresa Remmet 788f7f6bcSTeresa Remmet/dts-v1/; 888f7f6bcSTeresa Remmet 988f7f6bcSTeresa Remmet#include <dt-bindings/leds/leds-pca9532.h> 1088f7f6bcSTeresa Remmet#include <dt-bindings/pwm/pwm.h> 1188f7f6bcSTeresa Remmet#include "imx8mp-phycore-som.dtsi" 1288f7f6bcSTeresa Remmet 1388f7f6bcSTeresa Remmet/ { 1488f7f6bcSTeresa Remmet model = "PHYTEC phyBOARD-Pollux i.MX8MP"; 1588f7f6bcSTeresa Remmet compatible = "phytec,imx8mp-phyboard-pollux-rdk", 1688f7f6bcSTeresa Remmet "phytec,imx8mp-phycore-som", "fsl,imx8mp"; 1788f7f6bcSTeresa Remmet 1888f7f6bcSTeresa Remmet chosen { 1988f7f6bcSTeresa Remmet stdout-path = &uart2; 2088f7f6bcSTeresa Remmet }; 2188f7f6bcSTeresa Remmet 2288f7f6bcSTeresa Remmet reg_usdhc2_vmmc: regulator-usdhc2 { 2388f7f6bcSTeresa Remmet compatible = "regulator-fixed"; 2488f7f6bcSTeresa Remmet pinctrl-names = "default"; 2588f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 2688f7f6bcSTeresa Remmet regulator-name = "VSD_3V3"; 2788f7f6bcSTeresa Remmet regulator-min-microvolt = <3300000>; 2888f7f6bcSTeresa Remmet regulator-max-microvolt = <3300000>; 2988f7f6bcSTeresa Remmet gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 3088f7f6bcSTeresa Remmet enable-active-high; 3188f7f6bcSTeresa Remmet startup-delay-us = <100>; 3288f7f6bcSTeresa Remmet off-on-delay-us = <12000>; 3388f7f6bcSTeresa Remmet }; 3488f7f6bcSTeresa Remmet}; 3588f7f6bcSTeresa Remmet 3688f7f6bcSTeresa Remmet&i2c2 { 3788f7f6bcSTeresa Remmet clock-frequency = <400000>; 38*412627f6STeresa Remmet pinctrl-names = "default", "gpio"; 3988f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_i2c2>; 4088f7f6bcSTeresa Remmet pinctrl-1 = <&pinctrl_i2c2_gpio>; 4188f7f6bcSTeresa Remmet sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 4288f7f6bcSTeresa Remmet scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 4388f7f6bcSTeresa Remmet status = "okay"; 4488f7f6bcSTeresa Remmet 4588f7f6bcSTeresa Remmet eeprom@51 { 4688f7f6bcSTeresa Remmet compatible = "atmel,24c02"; 4788f7f6bcSTeresa Remmet reg = <0x51>; 4888f7f6bcSTeresa Remmet pagesize = <16>; 4988f7f6bcSTeresa Remmet }; 5088f7f6bcSTeresa Remmet 5188f7f6bcSTeresa Remmet leds@62 { 5288f7f6bcSTeresa Remmet compatible = "nxp,pca9533"; 5388f7f6bcSTeresa Remmet reg = <0x62>; 5488f7f6bcSTeresa Remmet 5588f7f6bcSTeresa Remmet led1 { 5688f7f6bcSTeresa Remmet type = <PCA9532_TYPE_LED>; 5788f7f6bcSTeresa Remmet }; 5888f7f6bcSTeresa Remmet 5988f7f6bcSTeresa Remmet led2 { 6088f7f6bcSTeresa Remmet type = <PCA9532_TYPE_LED>; 6188f7f6bcSTeresa Remmet }; 6288f7f6bcSTeresa Remmet 6388f7f6bcSTeresa Remmet led3 { 6488f7f6bcSTeresa Remmet type = <PCA9532_TYPE_LED>; 6588f7f6bcSTeresa Remmet }; 6688f7f6bcSTeresa Remmet }; 6788f7f6bcSTeresa Remmet}; 6888f7f6bcSTeresa Remmet 6988f7f6bcSTeresa Remmet&snvs_pwrkey { 7088f7f6bcSTeresa Remmet status = "okay"; 7188f7f6bcSTeresa Remmet}; 7288f7f6bcSTeresa Remmet 7388f7f6bcSTeresa Remmet/* debug console */ 7488f7f6bcSTeresa Remmet&uart2 { 7588f7f6bcSTeresa Remmet pinctrl-names = "default"; 7688f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_uart2>; 7788f7f6bcSTeresa Remmet status = "okay"; 7888f7f6bcSTeresa Remmet}; 7988f7f6bcSTeresa Remmet 8088f7f6bcSTeresa Remmet/* SD-Card */ 8188f7f6bcSTeresa Remmet&usdhc2 { 8288f7f6bcSTeresa Remmet pinctrl-names = "default", "state_100mhz", "state_200mhz"; 8388f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; 8488f7f6bcSTeresa Remmet pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>; 8588f7f6bcSTeresa Remmet pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>; 8688f7f6bcSTeresa Remmet cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 8788f7f6bcSTeresa Remmet vmmc-supply = <®_usdhc2_vmmc>; 8888f7f6bcSTeresa Remmet bus-width = <4>; 8988f7f6bcSTeresa Remmet status = "okay"; 9088f7f6bcSTeresa Remmet}; 9188f7f6bcSTeresa Remmet 9288f7f6bcSTeresa Remmet&iomuxc { 9388f7f6bcSTeresa Remmet pinctrl_i2c2: i2c2grp { 9488f7f6bcSTeresa Remmet fsl,pins = < 9588f7f6bcSTeresa Remmet MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 9688f7f6bcSTeresa Remmet MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 9788f7f6bcSTeresa Remmet >; 9888f7f6bcSTeresa Remmet }; 9988f7f6bcSTeresa Remmet 10088f7f6bcSTeresa Remmet pinctrl_i2c2_gpio: i2c2gpiogrp { 10188f7f6bcSTeresa Remmet fsl,pins = < 10288f7f6bcSTeresa Remmet MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3 10388f7f6bcSTeresa Remmet MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3 10488f7f6bcSTeresa Remmet >; 10588f7f6bcSTeresa Remmet }; 10688f7f6bcSTeresa Remmet 10788f7f6bcSTeresa Remmet pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 10888f7f6bcSTeresa Remmet fsl,pins = < 10988f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 11088f7f6bcSTeresa Remmet >; 11188f7f6bcSTeresa Remmet }; 11288f7f6bcSTeresa Remmet 11388f7f6bcSTeresa Remmet pinctrl_uart2: uart2grp { 11488f7f6bcSTeresa Remmet fsl,pins = < 11588f7f6bcSTeresa Remmet MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 11688f7f6bcSTeresa Remmet MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 11788f7f6bcSTeresa Remmet >; 11888f7f6bcSTeresa Remmet }; 11988f7f6bcSTeresa Remmet 12088f7f6bcSTeresa Remmet pinctrl_usdhc2_pins: usdhc2-gpiogrp { 12188f7f6bcSTeresa Remmet fsl,pins = < 12288f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 12388f7f6bcSTeresa Remmet >; 12488f7f6bcSTeresa Remmet }; 12588f7f6bcSTeresa Remmet 12688f7f6bcSTeresa Remmet pinctrl_usdhc2: usdhc2grp { 12788f7f6bcSTeresa Remmet fsl,pins = < 12888f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 12988f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 13088f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 13188f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 13288f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 13388f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 13488f7f6bcSTeresa Remmet MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 13588f7f6bcSTeresa Remmet >; 13688f7f6bcSTeresa Remmet }; 13788f7f6bcSTeresa Remmet 13888f7f6bcSTeresa Remmet pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 13988f7f6bcSTeresa Remmet fsl,pins = < 14088f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 14188f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 14288f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 14388f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 14488f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 14588f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 14688f7f6bcSTeresa Remmet MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 14788f7f6bcSTeresa Remmet >; 14888f7f6bcSTeresa Remmet }; 14988f7f6bcSTeresa Remmet 15088f7f6bcSTeresa Remmet pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 15188f7f6bcSTeresa Remmet fsl,pins = < 15288f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 15388f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 15488f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 15588f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 15688f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 15788f7f6bcSTeresa Remmet MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 15888f7f6bcSTeresa Remmet MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 15988f7f6bcSTeresa Remmet >; 16088f7f6bcSTeresa Remmet }; 16188f7f6bcSTeresa Remmet}; 162