1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9#include "imx8mp.dtsi" 10 11/ { 12 model = "NXP i.MX8MPlus EVK board"; 13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; 14 15 chosen { 16 stdout-path = &uart2; 17 }; 18 19 gpio-leds { 20 compatible = "gpio-leds"; 21 pinctrl-names = "default"; 22 pinctrl-0 = <&pinctrl_gpio_led>; 23 24 status { 25 label = "yellow:status"; 26 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 27 default-state = "on"; 28 }; 29 }; 30 31 memory@40000000 { 32 device_type = "memory"; 33 reg = <0x0 0x40000000 0 0xc0000000>, 34 <0x1 0x00000000 0 0xc0000000>; 35 }; 36 37 pcie0_refclk: pcie0-refclk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <100000000>; 41 }; 42 43 reg_can1_stby: regulator-can1-stby { 44 compatible = "regulator-fixed"; 45 regulator-name = "can1-stby"; 46 pinctrl-names = "default"; 47 pinctrl-0 = <&pinctrl_flexcan1_reg>; 48 regulator-min-microvolt = <3300000>; 49 regulator-max-microvolt = <3300000>; 50 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; 51 enable-active-high; 52 }; 53 54 reg_can2_stby: regulator-can2-stby { 55 compatible = "regulator-fixed"; 56 regulator-name = "can2-stby"; 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_flexcan2_reg>; 59 regulator-min-microvolt = <3300000>; 60 regulator-max-microvolt = <3300000>; 61 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 62 enable-active-high; 63 }; 64 65 reg_pcie0: regulator-pcie { 66 compatible = "regulator-fixed"; 67 pinctrl-names = "default"; 68 pinctrl-0 = <&pinctrl_pcie0_reg>; 69 regulator-name = "MPCIE_3V3"; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 73 enable-active-high; 74 }; 75 76 reg_usdhc2_vmmc: regulator-usdhc2 { 77 compatible = "regulator-fixed"; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 80 regulator-name = "VSD_3V3"; 81 regulator-min-microvolt = <3300000>; 82 regulator-max-microvolt = <3300000>; 83 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 84 enable-active-high; 85 }; 86}; 87 88&A53_0 { 89 cpu-supply = <®_arm>; 90}; 91 92&A53_1 { 93 cpu-supply = <®_arm>; 94}; 95 96&A53_2 { 97 cpu-supply = <®_arm>; 98}; 99 100&A53_3 { 101 cpu-supply = <®_arm>; 102}; 103 104&eqos { 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_eqos>; 107 phy-mode = "rgmii-id"; 108 phy-handle = <ðphy0>; 109 snps,force_thresh_dma_mode; 110 snps,mtl-tx-config = <&mtl_tx_setup>; 111 snps,mtl-rx-config = <&mtl_rx_setup>; 112 status = "okay"; 113 114 mdio { 115 compatible = "snps,dwmac-mdio"; 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 ethphy0: ethernet-phy@1 { 120 compatible = "ethernet-phy-ieee802.3-c22"; 121 reg = <1>; 122 eee-broken-1000t; 123 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 124 reset-assert-us = <10000>; 125 reset-deassert-us = <80000>; 126 realtek,clkout-disable; 127 }; 128 }; 129 130 mtl_tx_setup: tx-queues-config { 131 snps,tx-queues-to-use = <5>; 132 snps,tx-sched-sp; 133 134 queue0 { 135 snps,dcb-algorithm; 136 snps,priority = <0x1>; 137 }; 138 139 queue1 { 140 snps,dcb-algorithm; 141 snps,priority = <0x2>; 142 }; 143 144 queue2 { 145 snps,dcb-algorithm; 146 snps,priority = <0x4>; 147 }; 148 149 queue3 { 150 snps,dcb-algorithm; 151 snps,priority = <0x8>; 152 }; 153 154 queue4 { 155 snps,dcb-algorithm; 156 snps,priority = <0xf0>; 157 }; 158 }; 159 160 mtl_rx_setup: rx-queues-config { 161 snps,rx-queues-to-use = <5>; 162 snps,rx-sched-sp; 163 164 queue0 { 165 snps,dcb-algorithm; 166 snps,priority = <0x1>; 167 snps,map-to-dma-channel = <0>; 168 }; 169 170 queue1 { 171 snps,dcb-algorithm; 172 snps,priority = <0x2>; 173 snps,map-to-dma-channel = <1>; 174 }; 175 176 queue2 { 177 snps,dcb-algorithm; 178 snps,priority = <0x4>; 179 snps,map-to-dma-channel = <2>; 180 }; 181 182 queue3 { 183 snps,dcb-algorithm; 184 snps,priority = <0x8>; 185 snps,map-to-dma-channel = <3>; 186 }; 187 188 queue4 { 189 snps,dcb-algorithm; 190 snps,priority = <0xf0>; 191 snps,map-to-dma-channel = <4>; 192 }; 193 }; 194}; 195 196&fec { 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_fec>; 199 phy-mode = "rgmii-id"; 200 phy-handle = <ðphy1>; 201 fsl,magic-packet; 202 status = "okay"; 203 204 mdio { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 208 ethphy1: ethernet-phy@1 { 209 compatible = "ethernet-phy-ieee802.3-c22"; 210 reg = <1>; 211 eee-broken-1000t; 212 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 213 reset-assert-us = <10000>; 214 reset-deassert-us = <80000>; 215 realtek,clkout-disable; 216 }; 217 }; 218}; 219 220&flexcan1 { 221 pinctrl-names = "default"; 222 pinctrl-0 = <&pinctrl_flexcan1>; 223 xceiver-supply = <®_can1_stby>; 224 status = "okay"; 225}; 226 227&flexcan2 { 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pinctrl_flexcan2>; 230 xceiver-supply = <®_can2_stby>; 231 status = "disabled";/* can2 pin conflict with pdm */ 232}; 233 234&i2c1 { 235 clock-frequency = <400000>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_i2c1>; 238 status = "okay"; 239 240 pmic@25 { 241 compatible = "nxp,pca9450c"; 242 reg = <0x25>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_pmic>; 245 interrupt-parent = <&gpio1>; 246 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 247 248 regulators { 249 BUCK1 { 250 regulator-name = "BUCK1"; 251 regulator-min-microvolt = <720000>; 252 regulator-max-microvolt = <1000000>; 253 regulator-boot-on; 254 regulator-always-on; 255 regulator-ramp-delay = <3125>; 256 }; 257 258 reg_arm: BUCK2 { 259 regulator-name = "BUCK2"; 260 regulator-min-microvolt = <720000>; 261 regulator-max-microvolt = <1025000>; 262 regulator-boot-on; 263 regulator-always-on; 264 regulator-ramp-delay = <3125>; 265 nxp,dvs-run-voltage = <950000>; 266 nxp,dvs-standby-voltage = <850000>; 267 }; 268 269 BUCK4 { 270 regulator-name = "BUCK4"; 271 regulator-min-microvolt = <3000000>; 272 regulator-max-microvolt = <3600000>; 273 regulator-boot-on; 274 regulator-always-on; 275 }; 276 277 BUCK5 { 278 regulator-name = "BUCK5"; 279 regulator-min-microvolt = <1650000>; 280 regulator-max-microvolt = <1950000>; 281 regulator-boot-on; 282 regulator-always-on; 283 }; 284 285 BUCK6 { 286 regulator-name = "BUCK6"; 287 regulator-min-microvolt = <1045000>; 288 regulator-max-microvolt = <1155000>; 289 regulator-boot-on; 290 regulator-always-on; 291 }; 292 293 LDO1 { 294 regulator-name = "LDO1"; 295 regulator-min-microvolt = <1650000>; 296 regulator-max-microvolt = <1950000>; 297 regulator-boot-on; 298 regulator-always-on; 299 }; 300 301 LDO3 { 302 regulator-name = "LDO3"; 303 regulator-min-microvolt = <1710000>; 304 regulator-max-microvolt = <1890000>; 305 regulator-boot-on; 306 regulator-always-on; 307 }; 308 309 LDO5 { 310 regulator-name = "LDO5"; 311 regulator-min-microvolt = <1800000>; 312 regulator-max-microvolt = <3300000>; 313 regulator-boot-on; 314 regulator-always-on; 315 }; 316 }; 317 }; 318}; 319 320&i2c3 { 321 clock-frequency = <400000>; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_i2c3>; 324 status = "okay"; 325 326 pca6416: gpio@20 { 327 compatible = "ti,tca6416"; 328 reg = <0x20>; 329 gpio-controller; 330 #gpio-cells = <2>; 331 interrupt-controller; 332 #interrupt-cells = <2>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&pinctrl_pca6416_int>; 335 interrupt-parent = <&gpio1>; 336 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 337 gpio-line-names = "EXT_PWREN1", 338 "EXT_PWREN2", 339 "CAN1/I2C5_SEL", 340 "PDM/CAN2_SEL", 341 "FAN_EN", 342 "PWR_MEAS_IO1", 343 "PWR_MEAS_IO2", 344 "EXP_P0_7", 345 "EXP_P1_0", 346 "EXP_P1_1", 347 "EXP_P1_2", 348 "EXP_P1_3", 349 "EXP_P1_4", 350 "EXP_P1_5", 351 "EXP_P1_6", 352 "EXP_P1_7"; 353 }; 354}; 355 356/* I2C on expansion connector J22. */ 357&i2c5 { 358 clock-frequency = <100000>; /* Lower clock speed for external bus. */ 359 pinctrl-names = "default"; 360 pinctrl-0 = <&pinctrl_i2c5>; 361 status = "disabled"; /* can1 pins conflict with i2c5 */ 362 363 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions: 364 * LOW: CAN1 (default, pull-down) 365 * HIGH: I2C5 366 * You need to set it to high to enable I2C5 (for example, add gpio-hog 367 * in pca6416 node). 368 */ 369}; 370 371&pcie_phy { 372 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 373 clocks = <&pcie0_refclk>; 374 clock-names = "ref"; 375 status = "okay"; 376}; 377 378&pcie { 379 pinctrl-names = "default"; 380 pinctrl-0 = <&pinctrl_pcie0>; 381 reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; 382 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 383 <&clk IMX8MP_CLK_PCIE_ROOT>, 384 <&clk IMX8MP_CLK_HSIO_AXI>; 385 clock-names = "pcie", "pcie_aux", "pcie_bus"; 386 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 387 assigned-clock-rates = <10000000>; 388 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 389 vpcie-supply = <®_pcie0>; 390 status = "okay"; 391}; 392 393&snvs_pwrkey { 394 status = "okay"; 395}; 396 397&uart2 { 398 /* console */ 399 pinctrl-names = "default"; 400 pinctrl-0 = <&pinctrl_uart2>; 401 status = "okay"; 402}; 403 404&usb3_phy1 { 405 status = "okay"; 406}; 407 408&usb3_1 { 409 status = "okay"; 410}; 411 412&usb_dwc3_1 { 413 pinctrl-names = "default"; 414 pinctrl-0 = <&pinctrl_usb1_vbus>; 415 dr_mode = "host"; 416 status = "okay"; 417}; 418 419&usdhc2 { 420 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 421 assigned-clock-rates = <400000000>; 422 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 423 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 424 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 425 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 426 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 427 vmmc-supply = <®_usdhc2_vmmc>; 428 bus-width = <4>; 429 status = "okay"; 430}; 431 432&usdhc3 { 433 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 434 assigned-clock-rates = <400000000>; 435 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 436 pinctrl-0 = <&pinctrl_usdhc3>; 437 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 438 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 439 bus-width = <8>; 440 non-removable; 441 status = "okay"; 442}; 443 444&wdog1 { 445 pinctrl-names = "default"; 446 pinctrl-0 = <&pinctrl_wdog>; 447 fsl,ext-reset-output; 448 status = "okay"; 449}; 450 451&iomuxc { 452 pinctrl_eqos: eqosgrp { 453 fsl,pins = < 454 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 455 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 456 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 457 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 458 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 459 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 460 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 461 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 462 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 463 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 464 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 465 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 466 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 467 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 468 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 469 >; 470 }; 471 472 pinctrl_fec: fecgrp { 473 fsl,pins = < 474 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 475 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 476 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 477 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 478 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 479 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 480 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 481 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 482 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 483 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 484 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 485 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 486 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 487 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 488 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 489 >; 490 }; 491 492 pinctrl_flexcan1: flexcan1grp { 493 fsl,pins = < 494 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 495 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 496 >; 497 }; 498 499 pinctrl_flexcan2: flexcan2grp { 500 fsl,pins = < 501 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 502 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 503 >; 504 }; 505 506 pinctrl_flexcan1_reg: flexcan1reggrp { 507 fsl,pins = < 508 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ 509 >; 510 }; 511 512 pinctrl_flexcan2_reg: flexcan2reggrp { 513 fsl,pins = < 514 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ 515 >; 516 }; 517 518 pinctrl_gpio_led: gpioledgrp { 519 fsl,pins = < 520 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 521 >; 522 }; 523 524 pinctrl_i2c1: i2c1grp { 525 fsl,pins = < 526 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 527 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 528 >; 529 }; 530 531 pinctrl_i2c3: i2c3grp { 532 fsl,pins = < 533 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 534 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 535 >; 536 }; 537 538 pinctrl_i2c5: i2c5grp { 539 fsl,pins = < 540 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 541 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 542 >; 543 }; 544 545 pinctrl_pcie0: pcie0grp { 546 fsl,pins = < 547 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */ 548 MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 549 >; 550 }; 551 552 pinctrl_pcie0_reg: pcie0reggrp { 553 fsl,pins = < 554 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 555 >; 556 }; 557 558 pinctrl_pmic: pmicgrp { 559 fsl,pins = < 560 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 561 >; 562 }; 563 564 pinctrl_pca6416_int: pca6416_int_grp { 565 fsl,pins = < 566 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ 567 >; 568 }; 569 570 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 571 fsl,pins = < 572 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 573 >; 574 }; 575 576 pinctrl_uart2: uart2grp { 577 fsl,pins = < 578 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 579 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 580 >; 581 }; 582 583 pinctrl_usb1_vbus: usb1grp { 584 fsl,pins = < 585 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 586 >; 587 }; 588 589 pinctrl_usdhc2: usdhc2grp { 590 fsl,pins = < 591 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 592 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 593 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 594 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 595 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 596 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 597 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 598 >; 599 }; 600 601 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 602 fsl,pins = < 603 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 604 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 605 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 606 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 607 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 608 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 609 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 610 >; 611 }; 612 613 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 614 fsl,pins = < 615 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 616 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 617 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 618 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 619 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 620 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 621 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 622 >; 623 }; 624 625 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 626 fsl,pins = < 627 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 628 >; 629 }; 630 631 pinctrl_usdhc3: usdhc3grp { 632 fsl,pins = < 633 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 634 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 635 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 636 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 637 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 638 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 639 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 640 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 641 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 642 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 643 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 644 >; 645 }; 646 647 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 648 fsl,pins = < 649 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 650 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 651 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 652 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 653 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 654 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 655 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 656 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 657 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 658 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 659 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 660 >; 661 }; 662 663 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 664 fsl,pins = < 665 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 666 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 667 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 668 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 669 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 670 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 671 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 672 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 673 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 674 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 675 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 676 >; 677 }; 678 679 pinctrl_wdog: wdoggrp { 680 fsl,pins = < 681 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 682 >; 683 }; 684}; 685