1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8mp.dtsi"
9
10/ {
11	model = "NXP i.MX8MPlus EVK board";
12	compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
13
14	chosen {
15		stdout-path = &uart2;
16	};
17
18	gpio-leds {
19		compatible = "gpio-leds";
20		pinctrl-names = "default";
21		pinctrl-0 = <&pinctrl_gpio_led>;
22
23		status {
24			label = "yellow:status";
25			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
26			default-state = "on";
27		};
28	};
29
30	memory@40000000 {
31		device_type = "memory";
32		reg = <0x0 0x40000000 0 0xc0000000>,
33		      <0x1 0x00000000 0 0xc0000000>;
34	};
35
36	reg_can1_stby: regulator-can1-stby {
37		compatible = "regulator-fixed";
38		regulator-name = "can1-stby";
39		pinctrl-names = "default";
40		pinctrl-0 = <&pinctrl_flexcan1_reg>;
41		regulator-min-microvolt = <3300000>;
42		regulator-max-microvolt = <3300000>;
43		gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
44		enable-active-high;
45	};
46
47	reg_can2_stby: regulator-can2-stby {
48		compatible = "regulator-fixed";
49		regulator-name = "can2-stby";
50		pinctrl-names = "default";
51		pinctrl-0 = <&pinctrl_flexcan2_reg>;
52		regulator-min-microvolt = <3300000>;
53		regulator-max-microvolt = <3300000>;
54		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
55		enable-active-high;
56	};
57
58	reg_usdhc2_vmmc: regulator-usdhc2 {
59		compatible = "regulator-fixed";
60		pinctrl-names = "default";
61		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
62		regulator-name = "VSD_3V3";
63		regulator-min-microvolt = <3300000>;
64		regulator-max-microvolt = <3300000>;
65		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
66		enable-active-high;
67	};
68};
69
70&flexcan1 {
71	pinctrl-names = "default";
72	pinctrl-0 = <&pinctrl_flexcan1>;
73	xceiver-supply = <&reg_can1_stby>;
74	status = "okay";
75};
76
77&flexcan2 {
78	pinctrl-names = "default";
79	pinctrl-0 = <&pinctrl_flexcan2>;
80	xceiver-supply = <&reg_can2_stby>;
81	status = "disabled";/* can2 pin conflict with pdm */
82};
83
84&fec {
85	pinctrl-names = "default";
86	pinctrl-0 = <&pinctrl_fec>;
87	phy-mode = "rgmii-id";
88	phy-handle = <&ethphy1>;
89	fsl,magic-packet;
90	status = "okay";
91
92	mdio {
93		#address-cells = <1>;
94		#size-cells = <0>;
95
96		ethphy1: ethernet-phy@1 {
97			compatible = "ethernet-phy-ieee802.3-c22";
98			reg = <1>;
99			eee-broken-1000t;
100			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
101		};
102	};
103};
104
105&i2c3 {
106	clock-frequency = <400000>;
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_i2c3>;
109	status = "okay";
110
111	pca6416: gpio@20 {
112		compatible = "ti,tca6416";
113		reg = <0x20>;
114		gpio-controller;
115		#gpio-cells = <2>;
116	};
117};
118
119&snvs_pwrkey {
120	status = "okay";
121};
122
123&uart2 {
124	/* console */
125	pinctrl-names = "default";
126	pinctrl-0 = <&pinctrl_uart2>;
127	status = "okay";
128};
129
130&usb3_phy1 {
131	status = "okay";
132};
133
134&usb3_1 {
135	status = "okay";
136};
137
138&usb_dwc3_1 {
139	pinctrl-names = "default";
140	pinctrl-0 = <&pinctrl_usb1_vbus>;
141	dr_mode = "host";
142	status = "okay";
143};
144
145&usdhc2 {
146	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
147	assigned-clock-rates = <400000000>;
148	pinctrl-names = "default", "state_100mhz", "state_200mhz";
149	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
150	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
151	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
152	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
153	vmmc-supply = <&reg_usdhc2_vmmc>;
154	bus-width = <4>;
155	status = "okay";
156};
157
158&usdhc3 {
159	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
160	assigned-clock-rates = <400000000>;
161	pinctrl-names = "default", "state_100mhz", "state_200mhz";
162	pinctrl-0 = <&pinctrl_usdhc3>;
163	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
164	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
165	bus-width = <8>;
166	non-removable;
167	status = "okay";
168};
169
170&wdog1 {
171	pinctrl-names = "default";
172	pinctrl-0 = <&pinctrl_wdog>;
173	fsl,ext-reset-output;
174	status = "okay";
175};
176
177&iomuxc {
178	pinctrl_fec: fecgrp {
179		fsl,pins = <
180			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
181			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
182			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
183			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
184			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
185			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
186			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
187			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
188			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
189			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
190			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
191			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
192			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
193			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
194			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19
195		>;
196	};
197
198	pinctrl_flexcan1: flexcan1grp {
199		fsl,pins = <
200			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX          0x154
201			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX          0x154
202		>;
203	};
204
205	pinctrl_flexcan2: flexcan2grp {
206		fsl,pins = <
207			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154
208			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154
209		>;
210	};
211
212	pinctrl_flexcan1_reg: flexcan1reggrp {
213		fsl,pins = <
214			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154   /* CAN1_STBY */
215		>;
216	};
217
218	pinctrl_flexcan2_reg: flexcan2reggrp {
219		fsl,pins = <
220			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154   /* CAN2_STBY */
221		>;
222	};
223
224	pinctrl_gpio_led: gpioledgrp {
225		fsl,pins = <
226			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19
227		>;
228	};
229
230	pinctrl_i2c3: i2c3grp {
231		fsl,pins = <
232			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3
233			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3
234		>;
235	};
236
237	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
238		fsl,pins = <
239			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
240		>;
241	};
242
243	pinctrl_uart2: uart2grp {
244		fsl,pins = <
245			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49
246			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x49
247		>;
248	};
249
250	pinctrl_usb1_vbus: usb1grp {
251		fsl,pins = <
252			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x19
253		>;
254	};
255
256	pinctrl_usdhc2: usdhc2grp {
257		fsl,pins = <
258			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
259			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
260			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
261			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
262			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
263			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
264			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
265		>;
266	};
267
268	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
269		fsl,pins = <
270			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
271			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
272			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
273			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
274			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
275			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
276			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
277		>;
278	};
279
280	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
281		fsl,pins = <
282			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
283			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
284			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
285			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
286			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
287			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
288			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
289		>;
290	};
291
292	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
293		fsl,pins = <
294			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
295		>;
296	};
297
298	pinctrl_usdhc3: usdhc3grp {
299		fsl,pins = <
300			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
301			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
302			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
303			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
304			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
305			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
306			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
307			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
308			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
309			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
310			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
311		>;
312	};
313
314	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
315		fsl,pins = <
316			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
317			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
318			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
319			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
320			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
321			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
322			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
323			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
324			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
325			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
326			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
327		>;
328	};
329
330	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
331		fsl,pins = <
332			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
333			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
334			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
335			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
336			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
337			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
338			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
339			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
340			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
341			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
342			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
343		>;
344	};
345
346	pinctrl_wdog: wdoggrp {
347		fsl,pins = <
348			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166
349		>;
350	};
351};
352