1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9#include "imx8mp.dtsi" 10 11/ { 12 model = "NXP i.MX8MPlus EVK board"; 13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; 14 15 chosen { 16 stdout-path = &uart2; 17 }; 18 19 gpio-leds { 20 compatible = "gpio-leds"; 21 pinctrl-names = "default"; 22 pinctrl-0 = <&pinctrl_gpio_led>; 23 24 status { 25 label = "yellow:status"; 26 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 27 default-state = "on"; 28 }; 29 }; 30 31 memory@40000000 { 32 device_type = "memory"; 33 reg = <0x0 0x40000000 0 0xc0000000>, 34 <0x1 0x00000000 0 0xc0000000>; 35 }; 36 37 pcie0_refclk: pcie0-refclk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <100000000>; 41 }; 42 43 reg_audio_pwr: regulator-audio-pwr { 44 compatible = "regulator-fixed"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_audio_pwr_reg>; 47 regulator-name = "audio-pwr"; 48 regulator-min-microvolt = <3300000>; 49 regulator-max-microvolt = <3300000>; 50 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 51 enable-active-high; 52 }; 53 54 reg_can1_stby: regulator-can1-stby { 55 compatible = "regulator-fixed"; 56 regulator-name = "can1-stby"; 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_flexcan1_reg>; 59 regulator-min-microvolt = <3300000>; 60 regulator-max-microvolt = <3300000>; 61 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; 62 enable-active-high; 63 }; 64 65 reg_can2_stby: regulator-can2-stby { 66 compatible = "regulator-fixed"; 67 regulator-name = "can2-stby"; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&pinctrl_flexcan2_reg>; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 73 enable-active-high; 74 }; 75 76 reg_pcie0: regulator-pcie { 77 compatible = "regulator-fixed"; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pinctrl_pcie0_reg>; 80 regulator-name = "MPCIE_3V3"; 81 regulator-min-microvolt = <3300000>; 82 regulator-max-microvolt = <3300000>; 83 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 84 enable-active-high; 85 }; 86 87 reg_usdhc2_vmmc: regulator-usdhc2 { 88 compatible = "regulator-fixed"; 89 pinctrl-names = "default"; 90 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 91 regulator-name = "VSD_3V3"; 92 regulator-min-microvolt = <3300000>; 93 regulator-max-microvolt = <3300000>; 94 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 95 enable-active-high; 96 }; 97 98 sound { 99 compatible = "simple-audio-card"; 100 simple-audio-card,name = "wm8960-audio"; 101 simple-audio-card,format = "i2s"; 102 simple-audio-card,frame-master = <&cpudai>; 103 simple-audio-card,bitclock-master = <&cpudai>; 104 simple-audio-card,widgets = 105 "Headphone", "Headphone Jack", 106 "Speaker", "External Speaker", 107 "Microphone", "Mic Jack"; 108 simple-audio-card,routing = 109 "Headphone Jack", "HP_L", 110 "Headphone Jack", "HP_R", 111 "External Speaker", "SPK_LP", 112 "External Speaker", "SPK_LN", 113 "External Speaker", "SPK_RP", 114 "External Speaker", "SPK_RN", 115 "LINPUT1", "Mic Jack", 116 "LINPUT3", "Mic Jack", 117 "Mic Jack", "MICB"; 118 119 cpudai: simple-audio-card,cpu { 120 sound-dai = <&sai3>; 121 }; 122 123 simple-audio-card,codec { 124 sound-dai = <&wm8960>; 125 }; 126 127 }; 128}; 129 130&flexspi { 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_flexspi0>; 133 status = "okay"; 134 135 flash@0 { 136 compatible = "jedec,spi-nor"; 137 reg = <0>; 138 spi-max-frequency = <80000000>; 139 spi-tx-bus-width = <1>; 140 spi-rx-bus-width = <4>; 141 }; 142}; 143 144&A53_0 { 145 cpu-supply = <®_arm>; 146}; 147 148&A53_1 { 149 cpu-supply = <®_arm>; 150}; 151 152&A53_2 { 153 cpu-supply = <®_arm>; 154}; 155 156&A53_3 { 157 cpu-supply = <®_arm>; 158}; 159 160&eqos { 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_eqos>; 163 phy-mode = "rgmii-id"; 164 phy-handle = <ðphy0>; 165 snps,force_thresh_dma_mode; 166 snps,mtl-tx-config = <&mtl_tx_setup>; 167 snps,mtl-rx-config = <&mtl_rx_setup>; 168 status = "okay"; 169 170 mdio { 171 compatible = "snps,dwmac-mdio"; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 175 ethphy0: ethernet-phy@1 { 176 compatible = "ethernet-phy-ieee802.3-c22"; 177 reg = <1>; 178 eee-broken-1000t; 179 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 180 reset-assert-us = <10000>; 181 reset-deassert-us = <80000>; 182 realtek,clkout-disable; 183 }; 184 }; 185 186 mtl_tx_setup: tx-queues-config { 187 snps,tx-queues-to-use = <5>; 188 snps,tx-sched-sp; 189 190 queue0 { 191 snps,dcb-algorithm; 192 snps,priority = <0x1>; 193 }; 194 195 queue1 { 196 snps,dcb-algorithm; 197 snps,priority = <0x2>; 198 }; 199 200 queue2 { 201 snps,dcb-algorithm; 202 snps,priority = <0x4>; 203 }; 204 205 queue3 { 206 snps,dcb-algorithm; 207 snps,priority = <0x8>; 208 }; 209 210 queue4 { 211 snps,dcb-algorithm; 212 snps,priority = <0xf0>; 213 }; 214 }; 215 216 mtl_rx_setup: rx-queues-config { 217 snps,rx-queues-to-use = <5>; 218 snps,rx-sched-sp; 219 220 queue0 { 221 snps,dcb-algorithm; 222 snps,priority = <0x1>; 223 snps,map-to-dma-channel = <0>; 224 }; 225 226 queue1 { 227 snps,dcb-algorithm; 228 snps,priority = <0x2>; 229 snps,map-to-dma-channel = <1>; 230 }; 231 232 queue2 { 233 snps,dcb-algorithm; 234 snps,priority = <0x4>; 235 snps,map-to-dma-channel = <2>; 236 }; 237 238 queue3 { 239 snps,dcb-algorithm; 240 snps,priority = <0x8>; 241 snps,map-to-dma-channel = <3>; 242 }; 243 244 queue4 { 245 snps,dcb-algorithm; 246 snps,priority = <0xf0>; 247 snps,map-to-dma-channel = <4>; 248 }; 249 }; 250}; 251 252&fec { 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_fec>; 255 phy-mode = "rgmii-id"; 256 phy-handle = <ðphy1>; 257 fsl,magic-packet; 258 status = "okay"; 259 260 mdio { 261 #address-cells = <1>; 262 #size-cells = <0>; 263 264 ethphy1: ethernet-phy@1 { 265 compatible = "ethernet-phy-ieee802.3-c22"; 266 reg = <1>; 267 eee-broken-1000t; 268 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 269 reset-assert-us = <10000>; 270 reset-deassert-us = <80000>; 271 realtek,clkout-disable; 272 }; 273 }; 274}; 275 276&flexcan1 { 277 pinctrl-names = "default"; 278 pinctrl-0 = <&pinctrl_flexcan1>; 279 xceiver-supply = <®_can1_stby>; 280 status = "okay"; 281}; 282 283&flexcan2 { 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_flexcan2>; 286 xceiver-supply = <®_can2_stby>; 287 status = "disabled";/* can2 pin conflict with pdm */ 288}; 289 290&i2c1 { 291 clock-frequency = <400000>; 292 pinctrl-names = "default"; 293 pinctrl-0 = <&pinctrl_i2c1>; 294 status = "okay"; 295 296 pmic@25 { 297 compatible = "nxp,pca9450c"; 298 reg = <0x25>; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_pmic>; 301 interrupt-parent = <&gpio1>; 302 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 303 304 regulators { 305 BUCK1 { 306 regulator-name = "BUCK1"; 307 regulator-min-microvolt = <720000>; 308 regulator-max-microvolt = <1000000>; 309 regulator-boot-on; 310 regulator-always-on; 311 regulator-ramp-delay = <3125>; 312 }; 313 314 reg_arm: BUCK2 { 315 regulator-name = "BUCK2"; 316 regulator-min-microvolt = <720000>; 317 regulator-max-microvolt = <1025000>; 318 regulator-boot-on; 319 regulator-always-on; 320 regulator-ramp-delay = <3125>; 321 nxp,dvs-run-voltage = <950000>; 322 nxp,dvs-standby-voltage = <850000>; 323 }; 324 325 BUCK4 { 326 regulator-name = "BUCK4"; 327 regulator-min-microvolt = <3000000>; 328 regulator-max-microvolt = <3600000>; 329 regulator-boot-on; 330 regulator-always-on; 331 }; 332 333 BUCK5 { 334 regulator-name = "BUCK5"; 335 regulator-min-microvolt = <1650000>; 336 regulator-max-microvolt = <1950000>; 337 regulator-boot-on; 338 regulator-always-on; 339 }; 340 341 BUCK6 { 342 regulator-name = "BUCK6"; 343 regulator-min-microvolt = <1045000>; 344 regulator-max-microvolt = <1155000>; 345 regulator-boot-on; 346 regulator-always-on; 347 }; 348 349 LDO1 { 350 regulator-name = "LDO1"; 351 regulator-min-microvolt = <1650000>; 352 regulator-max-microvolt = <1950000>; 353 regulator-boot-on; 354 regulator-always-on; 355 }; 356 357 LDO3 { 358 regulator-name = "LDO3"; 359 regulator-min-microvolt = <1710000>; 360 regulator-max-microvolt = <1890000>; 361 regulator-boot-on; 362 regulator-always-on; 363 }; 364 365 LDO5 { 366 regulator-name = "LDO5"; 367 regulator-min-microvolt = <1800000>; 368 regulator-max-microvolt = <3300000>; 369 regulator-boot-on; 370 regulator-always-on; 371 }; 372 }; 373 }; 374}; 375 376&i2c2 { 377 clock-frequency = <400000>; 378 pinctrl-names = "default"; 379 pinctrl-0 = <&pinctrl_i2c2>; 380 status = "okay"; 381}; 382 383&i2c3 { 384 clock-frequency = <400000>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_i2c3>; 387 status = "okay"; 388 389 wm8960: codec@1a { 390 compatible = "wlf,wm8960"; 391 reg = <0x1a>; 392 #sound-dai-cells = <0>; 393 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; 394 clock-names = "mclk"; 395 wlf,shared-lrclk; 396 wlf,hp-cfg = <3 2 3>; 397 wlf,gpio-cfg = <1 3>; 398 SPKVDD1-supply = <®_audio_pwr>; 399 }; 400 401 pca6416: gpio@20 { 402 compatible = "ti,tca6416"; 403 reg = <0x20>; 404 gpio-controller; 405 #gpio-cells = <2>; 406 interrupt-controller; 407 #interrupt-cells = <2>; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&pinctrl_pca6416_int>; 410 interrupt-parent = <&gpio1>; 411 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 412 gpio-line-names = "EXT_PWREN1", 413 "EXT_PWREN2", 414 "CAN1/I2C5_SEL", 415 "PDM/CAN2_SEL", 416 "FAN_EN", 417 "PWR_MEAS_IO1", 418 "PWR_MEAS_IO2", 419 "EXP_P0_7", 420 "EXP_P1_0", 421 "EXP_P1_1", 422 "EXP_P1_2", 423 "EXP_P1_3", 424 "EXP_P1_4", 425 "EXP_P1_5", 426 "EXP_P1_6", 427 "EXP_P1_7"; 428 }; 429}; 430 431/* I2C on expansion connector J22. */ 432&i2c5 { 433 clock-frequency = <100000>; /* Lower clock speed for external bus. */ 434 pinctrl-names = "default"; 435 pinctrl-0 = <&pinctrl_i2c5>; 436 status = "disabled"; /* can1 pins conflict with i2c5 */ 437 438 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions: 439 * LOW: CAN1 (default, pull-down) 440 * HIGH: I2C5 441 * You need to set it to high to enable I2C5 (for example, add gpio-hog 442 * in pca6416 node). 443 */ 444}; 445 446&pcie_phy { 447 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 448 clocks = <&pcie0_refclk>; 449 clock-names = "ref"; 450 status = "okay"; 451}; 452 453&pcie { 454 pinctrl-names = "default"; 455 pinctrl-0 = <&pinctrl_pcie0>; 456 reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; 457 vpcie-supply = <®_pcie0>; 458 status = "okay"; 459}; 460 461&pwm1 { 462 pinctrl-names = "default"; 463 pinctrl-0 = <&pinctrl_pwm1>; 464 status = "okay"; 465}; 466 467&pwm2 { 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pinctrl_pwm2>; 470 status = "okay"; 471}; 472 473&pwm4 { 474 pinctrl-names = "default"; 475 pinctrl-0 = <&pinctrl_pwm4>; 476 status = "okay"; 477}; 478 479&sai3 { 480 pinctrl-names = "default"; 481 pinctrl-0 = <&pinctrl_sai3>; 482 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 483 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 484 assigned-clock-rates = <12288000>; 485 fsl,sai-mclk-direction-output; 486 status = "okay"; 487}; 488 489&snvs_pwrkey { 490 status = "okay"; 491}; 492 493&uart1 { /* BT */ 494 pinctrl-names = "default"; 495 pinctrl-0 = <&pinctrl_uart1>; 496 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 497 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 498 uart-has-rtscts; 499 status = "okay"; 500}; 501 502&uart2 { 503 /* console */ 504 pinctrl-names = "default"; 505 pinctrl-0 = <&pinctrl_uart2>; 506 status = "okay"; 507}; 508 509&usb3_phy1 { 510 status = "okay"; 511}; 512 513&usb3_1 { 514 status = "okay"; 515}; 516 517&usb_dwc3_1 { 518 pinctrl-names = "default"; 519 pinctrl-0 = <&pinctrl_usb1_vbus>; 520 dr_mode = "host"; 521 status = "okay"; 522}; 523 524&uart3 { 525 pinctrl-names = "default"; 526 pinctrl-0 = <&pinctrl_uart3>; 527 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 528 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 529 uart-has-rtscts; 530 status = "okay"; 531}; 532 533&usdhc2 { 534 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 535 assigned-clock-rates = <400000000>; 536 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 537 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 538 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 539 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 540 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 541 vmmc-supply = <®_usdhc2_vmmc>; 542 bus-width = <4>; 543 status = "okay"; 544}; 545 546&usdhc3 { 547 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 548 assigned-clock-rates = <400000000>; 549 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 550 pinctrl-0 = <&pinctrl_usdhc3>; 551 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 552 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 553 bus-width = <8>; 554 non-removable; 555 status = "okay"; 556}; 557 558&wdog1 { 559 pinctrl-names = "default"; 560 pinctrl-0 = <&pinctrl_wdog>; 561 fsl,ext-reset-output; 562 status = "okay"; 563}; 564 565&iomuxc { 566 pinctrl_audio_pwr_reg: audiopwrreggrp { 567 fsl,pins = < 568 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 569 >; 570 }; 571 572 pinctrl_eqos: eqosgrp { 573 fsl,pins = < 574 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 575 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 576 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 577 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 578 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 579 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 580 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 581 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 582 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 583 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 584 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 585 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 586 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 587 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 588 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 589 >; 590 }; 591 592 pinctrl_fec: fecgrp { 593 fsl,pins = < 594 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 595 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 596 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 597 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 598 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 599 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 600 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 601 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 602 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 603 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 604 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 605 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 606 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 607 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 608 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 609 >; 610 }; 611 612 pinctrl_flexcan1: flexcan1grp { 613 fsl,pins = < 614 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 615 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 616 >; 617 }; 618 619 pinctrl_flexcan2: flexcan2grp { 620 fsl,pins = < 621 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 622 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 623 >; 624 }; 625 626 pinctrl_flexcan1_reg: flexcan1reggrp { 627 fsl,pins = < 628 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ 629 >; 630 }; 631 632 pinctrl_flexcan2_reg: flexcan2reggrp { 633 fsl,pins = < 634 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ 635 >; 636 }; 637 638 pinctrl_flexspi0: flexspi0grp { 639 fsl,pins = < 640 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 641 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 642 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 643 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 644 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 645 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 646 >; 647 }; 648 649 pinctrl_gpio_led: gpioledgrp { 650 fsl,pins = < 651 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 652 >; 653 }; 654 655 pinctrl_i2c1: i2c1grp { 656 fsl,pins = < 657 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 658 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 659 >; 660 }; 661 662 pinctrl_i2c2: i2c2grp { 663 fsl,pins = < 664 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 665 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 666 >; 667 }; 668 669 pinctrl_i2c3: i2c3grp { 670 fsl,pins = < 671 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 672 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 673 >; 674 }; 675 676 pinctrl_i2c5: i2c5grp { 677 fsl,pins = < 678 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 679 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 680 >; 681 }; 682 683 pinctrl_pcie0: pcie0grp { 684 fsl,pins = < 685 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */ 686 MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40 687 >; 688 }; 689 690 pinctrl_pcie0_reg: pcie0reggrp { 691 fsl,pins = < 692 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 693 >; 694 }; 695 696 pinctrl_pmic: pmicgrp { 697 fsl,pins = < 698 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 699 >; 700 }; 701 702 pinctrl_pca6416_int: pca6416_int_grp { 703 fsl,pins = < 704 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ 705 >; 706 }; 707 708 pinctrl_pwm1: pwm1grp { 709 fsl,pins = < 710 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 711 >; 712 }; 713 714 pinctrl_pwm2: pwm2grp { 715 fsl,pins = < 716 MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 717 >; 718 }; 719 720 pinctrl_pwm4: pwm4grp { 721 fsl,pins = < 722 MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 723 >; 724 }; 725 726 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 727 fsl,pins = < 728 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 729 >; 730 }; 731 732 pinctrl_uart1: uart1grp { 733 fsl,pins = < 734 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 735 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 736 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 737 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 738 >; 739 }; 740 741 pinctrl_sai3: sai3grp { 742 fsl,pins = < 743 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 744 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 745 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 746 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 747 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 748 >; 749 }; 750 751 pinctrl_uart2: uart2grp { 752 fsl,pins = < 753 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 754 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 755 >; 756 }; 757 758 pinctrl_usb1_vbus: usb1grp { 759 fsl,pins = < 760 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 761 >; 762 }; 763 764 pinctrl_uart3: uart3grp { 765 fsl,pins = < 766 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 767 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 768 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 769 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 770 >; 771 }; 772 773 pinctrl_usdhc2: usdhc2grp { 774 fsl,pins = < 775 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 776 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 777 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 778 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 779 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 780 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 781 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 782 >; 783 }; 784 785 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 786 fsl,pins = < 787 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 788 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 789 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 790 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 791 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 792 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 793 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 794 >; 795 }; 796 797 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 798 fsl,pins = < 799 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 800 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 801 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 802 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 803 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 804 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 805 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 806 >; 807 }; 808 809 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 810 fsl,pins = < 811 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 812 >; 813 }; 814 815 pinctrl_usdhc3: usdhc3grp { 816 fsl,pins = < 817 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 818 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 819 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 820 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 821 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 822 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 823 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 824 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 825 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 826 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 827 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 828 >; 829 }; 830 831 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 832 fsl,pins = < 833 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 834 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 835 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 836 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 837 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 838 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 839 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 840 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 841 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 842 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 843 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 844 >; 845 }; 846 847 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 848 fsl,pins = < 849 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 850 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 851 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 852 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 853 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 854 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 855 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 856 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 857 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 858 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 859 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 860 >; 861 }; 862 863 pinctrl_wdog: wdoggrp { 864 fsl,pins = < 865 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 866 >; 867 }; 868}; 869