1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9#include "imx8mp.dtsi" 10 11/ { 12 model = "NXP i.MX8MPlus EVK board"; 13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; 14 15 chosen { 16 stdout-path = &uart2; 17 }; 18 19 hdmi-connector { 20 compatible = "hdmi-connector"; 21 label = "hdmi"; 22 type = "a"; 23 24 port { 25 hdmi_connector_in: endpoint { 26 remote-endpoint = <&adv7535_out>; 27 }; 28 }; 29 }; 30 31 gpio-leds { 32 compatible = "gpio-leds"; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_gpio_led>; 35 36 status { 37 label = "yellow:status"; 38 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 39 default-state = "on"; 40 }; 41 }; 42 43 memory@40000000 { 44 device_type = "memory"; 45 reg = <0x0 0x40000000 0 0xc0000000>, 46 <0x1 0x00000000 0 0xc0000000>; 47 }; 48 49 pcie0_refclk: pcie0-refclk { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <100000000>; 53 }; 54 55 reg_audio_pwr: regulator-audio-pwr { 56 compatible = "regulator-fixed"; 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_audio_pwr_reg>; 59 regulator-name = "audio-pwr"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 63 enable-active-high; 64 }; 65 66 reg_can1_stby: regulator-can1-stby { 67 compatible = "regulator-fixed"; 68 regulator-name = "can1-stby"; 69 pinctrl-names = "default"; 70 pinctrl-0 = <&pinctrl_flexcan1_reg>; 71 regulator-min-microvolt = <3300000>; 72 regulator-max-microvolt = <3300000>; 73 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; 74 enable-active-high; 75 }; 76 77 reg_can2_stby: regulator-can2-stby { 78 compatible = "regulator-fixed"; 79 regulator-name = "can2-stby"; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_flexcan2_reg>; 82 regulator-min-microvolt = <3300000>; 83 regulator-max-microvolt = <3300000>; 84 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 85 enable-active-high; 86 }; 87 88 reg_pcie0: regulator-pcie { 89 compatible = "regulator-fixed"; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_pcie0_reg>; 92 regulator-name = "MPCIE_3V3"; 93 regulator-min-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>; 95 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 96 enable-active-high; 97 }; 98 99 reg_usdhc2_vmmc: regulator-usdhc2 { 100 compatible = "regulator-fixed"; 101 pinctrl-names = "default"; 102 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 103 regulator-name = "VSD_3V3"; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 107 enable-active-high; 108 }; 109 110 reg_vext_3v3: regulator-vext-3v3 { 111 compatible = "regulator-fixed"; 112 regulator-name = "VEXT_3V3"; 113 regulator-min-microvolt = <3300000>; 114 regulator-max-microvolt = <3300000>; 115 }; 116 117 sound { 118 compatible = "simple-audio-card"; 119 simple-audio-card,name = "wm8960-audio"; 120 simple-audio-card,format = "i2s"; 121 simple-audio-card,frame-master = <&cpudai>; 122 simple-audio-card,bitclock-master = <&cpudai>; 123 simple-audio-card,widgets = 124 "Headphone", "Headphone Jack", 125 "Speaker", "External Speaker", 126 "Microphone", "Mic Jack"; 127 simple-audio-card,routing = 128 "Headphone Jack", "HP_L", 129 "Headphone Jack", "HP_R", 130 "External Speaker", "SPK_LP", 131 "External Speaker", "SPK_LN", 132 "External Speaker", "SPK_RP", 133 "External Speaker", "SPK_RN", 134 "LINPUT1", "Mic Jack", 135 "LINPUT3", "Mic Jack", 136 "Mic Jack", "MICB"; 137 138 cpudai: simple-audio-card,cpu { 139 sound-dai = <&sai3>; 140 }; 141 142 simple-audio-card,codec { 143 sound-dai = <&wm8960>; 144 }; 145 146 }; 147}; 148 149&flexspi { 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_flexspi0>; 152 status = "okay"; 153 154 flash@0 { 155 compatible = "jedec,spi-nor"; 156 reg = <0>; 157 spi-max-frequency = <80000000>; 158 spi-tx-bus-width = <1>; 159 spi-rx-bus-width = <4>; 160 }; 161}; 162 163&A53_0 { 164 cpu-supply = <®_arm>; 165}; 166 167&A53_1 { 168 cpu-supply = <®_arm>; 169}; 170 171&A53_2 { 172 cpu-supply = <®_arm>; 173}; 174 175&A53_3 { 176 cpu-supply = <®_arm>; 177}; 178 179&eqos { 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_eqos>; 182 phy-mode = "rgmii-id"; 183 phy-handle = <ðphy0>; 184 snps,force_thresh_dma_mode; 185 snps,mtl-tx-config = <&mtl_tx_setup>; 186 snps,mtl-rx-config = <&mtl_rx_setup>; 187 status = "okay"; 188 189 mdio { 190 compatible = "snps,dwmac-mdio"; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 194 ethphy0: ethernet-phy@1 { 195 compatible = "ethernet-phy-ieee802.3-c22"; 196 reg = <1>; 197 eee-broken-1000t; 198 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 199 reset-assert-us = <10000>; 200 reset-deassert-us = <80000>; 201 realtek,clkout-disable; 202 }; 203 }; 204 205 mtl_tx_setup: tx-queues-config { 206 snps,tx-queues-to-use = <5>; 207 snps,tx-sched-sp; 208 209 queue0 { 210 snps,dcb-algorithm; 211 snps,priority = <0x1>; 212 }; 213 214 queue1 { 215 snps,dcb-algorithm; 216 snps,priority = <0x2>; 217 }; 218 219 queue2 { 220 snps,dcb-algorithm; 221 snps,priority = <0x4>; 222 }; 223 224 queue3 { 225 snps,dcb-algorithm; 226 snps,priority = <0x8>; 227 }; 228 229 queue4 { 230 snps,dcb-algorithm; 231 snps,priority = <0xf0>; 232 }; 233 }; 234 235 mtl_rx_setup: rx-queues-config { 236 snps,rx-queues-to-use = <5>; 237 snps,rx-sched-sp; 238 239 queue0 { 240 snps,dcb-algorithm; 241 snps,priority = <0x1>; 242 snps,map-to-dma-channel = <0>; 243 }; 244 245 queue1 { 246 snps,dcb-algorithm; 247 snps,priority = <0x2>; 248 snps,map-to-dma-channel = <1>; 249 }; 250 251 queue2 { 252 snps,dcb-algorithm; 253 snps,priority = <0x4>; 254 snps,map-to-dma-channel = <2>; 255 }; 256 257 queue3 { 258 snps,dcb-algorithm; 259 snps,priority = <0x8>; 260 snps,map-to-dma-channel = <3>; 261 }; 262 263 queue4 { 264 snps,dcb-algorithm; 265 snps,priority = <0xf0>; 266 snps,map-to-dma-channel = <4>; 267 }; 268 }; 269}; 270 271&fec { 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pinctrl_fec>; 274 phy-mode = "rgmii-id"; 275 phy-handle = <ðphy1>; 276 fsl,magic-packet; 277 status = "okay"; 278 279 mdio { 280 #address-cells = <1>; 281 #size-cells = <0>; 282 283 ethphy1: ethernet-phy@1 { 284 compatible = "ethernet-phy-ieee802.3-c22"; 285 reg = <1>; 286 eee-broken-1000t; 287 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 288 reset-assert-us = <10000>; 289 reset-deassert-us = <80000>; 290 realtek,clkout-disable; 291 }; 292 }; 293}; 294 295&flexcan1 { 296 pinctrl-names = "default"; 297 pinctrl-0 = <&pinctrl_flexcan1>; 298 xceiver-supply = <®_can1_stby>; 299 status = "okay"; 300}; 301 302&flexcan2 { 303 pinctrl-names = "default"; 304 pinctrl-0 = <&pinctrl_flexcan2>; 305 xceiver-supply = <®_can2_stby>; 306 status = "disabled";/* can2 pin conflict with pdm */ 307}; 308 309&i2c1 { 310 clock-frequency = <400000>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_i2c1>; 313 status = "okay"; 314 315 pmic@25 { 316 compatible = "nxp,pca9450c"; 317 reg = <0x25>; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&pinctrl_pmic>; 320 interrupt-parent = <&gpio1>; 321 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 322 323 regulators { 324 BUCK1 { 325 regulator-name = "BUCK1"; 326 regulator-min-microvolt = <720000>; 327 regulator-max-microvolt = <1000000>; 328 regulator-boot-on; 329 regulator-always-on; 330 regulator-ramp-delay = <3125>; 331 }; 332 333 reg_arm: BUCK2 { 334 regulator-name = "BUCK2"; 335 regulator-min-microvolt = <720000>; 336 regulator-max-microvolt = <1025000>; 337 regulator-boot-on; 338 regulator-always-on; 339 regulator-ramp-delay = <3125>; 340 nxp,dvs-run-voltage = <950000>; 341 nxp,dvs-standby-voltage = <850000>; 342 }; 343 344 BUCK4 { 345 regulator-name = "BUCK4"; 346 regulator-min-microvolt = <3000000>; 347 regulator-max-microvolt = <3600000>; 348 regulator-boot-on; 349 regulator-always-on; 350 }; 351 352 reg_buck5: BUCK5 { 353 regulator-name = "BUCK5"; 354 regulator-min-microvolt = <1650000>; 355 regulator-max-microvolt = <1950000>; 356 regulator-boot-on; 357 regulator-always-on; 358 }; 359 360 BUCK6 { 361 regulator-name = "BUCK6"; 362 regulator-min-microvolt = <1045000>; 363 regulator-max-microvolt = <1155000>; 364 regulator-boot-on; 365 regulator-always-on; 366 }; 367 368 LDO1 { 369 regulator-name = "LDO1"; 370 regulator-min-microvolt = <1650000>; 371 regulator-max-microvolt = <1950000>; 372 regulator-boot-on; 373 regulator-always-on; 374 }; 375 376 LDO3 { 377 regulator-name = "LDO3"; 378 regulator-min-microvolt = <1710000>; 379 regulator-max-microvolt = <1890000>; 380 regulator-boot-on; 381 regulator-always-on; 382 }; 383 384 LDO5 { 385 regulator-name = "LDO5"; 386 regulator-min-microvolt = <1800000>; 387 regulator-max-microvolt = <3300000>; 388 regulator-boot-on; 389 regulator-always-on; 390 }; 391 }; 392 }; 393}; 394 395&i2c2 { 396 clock-frequency = <400000>; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&pinctrl_i2c2>; 399 status = "okay"; 400 401 hdmi@3d { 402 compatible = "adi,adv7535"; 403 reg = <0x3d>; 404 interrupt-parent = <&gpio1>; 405 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 406 adi,dsi-lanes = <4>; 407 avdd-supply = <®_buck5>; 408 dvdd-supply = <®_buck5>; 409 pvdd-supply = <®_buck5>; 410 a2vdd-supply = <®_buck5>; 411 v3p3-supply = <®_vext_3v3>; 412 v1p2-supply = <®_buck5>; 413 414 ports { 415 #address-cells = <1>; 416 #size-cells = <0>; 417 418 port@0 { 419 reg = <0>; 420 421 adv7535_in: endpoint { 422 remote-endpoint = <&dsi_out>; 423 }; 424 }; 425 426 port@1 { 427 reg = <1>; 428 429 adv7535_out: endpoint { 430 remote-endpoint = <&hdmi_connector_in>; 431 }; 432 }; 433 434 }; 435 }; 436}; 437 438&i2c3 { 439 clock-frequency = <400000>; 440 pinctrl-names = "default"; 441 pinctrl-0 = <&pinctrl_i2c3>; 442 status = "okay"; 443 444 wm8960: codec@1a { 445 compatible = "wlf,wm8960"; 446 reg = <0x1a>; 447 #sound-dai-cells = <0>; 448 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; 449 clock-names = "mclk"; 450 wlf,shared-lrclk; 451 wlf,hp-cfg = <3 2 3>; 452 wlf,gpio-cfg = <1 3>; 453 SPKVDD1-supply = <®_audio_pwr>; 454 }; 455 456 pca6416: gpio@20 { 457 compatible = "ti,tca6416"; 458 reg = <0x20>; 459 gpio-controller; 460 #gpio-cells = <2>; 461 interrupt-controller; 462 #interrupt-cells = <2>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&pinctrl_pca6416_int>; 465 interrupt-parent = <&gpio1>; 466 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 467 gpio-line-names = "EXT_PWREN1", 468 "EXT_PWREN2", 469 "CAN1/I2C5_SEL", 470 "PDM/CAN2_SEL", 471 "FAN_EN", 472 "PWR_MEAS_IO1", 473 "PWR_MEAS_IO2", 474 "EXP_P0_7", 475 "EXP_P1_0", 476 "EXP_P1_1", 477 "EXP_P1_2", 478 "EXP_P1_3", 479 "EXP_P1_4", 480 "EXP_P1_5", 481 "EXP_P1_6", 482 "EXP_P1_7"; 483 }; 484}; 485 486/* I2C on expansion connector J22. */ 487&i2c5 { 488 clock-frequency = <100000>; /* Lower clock speed for external bus. */ 489 pinctrl-names = "default"; 490 pinctrl-0 = <&pinctrl_i2c5>; 491 status = "disabled"; /* can1 pins conflict with i2c5 */ 492 493 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions: 494 * LOW: CAN1 (default, pull-down) 495 * HIGH: I2C5 496 * You need to set it to high to enable I2C5 (for example, add gpio-hog 497 * in pca6416 node). 498 */ 499}; 500 501&lcdif1 { 502 status = "okay"; 503}; 504 505&mipi_dsi { 506 samsung,esc-clock-frequency = <10000000>; 507 status = "okay"; 508 509 ports { 510 port@1 { 511 reg = <1>; 512 513 dsi_out: endpoint { 514 remote-endpoint = <&adv7535_in>; 515 data-lanes = <1 2 3 4>; 516 }; 517 }; 518 }; 519}; 520 521&pcie_phy { 522 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 523 clocks = <&pcie0_refclk>; 524 clock-names = "ref"; 525 status = "okay"; 526}; 527 528&pcie { 529 pinctrl-names = "default"; 530 pinctrl-0 = <&pinctrl_pcie0>; 531 reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; 532 vpcie-supply = <®_pcie0>; 533 status = "okay"; 534}; 535 536&pwm1 { 537 pinctrl-names = "default"; 538 pinctrl-0 = <&pinctrl_pwm1>; 539 status = "okay"; 540}; 541 542&pwm2 { 543 pinctrl-names = "default"; 544 pinctrl-0 = <&pinctrl_pwm2>; 545 status = "okay"; 546}; 547 548&pwm4 { 549 pinctrl-names = "default"; 550 pinctrl-0 = <&pinctrl_pwm4>; 551 status = "okay"; 552}; 553 554&sai3 { 555 pinctrl-names = "default"; 556 pinctrl-0 = <&pinctrl_sai3>; 557 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 558 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 559 assigned-clock-rates = <12288000>; 560 fsl,sai-mclk-direction-output; 561 status = "okay"; 562}; 563 564&snvs_pwrkey { 565 status = "okay"; 566}; 567 568&uart1 { /* BT */ 569 pinctrl-names = "default"; 570 pinctrl-0 = <&pinctrl_uart1>; 571 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 572 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 573 uart-has-rtscts; 574 status = "okay"; 575}; 576 577&uart2 { 578 /* console */ 579 pinctrl-names = "default"; 580 pinctrl-0 = <&pinctrl_uart2>; 581 status = "okay"; 582}; 583 584&usb3_phy1 { 585 status = "okay"; 586}; 587 588&usb3_1 { 589 status = "okay"; 590}; 591 592&usb_dwc3_1 { 593 pinctrl-names = "default"; 594 pinctrl-0 = <&pinctrl_usb1_vbus>; 595 dr_mode = "host"; 596 status = "okay"; 597}; 598 599&uart3 { 600 pinctrl-names = "default"; 601 pinctrl-0 = <&pinctrl_uart3>; 602 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 603 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 604 uart-has-rtscts; 605 status = "okay"; 606}; 607 608&usdhc2 { 609 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 610 assigned-clock-rates = <400000000>; 611 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 612 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 613 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 614 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 615 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 616 vmmc-supply = <®_usdhc2_vmmc>; 617 bus-width = <4>; 618 status = "okay"; 619}; 620 621&usdhc3 { 622 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 623 assigned-clock-rates = <400000000>; 624 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 625 pinctrl-0 = <&pinctrl_usdhc3>; 626 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 627 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 628 bus-width = <8>; 629 non-removable; 630 status = "okay"; 631}; 632 633&wdog1 { 634 pinctrl-names = "default"; 635 pinctrl-0 = <&pinctrl_wdog>; 636 fsl,ext-reset-output; 637 status = "okay"; 638}; 639 640&iomuxc { 641 pinctrl_audio_pwr_reg: audiopwrreggrp { 642 fsl,pins = < 643 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 644 >; 645 }; 646 647 pinctrl_eqos: eqosgrp { 648 fsl,pins = < 649 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 650 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 651 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 652 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 653 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 654 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 655 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 656 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 657 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 658 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 659 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 660 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 661 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 662 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 663 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 664 >; 665 }; 666 667 pinctrl_fec: fecgrp { 668 fsl,pins = < 669 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 670 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 671 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 672 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 673 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 674 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 675 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 676 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 677 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 678 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 679 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 680 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 681 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 682 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 683 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 684 >; 685 }; 686 687 pinctrl_flexcan1: flexcan1grp { 688 fsl,pins = < 689 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 690 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 691 >; 692 }; 693 694 pinctrl_flexcan2: flexcan2grp { 695 fsl,pins = < 696 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 697 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 698 >; 699 }; 700 701 pinctrl_flexcan1_reg: flexcan1reggrp { 702 fsl,pins = < 703 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ 704 >; 705 }; 706 707 pinctrl_flexcan2_reg: flexcan2reggrp { 708 fsl,pins = < 709 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ 710 >; 711 }; 712 713 pinctrl_flexspi0: flexspi0grp { 714 fsl,pins = < 715 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 716 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 717 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 718 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 719 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 720 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 721 >; 722 }; 723 724 pinctrl_gpio_led: gpioledgrp { 725 fsl,pins = < 726 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 727 >; 728 }; 729 730 pinctrl_i2c1: i2c1grp { 731 fsl,pins = < 732 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 733 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 734 >; 735 }; 736 737 pinctrl_i2c2: i2c2grp { 738 fsl,pins = < 739 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 740 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 741 >; 742 }; 743 744 pinctrl_i2c3: i2c3grp { 745 fsl,pins = < 746 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 747 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 748 >; 749 }; 750 751 pinctrl_i2c5: i2c5grp { 752 fsl,pins = < 753 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 754 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 755 >; 756 }; 757 758 pinctrl_pcie0: pcie0grp { 759 fsl,pins = < 760 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */ 761 MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40 762 >; 763 }; 764 765 pinctrl_pcie0_reg: pcie0reggrp { 766 fsl,pins = < 767 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 768 >; 769 }; 770 771 pinctrl_pmic: pmicgrp { 772 fsl,pins = < 773 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 774 >; 775 }; 776 777 pinctrl_pca6416_int: pca6416_int_grp { 778 fsl,pins = < 779 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ 780 >; 781 }; 782 783 pinctrl_pwm1: pwm1grp { 784 fsl,pins = < 785 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 786 >; 787 }; 788 789 pinctrl_pwm2: pwm2grp { 790 fsl,pins = < 791 MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 792 >; 793 }; 794 795 pinctrl_pwm4: pwm4grp { 796 fsl,pins = < 797 MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 798 >; 799 }; 800 801 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 802 fsl,pins = < 803 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 804 >; 805 }; 806 807 pinctrl_uart1: uart1grp { 808 fsl,pins = < 809 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 810 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 811 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 812 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 813 >; 814 }; 815 816 pinctrl_sai3: sai3grp { 817 fsl,pins = < 818 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 819 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 820 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 821 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 822 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 823 >; 824 }; 825 826 pinctrl_uart2: uart2grp { 827 fsl,pins = < 828 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 829 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 830 >; 831 }; 832 833 pinctrl_usb1_vbus: usb1grp { 834 fsl,pins = < 835 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 836 >; 837 }; 838 839 pinctrl_uart3: uart3grp { 840 fsl,pins = < 841 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 842 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 843 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 844 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 845 >; 846 }; 847 848 pinctrl_usdhc2: usdhc2grp { 849 fsl,pins = < 850 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 851 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 852 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 853 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 854 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 855 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 856 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 857 >; 858 }; 859 860 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 861 fsl,pins = < 862 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 863 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 864 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 865 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 866 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 867 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 868 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 869 >; 870 }; 871 872 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 873 fsl,pins = < 874 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 875 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 876 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 877 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 878 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 879 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 880 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 881 >; 882 }; 883 884 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 885 fsl,pins = < 886 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 887 >; 888 }; 889 890 pinctrl_usdhc3: usdhc3grp { 891 fsl,pins = < 892 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 893 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 894 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 895 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 896 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 897 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 898 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 899 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 900 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 901 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 902 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 903 >; 904 }; 905 906 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 907 fsl,pins = < 908 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 909 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 910 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 911 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 912 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 913 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 914 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 915 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 916 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 917 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 918 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 919 >; 920 }; 921 922 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 923 fsl,pins = < 924 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 925 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 926 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 927 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 928 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 929 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 930 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 931 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 932 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 933 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 934 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 935 >; 936 }; 937 938 pinctrl_wdog: wdoggrp { 939 fsl,pins = < 940 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 941 >; 942 }; 943}; 944