1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/usb/pd.h>
7#include "imx8mn.dtsi"
8
9/ {
10	chosen {
11		stdout-path = &uart2;
12	};
13
14	gpio-leds {
15		compatible = "gpio-leds";
16		pinctrl-names = "default";
17		pinctrl-0 = <&pinctrl_gpio_led>;
18
19		status {
20			label = "yellow:status";
21			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
22			default-state = "on";
23		};
24	};
25
26	memory@40000000 {
27		device_type = "memory";
28		reg = <0x0 0x40000000 0 0x80000000>;
29	};
30
31	reg_usdhc2_vmmc: regulator-usdhc2 {
32		compatible = "regulator-fixed";
33		pinctrl-names = "default";
34		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
35		regulator-name = "VSD_3V3";
36		regulator-min-microvolt = <3300000>;
37		regulator-max-microvolt = <3300000>;
38		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
39		enable-active-high;
40	};
41};
42
43&fec1 {
44	pinctrl-names = "default";
45	pinctrl-0 = <&pinctrl_fec1>;
46	phy-mode = "rgmii-id";
47	phy-handle = <&ethphy0>;
48	fsl,magic-packet;
49	status = "okay";
50
51	mdio {
52		#address-cells = <1>;
53		#size-cells = <0>;
54
55		ethphy0: ethernet-phy@0 {
56			compatible = "ethernet-phy-ieee802.3-c22";
57			reg = <0>;
58		};
59	};
60};
61
62&i2c1 {
63	clock-frequency = <400000>;
64	pinctrl-names = "default";
65	pinctrl-0 = <&pinctrl_i2c1>;
66	status = "okay";
67};
68
69&i2c2 {
70	clock-frequency = <400000>;
71	pinctrl-names = "default";
72	pinctrl-0 = <&pinctrl_i2c2>;
73	status = "okay";
74
75	ptn5110: tcpc@50 {
76		compatible = "nxp,ptn5110";
77		pinctrl-names = "default";
78		pinctrl-0 = <&pinctrl_typec1>;
79		reg = <0x50>;
80		interrupt-parent = <&gpio2>;
81		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
82		status = "okay";
83
84		port {
85			typec1_dr_sw: endpoint {
86				remote-endpoint = <&usb1_drd_sw>;
87			};
88		};
89
90		typec1_con: connector {
91			compatible = "usb-c-connector";
92			label = "USB-C";
93			power-role = "dual";
94			data-role = "dual";
95			try-power-role = "sink";
96			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
97			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
98				     PDO_VAR(5000, 20000, 3000)>;
99			op-sink-microwatt = <15000000>;
100			self-powered;
101		};
102	};
103};
104
105&i2c3 {
106	clock-frequency = <400000>;
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_i2c3>;
109	status = "okay";
110
111	pca6416: gpio@20 {
112		compatible = "ti,tca6416";
113		reg = <0x20>;
114		gpio-controller;
115		#gpio-cells = <2>;
116	};
117};
118
119&snvs_pwrkey {
120	status = "okay";
121};
122
123&uart2 { /* console */
124	pinctrl-names = "default";
125	pinctrl-0 = <&pinctrl_uart2>;
126	status = "okay";
127};
128
129&usbotg1 {
130	dr_mode = "otg";
131	hnp-disable;
132	srp-disable;
133	adp-disable;
134	usb-role-switch;
135	samsung,picophy-pre-emp-curr-control = <3>;
136	samsung,picophy-dc-vol-level-adjust = <7>;
137	status = "okay";
138
139	port {
140		usb1_drd_sw: endpoint {
141			remote-endpoint = <&typec1_dr_sw>;
142		};
143	};
144};
145
146&usdhc2 {
147	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
148	assigned-clock-rates = <200000000>;
149	pinctrl-names = "default", "state_100mhz", "state_200mhz";
150	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
151	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
152	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
153	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
154	bus-width = <4>;
155	vmmc-supply = <&reg_usdhc2_vmmc>;
156	status = "okay";
157};
158
159&usdhc3 {
160	assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
161	assigned-clock-rates = <400000000>;
162	pinctrl-names = "default", "state_100mhz", "state_200mhz";
163	pinctrl-0 = <&pinctrl_usdhc3>;
164	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
165	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
166	bus-width = <8>;
167	non-removable;
168	status = "okay";
169};
170
171&wdog1 {
172	pinctrl-names = "default";
173	pinctrl-0 = <&pinctrl_wdog>;
174	fsl,ext-reset-output;
175	status = "okay";
176};
177
178&iomuxc {
179	pinctrl_fec1: fec1grp {
180		fsl,pins = <
181			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3
182			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
183			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
184			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
185			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
186			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
187			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
188			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
189			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
190			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
191			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
192			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
193			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
194			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
195			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
196		>;
197	};
198
199	pinctrl_gpio_led: gpioledgrp {
200		fsl,pins = <
201			MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
202		>;
203	};
204
205	pinctrl_i2c1: i2c1grp {
206		fsl,pins = <
207			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
208			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
209		>;
210	};
211
212	pinctrl_i2c2: i2c2grp {
213		fsl,pins = <
214			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
215			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
216		>;
217	};
218
219	pinctrl_i2c3: i2c3grp {
220		fsl,pins = <
221			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
222			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
223		>;
224	};
225
226	pinctrl_pmic: pmicirqgrp {
227		fsl,pins = <
228			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
229		>;
230	};
231
232	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
233		fsl,pins = <
234			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
235		>;
236	};
237
238	pinctrl_typec1: typec1grp {
239		fsl,pins = <
240			MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
241		>;
242	};
243
244	pinctrl_uart2: uart2grp {
245		fsl,pins = <
246			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
247			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
248		>;
249	};
250
251	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
252		fsl,pins = <
253			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
254		>;
255	};
256
257	pinctrl_usdhc2: usdhc2grp {
258		fsl,pins = <
259			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
260			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
261			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
262			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
263			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
264			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
265			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
266		>;
267	};
268
269	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
270		fsl,pins = <
271			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
272			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
273			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
274			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
275			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
276			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
277			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
278		>;
279	};
280
281	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
282		fsl,pins = <
283			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
284			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
285			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
286			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
287			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
288			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
289			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
290		>;
291	};
292
293	pinctrl_usdhc3: usdhc3grp {
294		fsl,pins = <
295			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000190
296			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
297			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
298			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
299			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
300			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
301			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
302			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
303			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
304			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
305			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
306		>;
307	};
308
309	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
310		fsl,pins = <
311			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194
312			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
313			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
314			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
315			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
316			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
317			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
318			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
319			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
320			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
321			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
322		>;
323	};
324
325	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
326		fsl,pins = <
327			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196
328			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
329			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
330			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
331			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
332			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
333			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
334			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
335			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
336			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
337			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
338		>;
339	};
340
341	pinctrl_wdog: wdoggrp {
342		fsl,pins = <
343			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
344		>;
345	};
346};
347