1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/usb/pd.h>
7#include "imx8mn.dtsi"
8
9/ {
10	chosen {
11		stdout-path = &uart2;
12	};
13
14	gpio-leds {
15		compatible = "gpio-leds";
16		pinctrl-names = "default";
17		pinctrl-0 = <&pinctrl_gpio_led>;
18
19		status {
20			label = "yellow:status";
21			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
22			default-state = "on";
23		};
24	};
25
26	memory@40000000 {
27		device_type = "memory";
28		reg = <0x0 0x40000000 0 0x80000000>;
29	};
30
31	reg_usdhc2_vmmc: regulator-usdhc2 {
32		compatible = "regulator-fixed";
33		pinctrl-names = "default";
34		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
35		regulator-name = "VSD_3V3";
36		regulator-min-microvolt = <3300000>;
37		regulator-max-microvolt = <3300000>;
38		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
39		enable-active-high;
40	};
41
42	ir-receiver {
43		compatible = "gpio-ir-receiver";
44		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
45		pinctrl-names = "default";
46		pinctrl-0 = <&pinctrl_ir>;
47		linux,autosuspend-period = <125>;
48	};
49
50	wm8524: audio-codec {
51		#sound-dai-cells = <0>;
52		compatible = "wlf,wm8524";
53		pinctrl-names = "default";
54		pinctrl-0 = <&pinctrl_gpio_wlf>;
55		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
56		clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
57		clock-names = "mclk";
58	};
59
60	sound-wm8524 {
61		compatible = "fsl,imx-audio-wm8524";
62		model = "wm8524-audio";
63		audio-cpu = <&sai3>;
64		audio-codec = <&wm8524>;
65		audio-asrc = <&easrc>;
66		audio-routing =
67			"Line Out Jack", "LINEVOUTL",
68			"Line Out Jack", "LINEVOUTR";
69	};
70
71	sound-spdif {
72		compatible = "fsl,imx-audio-spdif";
73		model = "imx-spdif";
74		spdif-controller = <&spdif1>;
75		spdif-out;
76		spdif-in;
77	};
78};
79
80&easrc {
81	fsl,asrc-rate  = <48000>;
82	status = "okay";
83};
84
85&fec1 {
86	pinctrl-names = "default";
87	pinctrl-0 = <&pinctrl_fec1>;
88	phy-mode = "rgmii-id";
89	phy-handle = <&ethphy0>;
90	fsl,magic-packet;
91	status = "okay";
92
93	mdio {
94		#address-cells = <1>;
95		#size-cells = <0>;
96
97		ethphy0: ethernet-phy@0 {
98			compatible = "ethernet-phy-ieee802.3-c22";
99			reg = <0>;
100			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
101			reset-assert-us = <10000>;
102			qca,disable-smarteee;
103			vddio-supply = <&vddio>;
104
105			vddio: vddio-regulator {
106				regulator-min-microvolt = <1800000>;
107				regulator-max-microvolt = <1800000>;
108			};
109		};
110	};
111};
112
113&i2c1 {
114	clock-frequency = <400000>;
115	pinctrl-names = "default";
116	pinctrl-0 = <&pinctrl_i2c1>;
117	status = "okay";
118};
119
120&i2c2 {
121	clock-frequency = <400000>;
122	pinctrl-names = "default";
123	pinctrl-0 = <&pinctrl_i2c2>;
124	status = "okay";
125
126	ptn5110: tcpc@50 {
127		compatible = "nxp,ptn5110";
128		pinctrl-names = "default";
129		pinctrl-0 = <&pinctrl_typec1>;
130		reg = <0x50>;
131		interrupt-parent = <&gpio2>;
132		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
133		status = "okay";
134
135		port {
136			typec1_dr_sw: endpoint {
137				remote-endpoint = <&usb1_drd_sw>;
138			};
139		};
140
141		typec1_con: connector {
142			compatible = "usb-c-connector";
143			label = "USB-C";
144			power-role = "dual";
145			data-role = "dual";
146			try-power-role = "sink";
147			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
148			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
149				     PDO_VAR(5000, 20000, 3000)>;
150			op-sink-microwatt = <15000000>;
151			self-powered;
152		};
153	};
154};
155
156&i2c3 {
157	clock-frequency = <400000>;
158	pinctrl-names = "default";
159	pinctrl-0 = <&pinctrl_i2c3>;
160	status = "okay";
161
162	pca6416: gpio@20 {
163		compatible = "ti,tca6416";
164		reg = <0x20>;
165		gpio-controller;
166		#gpio-cells = <2>;
167	};
168};
169
170&sai3 {
171	pinctrl-names = "default";
172	pinctrl-0 = <&pinctrl_sai3>;
173	assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
174	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
175	assigned-clock-rates = <24576000>;
176	fsl,sai-mclk-direction-output;
177	status = "okay";
178};
179
180&snvs_pwrkey {
181	status = "okay";
182};
183
184&spdif1 {
185	pinctrl-names = "default";
186	pinctrl-0 = <&pinctrl_spdif1>;
187	assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
188	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
189	assigned-clock-rates = <24576000>;
190	status = "okay";
191};
192
193&uart2 { /* console */
194	pinctrl-names = "default";
195	pinctrl-0 = <&pinctrl_uart2>;
196	status = "okay";
197};
198
199&usbotg1 {
200	dr_mode = "otg";
201	hnp-disable;
202	srp-disable;
203	adp-disable;
204	usb-role-switch;
205	disable-over-current;
206	samsung,picophy-pre-emp-curr-control = <3>;
207	samsung,picophy-dc-vol-level-adjust = <7>;
208	status = "okay";
209
210	port {
211		usb1_drd_sw: endpoint {
212			remote-endpoint = <&typec1_dr_sw>;
213		};
214	};
215};
216
217&usdhc2 {
218	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
219	assigned-clock-rates = <200000000>;
220	pinctrl-names = "default", "state_100mhz", "state_200mhz";
221	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
222	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
223	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
224	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
225	bus-width = <4>;
226	vmmc-supply = <&reg_usdhc2_vmmc>;
227	status = "okay";
228};
229
230&usdhc3 {
231	assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
232	assigned-clock-rates = <400000000>;
233	pinctrl-names = "default", "state_100mhz", "state_200mhz";
234	pinctrl-0 = <&pinctrl_usdhc3>;
235	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
236	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
237	bus-width = <8>;
238	non-removable;
239	status = "okay";
240};
241
242&wdog1 {
243	pinctrl-names = "default";
244	pinctrl-0 = <&pinctrl_wdog>;
245	fsl,ext-reset-output;
246	status = "okay";
247};
248
249&iomuxc {
250	pinctrl_fec1: fec1grp {
251		fsl,pins = <
252			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3
253			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
254			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
255			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
256			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
257			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
258			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
259			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
260			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
261			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
262			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
263			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
264			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
265			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
266			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
267		>;
268	};
269
270	pinctrl_gpio_led: gpioledgrp {
271		fsl,pins = <
272			MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
273		>;
274	};
275
276	pinctrl_gpio_wlf: gpiowlfgrp {
277		fsl,pins = <
278			MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
279		>;
280	};
281
282	pinctrl_ir: irgrp {
283		fsl,pins = <
284			MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
285		>;
286	};
287
288	pinctrl_i2c1: i2c1grp {
289		fsl,pins = <
290			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
291			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
292		>;
293	};
294
295	pinctrl_i2c2: i2c2grp {
296		fsl,pins = <
297			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
298			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
299		>;
300	};
301
302	pinctrl_i2c3: i2c3grp {
303		fsl,pins = <
304			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
305			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
306		>;
307	};
308
309	pinctrl_pmic: pmicirqgrp {
310		fsl,pins = <
311			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
312		>;
313	};
314
315	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
316		fsl,pins = <
317			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
318		>;
319	};
320
321	pinctrl_sai3: sai3grp {
322		fsl,pins = <
323			MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
324			MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
325			MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
326			MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
327		>;
328	};
329
330	pinctrl_spdif1: spdif1grp {
331		fsl,pins = <
332			MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
333			MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
334		>;
335	};
336
337	pinctrl_typec1: typec1grp {
338		fsl,pins = <
339			MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
340		>;
341	};
342
343	pinctrl_uart2: uart2grp {
344		fsl,pins = <
345			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
346			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
347		>;
348	};
349
350	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
351		fsl,pins = <
352			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
353		>;
354	};
355
356	pinctrl_usdhc2: usdhc2grp {
357		fsl,pins = <
358			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
359			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
360			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
361			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
362			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
363			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
364			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
365		>;
366	};
367
368	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
369		fsl,pins = <
370			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
371			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
372			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
373			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
374			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
375			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
376			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
377		>;
378	};
379
380	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
381		fsl,pins = <
382			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
383			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
384			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
385			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
386			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
387			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
388			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
389		>;
390	};
391
392	pinctrl_usdhc3: usdhc3grp {
393		fsl,pins = <
394			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000190
395			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
396			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
397			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
398			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
399			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
400			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
401			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
402			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
403			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
404			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
405		>;
406	};
407
408	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
409		fsl,pins = <
410			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194
411			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
412			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
413			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
414			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
415			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
416			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
417			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
418			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
419			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
420			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
421		>;
422	};
423
424	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
425		fsl,pins = <
426			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196
427			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
428			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
429			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
430			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
431			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
432			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
433			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
434			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
435			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
436			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
437		>;
438	};
439
440	pinctrl_wdog: wdoggrp {
441		fsl,pins = <
442			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166
443		>;
444	};
445};
446