1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2021 Collabora Ltd.
4 * Copyright 2021 BSH Hausgeraete GmbH
5 */
6
7/dts-v1/;
8
9#include "imx8mn.dtsi"
10
11/ {
12	chosen {
13		stdout-path = &uart4;
14	};
15
16	fec_supply: fec-supply-en {
17		compatible = "regulator-fixed";
18		vin-supply = <&buck4_reg>;
19		regulator-name = "tja1101_en";
20		regulator-min-microvolt = <3300000>;
21		regulator-max-microvolt = <3300000>;
22		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
23		enable-active-high;
24	};
25
26	usdhc2_pwrseq: usdhc2-pwrseq {
27		compatible = "mmc-pwrseq-simple";
28		pinctrl-names = "default";
29		pinctrl-0 = <&pinctrl_usdhc2_pwrseq>;
30		reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
31	};
32};
33
34&A53_0 {
35	cpu-supply = <&buck2_reg>;
36};
37
38&A53_1 {
39	cpu-supply = <&buck2_reg>;
40};
41
42&A53_2 {
43	cpu-supply = <&buck2_reg>;
44};
45
46&A53_3 {
47	cpu-supply = <&buck2_reg>;
48};
49
50&ecspi2 {
51	pinctrl-names = "default";
52	pinctrl-0 = <&pinctrl_espi2>;
53	status = "okay";
54};
55
56&fec1 {
57	pinctrl-names = "default";
58	pinctrl-0 = <&pinctrl_fec1>;
59	phy-mode = "rmii";
60	phy-handle = <&ethphy0>;
61	phy-supply = <&fec_supply>;
62	fsl,magic-packet;
63	status = "okay";
64
65	mdio {
66		#address-cells = <1>;
67		#size-cells = <0>;
68
69		ethphy0: ethernet-phy@0 {
70			compatible = "ethernet-phy-ieee802.3-c22";
71			reg = <0>;
72			reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
73			reset-assert-us = <20>;
74			reset-deassert-us = <2000>;
75		};
76	};
77};
78
79&i2c1 {
80	clock-frequency = <400000>;
81	pinctrl-names = "default";
82	pinctrl-0 = <&pinctrl_i2c1>;
83	status = "okay";
84
85	bd71847: pmic@4b {
86		compatible = "rohm,bd71847";
87		reg = <0x4b>;
88		pinctrl-names = "default";
89		pinctrl-0 = <&pinctrl_pmic>;
90		interrupt-parent = <&gpio1>;
91		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
92		rohm,reset-snvs-powered;
93
94		#clock-cells = <0>;
95		clocks = <&osc_32k 0>;
96		clock-output-names = "clk-32k-out";
97
98		regulators {
99			buck1_reg: BUCK1 {
100				/* PMIC_BUCK1 - VDD_SOC */
101				regulator-name = "buck1";
102				regulator-min-microvolt = <700000>;
103				regulator-max-microvolt = <1300000>;
104				regulator-boot-on;
105				regulator-always-on;
106				regulator-ramp-delay = <1250>;
107			};
108
109			buck2_reg: BUCK2 {
110				/* PMIC_BUCK2 - VDD_ARM */
111				regulator-name = "buck2";
112				regulator-min-microvolt = <700000>;
113				regulator-max-microvolt = <1300000>;
114				regulator-boot-on;
115				regulator-always-on;
116				regulator-ramp-delay = <1250>;
117			};
118
119			buck3_reg: BUCK3 {
120				/* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */
121				regulator-name = "buck3";
122				regulator-min-microvolt = <700000>;
123				regulator-max-microvolt = <1350000>;
124				regulator-boot-on;
125				regulator-always-on;
126			};
127
128			buck4_reg: BUCK4 {
129				/* PMIC_BUCK6 - VDD_3V3 */
130				regulator-name = "buck4";
131				regulator-min-microvolt = <3000000>;
132				regulator-max-microvolt = <3300000>;
133				regulator-boot-on;
134				regulator-always-on;
135			};
136
137			buck5_reg: BUCK5 {
138				/* PMIC_BUCK7 - VDD_1V8 */
139				regulator-name = "buck5";
140				regulator-min-microvolt = <1605000>;
141				regulator-max-microvolt = <1995000>;
142				regulator-boot-on;
143				regulator-always-on;
144			};
145
146			buck6_reg: BUCK6 {
147				/* PMIC_BUCK8 - NVCC_DRAM */
148				regulator-name = "buck6";
149				regulator-min-microvolt = <800000>;
150				regulator-max-microvolt = <1400000>;
151				regulator-boot-on;
152				regulator-always-on;
153			};
154
155			ldo1_reg: LDO1 {
156				/* PMIC_LDO1 - NVCC_SNVS_1V8 */
157				regulator-name = "ldo1";
158				regulator-min-microvolt = <1600000>;
159				regulator-max-microvolt = <1900000>;
160				regulator-boot-on;
161				regulator-always-on;
162			};
163
164			ldo2_reg: LDO2 {
165				/* PMIC_LDO2 - VDD_SNVS_0V8 */
166				regulator-name = "ldo2";
167				regulator-min-microvolt = <800000>;
168				regulator-max-microvolt = <900000>;
169				regulator-boot-on;
170				regulator-always-on;
171			};
172
173			ldo3_reg: LDO3 {
174				/* PMIC_LDO3 - VDDA_1V8 */
175				regulator-name = "ldo3";
176				regulator-min-microvolt = <1800000>;
177				regulator-max-microvolt = <3300000>;
178				regulator-boot-on;
179				regulator-always-on;
180			};
181
182			ldo4_reg: LDO4 {
183				/* PMIC_LDO4 - VDD_MIPI_0V9 */
184				regulator-name = "ldo4";
185				regulator-min-microvolt = <900000>;
186				regulator-max-microvolt = <1800000>;
187				regulator-boot-on;
188				regulator-always-on;
189			};
190
191			ldo6_reg: LDO6 {
192				/* PMIC_LDO6 - VDD_MIPI_1V2 */
193				regulator-name = "ldo6";
194				regulator-min-microvolt = <900000>;
195				regulator-max-microvolt = <1800000>;
196				regulator-boot-on;
197				regulator-always-on;
198			};
199		};
200	};
201};
202
203&i2c3 {
204	clock-frequency = <400000>;
205	pinctrl-names = "default";
206	pinctrl-0 = <&pinctrl_i2c3>;
207	status = "okay";
208};
209
210&i2c4 {
211	clock-frequency = <400000>;
212	pinctrl-names = "default";
213	pinctrl-0 = <&pinctrl_i2c4>;
214	status = "okay";
215};
216
217&uart2 {
218	pinctrl-names = "default";
219	pinctrl-0 = <&pinctrl_uart2>;
220	status = "okay";
221};
222
223&uart3 {
224	pinctrl-names = "default";
225	pinctrl-0 = <&pinctrl_uart3>;
226	assigned-clocks = <&clk IMX8MN_CLK_UART3>;
227	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
228	uart-has-rtscts;
229	status = "okay";
230
231	bluetooth {
232		compatible = "brcm,bcm43438-bt";
233		pinctrl-names = "default";
234		pinctrl-0 = <&pinctrl_bluetooth>;
235		shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
236		device-wakeup-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
237		host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
238		max-speed = <3000000>;
239	};
240};
241
242/* Console */
243&uart4 {
244	pinctrl-names = "default";
245	pinctrl-0 = <&pinctrl_uart4>;
246	status = "okay";
247};
248
249&usbotg1 {
250	dr_mode = "peripheral";
251	disable-over-current;
252	status = "okay";
253};
254
255&usdhc2 {
256	#address-cells = <1>;
257	#size-cells = <0>;
258	pinctrl-names = "default", "state_100mhz", "state_200mhz";
259	pinctrl-0 = <&pinctrl_usdhc2>;
260	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
261	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
262	mmc-pwrseq = <&usdhc2_pwrseq>;
263	bus-width = <4>;
264	non-removable;
265	status = "okay";
266
267	brcmf: bcrmf@1 {
268		compatible = "brcm,bcm4329-fmac";
269		reg = <1>;
270		pinctrl-names = "default";
271		pinctrl-0 = <&pinctrl_wlan>;
272		interrupt-parent = <&gpio1>;
273		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
274		interrupt-names = "host-wake";
275	};
276};
277
278&wdog1 {
279	pinctrl-names = "default";
280	pinctrl-0 = <&pinctrl_wdog>;
281	fsl,ext-reset-output;
282	status = "okay";
283};
284
285&iomuxc {
286	pinctrl_bluetooth: bluetoothgrp {
287		fsl,pins = <
288			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x044	/* BT_REG_ON */
289			MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18		0x046	/* BT_DEV_WAKE */
290			MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28		0x090	/* BT_HOST_WAKE */
291		>;
292	};
293
294	pinctrl_espi2: espi2grp {
295		fsl,pins = <
296			MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x082
297			MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x082
298			MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x082
299			MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0		0x040
300		>;
301	};
302
303	pinctrl_fec1: fec1grp {
304		fsl,pins = <
305			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x002
306			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x002
307			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x090
308			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x090
309			MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER		0x090
310			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x016
311			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x016
312			MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK		0x016
313			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x016
314			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x090
315			MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER		0x016
316			MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12		0x150	/* RMII_INT - ENET_INT */
317			MX8MN_IOMUXC_SD2_WP_GPIO2_IO20			0x150	/* RMII_EN - ENET_EN */
318			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x016	/* RMII_WAKE - GPIO_ENET_WAKE */
319			MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29		0x016	/* RMII_RESET - GPIO_ENET_RST */
320		>;
321	};
322
323	pinctrl_i2c1: i2c1grp {
324		fsl,pins = <
325			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL			0x400000c2
326			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA			0x400000c2
327		>;
328	};
329
330	pinctrl_i2c3: i2c3grp {
331		fsl,pins = <
332			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL			0x400000c2
333			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA			0x400000c2
334		>;
335	};
336
337	pinctrl_i2c4: i2c4grp {
338		fsl,pins = <
339			MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL			0x400000c2
340			MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA			0x400000c2
341		>;
342	};
343
344	pinctrl_pmic: pmicirqgrp {
345		fsl,pins = <
346			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x040
347		>;
348	};
349
350	pinctrl_uart2: uart2grp {
351		fsl,pins = <
352			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX		0x040
353			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX		0x040
354		>;
355	};
356
357	pinctrl_uart3: uart3grp {
358		fsl,pins = <
359			MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX		0x040
360			MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX		0x040
361			MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x040
362			MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x040
363		>;
364	};
365
366	pinctrl_uart4: uart4grp {
367		fsl,pins = <
368			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX		0x040
369			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX		0x040
370		>;
371	};
372
373	pinctrl_usdhc2: usdhc2grp {
374		fsl,pins = <
375			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK			0x090
376			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD			0x0d0
377			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0d0
378			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x0d0
379			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x0d0
380			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x0d0
381		>;
382	};
383
384	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
385		fsl,pins = <
386			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK			0x094
387			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD			0x0d4
388			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0d4
389			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x0d4
390			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x0d4
391			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x0d4
392		>;
393	};
394
395	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
396		fsl,pins = <
397			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK			0x096
398			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD			0x0d6
399			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0d6
400			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x0d6
401			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x0d6
402			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x0d6
403		>;
404	};
405
406	pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp {
407		fsl,pins = <
408			MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x040	/* WL_REG_ON */
409		>;
410	};
411
412	pinctrl_wdog: wdoggrp {
413		fsl,pins = <
414			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x046
415		>;
416	};
417
418	pinctrl_wlan: wlangrp {
419		fsl,pins = <
420			MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x0d6	/* GPIO_0 - WIFI_GPIO_0 */
421			MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x0d6	/* GPIO_1 - WIFI_GPIO_1 */
422			MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4		0x0d6	/* BT_GPIO_5 - WIFI_GPIO_5 */
423			MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4			0x0d6	/* I2S_CLK - WIFI_GPIO_6 */
424		>;
425	};
426};
427