1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2020 Compass Electronics Group, LLC 4 */ 5 6/ { 7 usdhc1_pwrseq: usdhc1_pwrseq { 8 compatible = "mmc-pwrseq-simple"; 9 pinctrl-names = "default"; 10 pinctrl-0 = <&pinctrl_usdhc1_gpio>; 11 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 12 clocks = <&osc_32k>; 13 clock-names = "ext_clock"; 14 post-power-on-delay-ms = <80>; 15 }; 16 17 memory@40000000 { 18 device_type = "memory"; 19 reg = <0x0 0x40000000 0 0x80000000>; 20 }; 21}; 22 23&A53_0 { 24 cpu-supply = <&buck2_reg>; 25}; 26 27&A53_1 { 28 cpu-supply = <&buck2_reg>; 29}; 30 31&A53_2 { 32 cpu-supply = <&buck2_reg>; 33}; 34 35&A53_3 { 36 cpu-supply = <&buck2_reg>; 37}; 38 39/* DDR controller is running LPDDR at 800MHz which requires 0.95V */ 40&a53_opp_table { 41 opp-1200000000 { 42 opp-microvolt = <950000>; 43 }; 44}; 45 46&ddrc { 47 operating-points-v2 = <&ddrc_opp_table>; 48 49 ddrc_opp_table: opp-table { 50 compatible = "operating-points-v2"; 51 52 opp-25M { 53 opp-hz = /bits/ 64 <25000000>; 54 }; 55 56 opp-100M { 57 opp-hz = /bits/ 64 <100000000>; 58 }; 59 60 opp-800M { 61 opp-hz = /bits/ 64 <800000000>; 62 }; 63 }; 64}; 65 66&fec1 { 67 pinctrl-names = "default"; 68 pinctrl-0 = <&pinctrl_fec1>; 69 phy-mode = "rgmii-id"; 70 phy-handle = <ðphy0>; 71 phy-supply = <&buck6_reg>; 72 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 73 fsl,magic-packet; 74 status = "okay"; 75 76 mdio { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 80 ethphy0: ethernet-phy@0 { 81 compatible = "ethernet-phy-ieee802.3-c22"; 82 reg = <0>; 83 }; 84 }; 85}; 86 87&i2c1 { 88 clock-frequency = <400000>; 89 pinctrl-names = "default"; 90 pinctrl-0 = <&pinctrl_i2c1>; 91 status = "okay"; 92 93 pmic@4b { 94 compatible = "rohm,bd71847"; 95 reg = <0x4b>; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_pmic>; 98 interrupt-parent = <&gpio1>; 99 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 100 rohm,reset-snvs-powered; 101 102 regulators { 103 buck1_reg: BUCK1 { 104 regulator-name = "buck1"; 105 regulator-min-microvolt = <700000>; 106 regulator-max-microvolt = <1300000>; 107 regulator-boot-on; 108 regulator-always-on; 109 regulator-ramp-delay = <1250>; 110 }; 111 112 buck2_reg: BUCK2 { 113 regulator-name = "buck2"; 114 regulator-min-microvolt = <700000>; 115 regulator-max-microvolt = <1300000>; 116 regulator-boot-on; 117 regulator-always-on; 118 regulator-ramp-delay = <1250>; 119 rohm,dvs-run-voltage = <1000000>; 120 rohm,dvs-idle-voltage = <900000>; 121 }; 122 123 buck3_reg: BUCK3 { 124 // BUCK5 in datasheet 125 regulator-name = "buck3"; 126 regulator-min-microvolt = <700000>; 127 regulator-max-microvolt = <1350000>; 128 regulator-boot-on; 129 regulator-always-on; 130 }; 131 132 buck4_reg: BUCK4 { 133 // BUCK6 in datasheet 134 regulator-name = "buck4"; 135 regulator-min-microvolt = <3000000>; 136 regulator-max-microvolt = <3300000>; 137 regulator-boot-on; 138 regulator-always-on; 139 }; 140 141 buck5_reg: BUCK5 { 142 // BUCK7 in datasheet 143 regulator-name = "buck5"; 144 regulator-min-microvolt = <1605000>; 145 regulator-max-microvolt = <1995000>; 146 regulator-boot-on; 147 regulator-always-on; 148 }; 149 150 buck6_reg: BUCK6 { 151 // BUCK8 in datasheet 152 regulator-name = "buck6"; 153 regulator-min-microvolt = <800000>; 154 regulator-max-microvolt = <1400000>; 155 regulator-boot-on; 156 regulator-always-on; 157 }; 158 159 ldo1_reg: LDO1 { 160 regulator-name = "ldo1"; 161 regulator-min-microvolt = <1600000>; 162 regulator-max-microvolt = <3300000>; 163 regulator-boot-on; 164 regulator-always-on; 165 }; 166 167 ldo2_reg: LDO2 { 168 regulator-name = "ldo2"; 169 regulator-min-microvolt = <800000>; 170 regulator-max-microvolt = <900000>; 171 regulator-boot-on; 172 regulator-always-on; 173 }; 174 175 ldo3_reg: LDO3 { 176 regulator-name = "ldo3"; 177 regulator-min-microvolt = <1800000>; 178 regulator-max-microvolt = <3300000>; 179 regulator-boot-on; 180 regulator-always-on; 181 }; 182 183 ldo4_reg: LDO4 { 184 regulator-name = "ldo4"; 185 regulator-min-microvolt = <900000>; 186 regulator-max-microvolt = <1800000>; 187 regulator-boot-on; 188 regulator-always-on; 189 }; 190 191 ldo6_reg: LDO6 { 192 regulator-name = "ldo6"; 193 regulator-min-microvolt = <900000>; 194 regulator-max-microvolt = <1800000>; 195 regulator-boot-on; 196 regulator-always-on; 197 }; 198 }; 199 }; 200}; 201 202&i2c3 { 203 clock-frequency = <400000>; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_i2c3>; 206 status = "okay"; 207 208 eeprom@50 { 209 compatible = "microchip,24c64", "atmel,24c64"; 210 pagesize = <32>; 211 read-only; /* Manufacturing EEPROM programmed at factory */ 212 reg = <0x50>; 213 }; 214 215 rtc@51 { 216 compatible = "nxp,pcf85263"; 217 reg = <0x51>; 218 }; 219}; 220 221&uart1 { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pinctrl_uart1>; 224 assigned-clocks = <&clk IMX8MN_CLK_UART1>; 225 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; 226 uart-has-rtscts; 227 status = "okay"; 228 229 bluetooth { 230 compatible = "brcm,bcm43438-bt"; 231 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 232 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 233 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 234 clocks = <&osc_32k>; 235 max-speed = <4000000>; 236 clock-names = "extclk"; 237 }; 238}; 239 240&usdhc1 { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_usdhc1>; 245 bus-width = <4>; 246 non-removable; 247 cap-power-off-card; 248 pm-ignore-notify; 249 keep-power-in-suspend; 250 mmc-pwrseq = <&usdhc1_pwrseq>; 251 status = "okay"; 252 253 brcmf: bcrmf@1 { 254 reg = <1>; 255 compatible = "brcm,bcm4329-fmac"; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_wlan>; 258 interrupt-parent = <&gpio2>; 259 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 260 interrupt-names = "host-wake"; 261 }; 262}; 263 264&usdhc3 { 265 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 266 pinctrl-0 = <&pinctrl_usdhc3>; 267 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 268 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 269 bus-width = <8>; 270 non-removable; 271 status = "okay"; 272}; 273 274&wdog1 { 275 pinctrl-names = "default"; 276 pinctrl-0 = <&pinctrl_wdog>; 277 fsl,ext-reset-output; 278 status = "okay"; 279}; 280 281&iomuxc { 282 pinctrl_fec1: fec1grp { 283 fsl,pins = < 284 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 285 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 286 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 287 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 288 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 289 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 290 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 291 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 292 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 293 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 294 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 295 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 296 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 297 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 298 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 299 >; 300 }; 301 302 pinctrl_i2c1: i2c1grp { 303 fsl,pins = < 304 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 305 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 306 >; 307 }; 308 309 pinctrl_i2c3: i2c3grp { 310 fsl,pins = < 311 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 312 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 313 >; 314 }; 315 316 pinctrl_pmic: pmicirqgrp { 317 fsl,pins = < 318 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 319 >; 320 }; 321 322 pinctrl_uart1: uart1grp { 323 fsl,pins = < 324 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 325 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 326 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 327 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 328 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 329 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 330 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 331 MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 332 >; 333 }; 334 335 pinctrl_usdhc1_gpio: usdhc1gpiogrp { 336 fsl,pins = < 337 MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 338 >; 339 }; 340 341 pinctrl_usdhc1: usdhc1grp { 342 fsl,pins = < 343 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 344 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 345 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 346 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 347 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 348 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 349 >; 350 }; 351 352 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 353 fsl,pins = < 354 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 355 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 356 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 357 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 358 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 359 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 360 >; 361 }; 362 363 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 364 fsl,pins = < 365 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 366 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 367 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 368 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 369 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 370 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 371 >; 372 }; 373 374 pinctrl_usdhc3: usdhc3grp { 375 fsl,pins = < 376 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 377 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 378 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 379 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 380 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 381 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 382 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 383 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 384 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 385 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 386 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 387 >; 388 }; 389 390 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 391 fsl,pins = < 392 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 393 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 394 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 395 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 396 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 397 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 398 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 399 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 400 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 401 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 402 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 403 >; 404 }; 405 406 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 407 fsl,pins = < 408 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 409 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 410 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 411 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 412 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 413 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 414 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 415 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 416 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 417 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 418 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 419 >; 420 }; 421 422 pinctrl_wdog: wdoggrp { 423 fsl,pins = < 424 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 425 >; 426 }; 427 428 pinctrl_wlan: wlangrp { 429 fsl,pins = < 430 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 431 >; 432 }; 433}; 434