1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2020 Compass Electronics Group, LLC 4 */ 5 6/ { 7 aliases { 8 rtc0 = &rtc; 9 rtc1 = &snvs_rtc; 10 }; 11 12 usdhc1_pwrseq: usdhc1_pwrseq { 13 compatible = "mmc-pwrseq-simple"; 14 pinctrl-names = "default"; 15 pinctrl-0 = <&pinctrl_usdhc1_gpio>; 16 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 17 clocks = <&osc_32k>; 18 clock-names = "ext_clock"; 19 post-power-on-delay-ms = <80>; 20 }; 21 22 memory@40000000 { 23 device_type = "memory"; 24 reg = <0x0 0x40000000 0 0x80000000>; 25 }; 26}; 27 28&A53_0 { 29 cpu-supply = <&buck2_reg>; 30}; 31 32&A53_1 { 33 cpu-supply = <&buck2_reg>; 34}; 35 36&A53_2 { 37 cpu-supply = <&buck2_reg>; 38}; 39 40&A53_3 { 41 cpu-supply = <&buck2_reg>; 42}; 43 44/* DDR controller is running LPDDR at 800MHz which requires 0.95V */ 45&a53_opp_table { 46 opp-1200000000 { 47 opp-microvolt = <950000>; 48 }; 49}; 50 51&ddrc { 52 operating-points-v2 = <&ddrc_opp_table>; 53 54 ddrc_opp_table: opp-table { 55 compatible = "operating-points-v2"; 56 57 opp-25M { 58 opp-hz = /bits/ 64 <25000000>; 59 }; 60 61 opp-100M { 62 opp-hz = /bits/ 64 <100000000>; 63 }; 64 65 opp-800M { 66 opp-hz = /bits/ 64 <800000000>; 67 }; 68 }; 69}; 70 71&fec1 { 72 pinctrl-names = "default"; 73 pinctrl-0 = <&pinctrl_fec1>; 74 phy-mode = "rgmii-id"; 75 phy-handle = <ðphy0>; 76 phy-supply = <&buck6_reg>; 77 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 78 fsl,magic-packet; 79 status = "okay"; 80 81 mdio { 82 #address-cells = <1>; 83 #size-cells = <0>; 84 85 ethphy0: ethernet-phy@0 { 86 compatible = "ethernet-phy-ieee802.3-c22"; 87 reg = <0>; 88 }; 89 }; 90}; 91 92&i2c1 { 93 clock-frequency = <400000>; 94 pinctrl-names = "default"; 95 pinctrl-0 = <&pinctrl_i2c1>; 96 status = "okay"; 97 98 pmic@4b { 99 compatible = "rohm,bd71847"; 100 reg = <0x4b>; 101 pinctrl-names = "default"; 102 pinctrl-0 = <&pinctrl_pmic>; 103 interrupt-parent = <&gpio1>; 104 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 105 rohm,reset-snvs-powered; 106 107 regulators { 108 buck1_reg: BUCK1 { 109 regulator-name = "buck1"; 110 regulator-min-microvolt = <700000>; 111 regulator-max-microvolt = <1300000>; 112 regulator-boot-on; 113 regulator-always-on; 114 regulator-ramp-delay = <1250>; 115 }; 116 117 buck2_reg: BUCK2 { 118 regulator-name = "buck2"; 119 regulator-min-microvolt = <700000>; 120 regulator-max-microvolt = <1300000>; 121 regulator-boot-on; 122 regulator-always-on; 123 regulator-ramp-delay = <1250>; 124 rohm,dvs-run-voltage = <1000000>; 125 rohm,dvs-idle-voltage = <900000>; 126 }; 127 128 buck3_reg: BUCK3 { 129 // BUCK5 in datasheet 130 regulator-name = "buck3"; 131 regulator-min-microvolt = <700000>; 132 regulator-max-microvolt = <1350000>; 133 regulator-boot-on; 134 regulator-always-on; 135 }; 136 137 buck4_reg: BUCK4 { 138 // BUCK6 in datasheet 139 regulator-name = "buck4"; 140 regulator-min-microvolt = <3000000>; 141 regulator-max-microvolt = <3300000>; 142 regulator-boot-on; 143 regulator-always-on; 144 }; 145 146 buck5_reg: BUCK5 { 147 // BUCK7 in datasheet 148 regulator-name = "buck5"; 149 regulator-min-microvolt = <1605000>; 150 regulator-max-microvolt = <1995000>; 151 regulator-boot-on; 152 regulator-always-on; 153 }; 154 155 buck6_reg: BUCK6 { 156 // BUCK8 in datasheet 157 regulator-name = "buck6"; 158 regulator-min-microvolt = <800000>; 159 regulator-max-microvolt = <1400000>; 160 regulator-boot-on; 161 regulator-always-on; 162 }; 163 164 ldo1_reg: LDO1 { 165 regulator-name = "ldo1"; 166 regulator-min-microvolt = <1600000>; 167 regulator-max-microvolt = <3300000>; 168 regulator-boot-on; 169 regulator-always-on; 170 }; 171 172 ldo2_reg: LDO2 { 173 regulator-name = "ldo2"; 174 regulator-min-microvolt = <800000>; 175 regulator-max-microvolt = <900000>; 176 regulator-boot-on; 177 regulator-always-on; 178 }; 179 180 ldo3_reg: LDO3 { 181 regulator-name = "ldo3"; 182 regulator-min-microvolt = <1800000>; 183 regulator-max-microvolt = <3300000>; 184 regulator-boot-on; 185 regulator-always-on; 186 }; 187 188 ldo4_reg: LDO4 { 189 regulator-name = "ldo4"; 190 regulator-min-microvolt = <900000>; 191 regulator-max-microvolt = <1800000>; 192 regulator-boot-on; 193 regulator-always-on; 194 }; 195 196 ldo6_reg: LDO6 { 197 regulator-name = "ldo6"; 198 regulator-min-microvolt = <900000>; 199 regulator-max-microvolt = <1800000>; 200 regulator-boot-on; 201 regulator-always-on; 202 }; 203 }; 204 }; 205}; 206 207&i2c3 { 208 clock-frequency = <400000>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_i2c3>; 211 status = "okay"; 212 213 eeprom@50 { 214 compatible = "microchip,24c64", "atmel,24c64"; 215 pagesize = <32>; 216 read-only; /* Manufacturing EEPROM programmed at factory */ 217 reg = <0x50>; 218 }; 219 220 rtc: rtc@51 { 221 compatible = "nxp,pcf85263"; 222 reg = <0x51>; 223 }; 224}; 225 226&uart1 { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_uart1>; 229 assigned-clocks = <&clk IMX8MN_CLK_UART1>; 230 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; 231 uart-has-rtscts; 232 status = "okay"; 233 234 bluetooth { 235 compatible = "brcm,bcm43438-bt"; 236 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 237 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 238 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 239 clocks = <&osc_32k>; 240 max-speed = <4000000>; 241 clock-names = "extclk"; 242 }; 243}; 244 245&usdhc1 { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_usdhc1>; 250 bus-width = <4>; 251 non-removable; 252 cap-power-off-card; 253 pm-ignore-notify; 254 keep-power-in-suspend; 255 mmc-pwrseq = <&usdhc1_pwrseq>; 256 status = "okay"; 257 258 brcmf: bcrmf@1 { 259 reg = <1>; 260 compatible = "brcm,bcm4329-fmac"; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_wlan>; 263 interrupt-parent = <&gpio2>; 264 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-names = "host-wake"; 266 }; 267}; 268 269&usdhc3 { 270 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 271 pinctrl-0 = <&pinctrl_usdhc3>; 272 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 273 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 274 bus-width = <8>; 275 non-removable; 276 status = "okay"; 277}; 278 279&wdog1 { 280 pinctrl-names = "default"; 281 pinctrl-0 = <&pinctrl_wdog>; 282 fsl,ext-reset-output; 283 status = "okay"; 284}; 285 286&iomuxc { 287 pinctrl_fec1: fec1grp { 288 fsl,pins = < 289 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 290 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 291 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 292 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 293 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 294 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 295 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 296 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 297 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 298 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 299 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 300 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 301 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 302 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 303 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 304 >; 305 }; 306 307 pinctrl_i2c1: i2c1grp { 308 fsl,pins = < 309 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 310 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 311 >; 312 }; 313 314 pinctrl_i2c3: i2c3grp { 315 fsl,pins = < 316 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 317 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 318 >; 319 }; 320 321 pinctrl_pmic: pmicirqgrp { 322 fsl,pins = < 323 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 324 >; 325 }; 326 327 pinctrl_uart1: uart1grp { 328 fsl,pins = < 329 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 330 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 331 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 332 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 333 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 334 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 335 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 336 MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 337 >; 338 }; 339 340 pinctrl_usdhc1_gpio: usdhc1gpiogrp { 341 fsl,pins = < 342 MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 343 >; 344 }; 345 346 pinctrl_usdhc1: usdhc1grp { 347 fsl,pins = < 348 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 349 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 350 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 351 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 352 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 353 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 354 >; 355 }; 356 357 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 358 fsl,pins = < 359 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 360 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 361 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 362 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 363 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 364 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 365 >; 366 }; 367 368 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 369 fsl,pins = < 370 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 371 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 372 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 373 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 374 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 375 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 376 >; 377 }; 378 379 pinctrl_usdhc3: usdhc3grp { 380 fsl,pins = < 381 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 382 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 383 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 384 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 385 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 386 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 387 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 388 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 389 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 390 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 391 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 392 >; 393 }; 394 395 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 396 fsl,pins = < 397 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 398 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 399 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 400 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 401 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 402 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 403 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 404 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 405 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 406 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 407 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 408 >; 409 }; 410 411 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 412 fsl,pins = < 413 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 414 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 415 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 416 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 417 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 418 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 419 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 420 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 421 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 422 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 423 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 424 >; 425 }; 426 427 pinctrl_wdog: wdoggrp { 428 fsl,pins = < 429 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 430 >; 431 }; 432 433 pinctrl_wlan: wlangrp { 434 fsl,pins = < 435 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 436 >; 437 }; 438}; 439