1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mm-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/imx8mm-power.h> 11#include <dt-bindings/reset/imx8mq-reset.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx8mm-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 idle-states { 49 entry-method = "psci"; 50 51 cpu_pd_wait: cpu-pd-wait { 52 compatible = "arm,idle-state"; 53 arm,psci-suspend-param = <0x0010033>; 54 local-timer-stop; 55 entry-latency-us = <1000>; 56 exit-latency-us = <700>; 57 min-residency-us = <2700>; 58 }; 59 }; 60 61 A53_0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x0>; 65 clock-latency = <61036>; /* two CLK32 periods */ 66 clocks = <&clk IMX8MM_CLK_ARM>; 67 enable-method = "psci"; 68 i-cache-size = <0x8000>; 69 i-cache-line-size = <64>; 70 i-cache-sets = <256>; 71 d-cache-size = <0x8000>; 72 d-cache-line-size = <64>; 73 d-cache-sets = <128>; 74 next-level-cache = <&A53_L2>; 75 operating-points-v2 = <&a53_opp_table>; 76 nvmem-cells = <&cpu_speed_grade>; 77 nvmem-cell-names = "speed_grade"; 78 cpu-idle-states = <&cpu_pd_wait>; 79 #cooling-cells = <2>; 80 }; 81 82 A53_1: cpu@1 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x1>; 86 clock-latency = <61036>; /* two CLK32 periods */ 87 clocks = <&clk IMX8MM_CLK_ARM>; 88 enable-method = "psci"; 89 i-cache-size = <0x8000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <256>; 92 d-cache-size = <0x8000>; 93 d-cache-line-size = <64>; 94 d-cache-sets = <128>; 95 next-level-cache = <&A53_L2>; 96 operating-points-v2 = <&a53_opp_table>; 97 cpu-idle-states = <&cpu_pd_wait>; 98 #cooling-cells = <2>; 99 }; 100 101 A53_2: cpu@2 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x2>; 105 clock-latency = <61036>; /* two CLK32 periods */ 106 clocks = <&clk IMX8MM_CLK_ARM>; 107 enable-method = "psci"; 108 i-cache-size = <0x8000>; 109 i-cache-line-size = <64>; 110 i-cache-sets = <256>; 111 d-cache-size = <0x8000>; 112 d-cache-line-size = <64>; 113 d-cache-sets = <128>; 114 next-level-cache = <&A53_L2>; 115 operating-points-v2 = <&a53_opp_table>; 116 cpu-idle-states = <&cpu_pd_wait>; 117 #cooling-cells = <2>; 118 }; 119 120 A53_3: cpu@3 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53"; 123 reg = <0x3>; 124 clock-latency = <61036>; /* two CLK32 periods */ 125 clocks = <&clk IMX8MM_CLK_ARM>; 126 enable-method = "psci"; 127 i-cache-size = <0x8000>; 128 i-cache-line-size = <64>; 129 i-cache-sets = <256>; 130 d-cache-size = <0x8000>; 131 d-cache-line-size = <64>; 132 d-cache-sets = <128>; 133 next-level-cache = <&A53_L2>; 134 operating-points-v2 = <&a53_opp_table>; 135 cpu-idle-states = <&cpu_pd_wait>; 136 #cooling-cells = <2>; 137 }; 138 139 A53_L2: l2-cache0 { 140 compatible = "cache"; 141 cache-level = <2>; 142 cache-size = <0x80000>; 143 cache-line-size = <64>; 144 cache-sets = <512>; 145 }; 146 }; 147 148 a53_opp_table: opp-table { 149 compatible = "operating-points-v2"; 150 opp-shared; 151 152 opp-1200000000 { 153 opp-hz = /bits/ 64 <1200000000>; 154 opp-microvolt = <850000>; 155 opp-supported-hw = <0xe>, <0x7>; 156 clock-latency-ns = <150000>; 157 opp-suspend; 158 }; 159 160 opp-1600000000 { 161 opp-hz = /bits/ 64 <1600000000>; 162 opp-microvolt = <950000>; 163 opp-supported-hw = <0xc>, <0x7>; 164 clock-latency-ns = <150000>; 165 opp-suspend; 166 }; 167 168 opp-1800000000 { 169 opp-hz = /bits/ 64 <1800000000>; 170 opp-microvolt = <1000000>; 171 opp-supported-hw = <0x8>, <0x3>; 172 clock-latency-ns = <150000>; 173 opp-suspend; 174 }; 175 }; 176 177 osc_32k: clock-osc-32k { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <32768>; 181 clock-output-names = "osc_32k"; 182 }; 183 184 osc_24m: clock-osc-24m { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <24000000>; 188 clock-output-names = "osc_24m"; 189 }; 190 191 clk_ext1: clock-ext1 { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <133000000>; 195 clock-output-names = "clk_ext1"; 196 }; 197 198 clk_ext2: clock-ext2 { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <133000000>; 202 clock-output-names = "clk_ext2"; 203 }; 204 205 clk_ext3: clock-ext3 { 206 compatible = "fixed-clock"; 207 #clock-cells = <0>; 208 clock-frequency = <133000000>; 209 clock-output-names = "clk_ext3"; 210 }; 211 212 clk_ext4: clock-ext4 { 213 compatible = "fixed-clock"; 214 #clock-cells = <0>; 215 clock-frequency= <133000000>; 216 clock-output-names = "clk_ext4"; 217 }; 218 219 psci { 220 compatible = "arm,psci-1.0"; 221 method = "smc"; 222 }; 223 224 pmu { 225 compatible = "arm,cortex-a53-pmu"; 226 interrupts = <GIC_PPI 7 227 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 228 }; 229 230 timer { 231 compatible = "arm,armv8-timer"; 232 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 233 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 234 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 235 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 236 clock-frequency = <8000000>; 237 arm,no-tick-in-suspend; 238 }; 239 240 thermal-zones { 241 cpu-thermal { 242 polling-delay-passive = <250>; 243 polling-delay = <2000>; 244 thermal-sensors = <&tmu>; 245 trips { 246 cpu_alert0: trip0 { 247 temperature = <85000>; 248 hysteresis = <2000>; 249 type = "passive"; 250 }; 251 252 cpu_crit0: trip1 { 253 temperature = <95000>; 254 hysteresis = <2000>; 255 type = "critical"; 256 }; 257 }; 258 259 cooling-maps { 260 map0 { 261 trip = <&cpu_alert0>; 262 cooling-device = 263 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 264 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 265 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 266 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 267 }; 268 }; 269 }; 270 }; 271 272 usbphynop1: usbphynop1 { 273 #phy-cells = <0>; 274 compatible = "usb-nop-xceiv"; 275 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 276 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 277 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 278 clock-names = "main_clk"; 279 }; 280 281 usbphynop2: usbphynop2 { 282 #phy-cells = <0>; 283 compatible = "usb-nop-xceiv"; 284 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 285 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 286 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 287 clock-names = "main_clk"; 288 }; 289 290 soc@0 { 291 compatible = "fsl,imx8mm-soc", "simple-bus"; 292 #address-cells = <1>; 293 #size-cells = <1>; 294 ranges = <0x0 0x0 0x0 0x3e000000>; 295 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 296 nvmem-cells = <&imx8mm_uid>; 297 nvmem-cell-names = "soc_unique_id"; 298 299 aips1: bus@30000000 { 300 compatible = "fsl,aips-bus", "simple-bus"; 301 reg = <0x30000000 0x400000>; 302 #address-cells = <1>; 303 #size-cells = <1>; 304 ranges = <0x30000000 0x30000000 0x400000>; 305 306 spba2: spba-bus@30000000 { 307 compatible = "fsl,spba-bus", "simple-bus"; 308 #address-cells = <1>; 309 #size-cells = <1>; 310 reg = <0x30000000 0x100000>; 311 ranges; 312 313 sai1: sai@30010000 { 314 #sound-dai-cells = <0>; 315 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 316 reg = <0x30010000 0x10000>; 317 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 319 <&clk IMX8MM_CLK_SAI1_ROOT>, 320 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 321 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 322 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 323 dma-names = "rx", "tx"; 324 status = "disabled"; 325 }; 326 327 sai2: sai@30020000 { 328 #sound-dai-cells = <0>; 329 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 330 reg = <0x30020000 0x10000>; 331 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clk IMX8MM_CLK_SAI2_IPG>, 333 <&clk IMX8MM_CLK_SAI2_ROOT>, 334 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 335 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 336 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 337 dma-names = "rx", "tx"; 338 status = "disabled"; 339 }; 340 341 sai3: sai@30030000 { 342 #sound-dai-cells = <0>; 343 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 344 reg = <0x30030000 0x10000>; 345 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, 347 <&clk IMX8MM_CLK_SAI3_ROOT>, 348 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 349 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 350 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 351 dma-names = "rx", "tx"; 352 status = "disabled"; 353 }; 354 355 sai5: sai@30050000 { 356 #sound-dai-cells = <0>; 357 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 358 reg = <0x30050000 0x10000>; 359 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&clk IMX8MM_CLK_SAI5_IPG>, 361 <&clk IMX8MM_CLK_SAI5_ROOT>, 362 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 363 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 364 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 365 dma-names = "rx", "tx"; 366 status = "disabled"; 367 }; 368 369 sai6: sai@30060000 { 370 #sound-dai-cells = <0>; 371 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 372 reg = <0x30060000 0x10000>; 373 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&clk IMX8MM_CLK_SAI6_IPG>, 375 <&clk IMX8MM_CLK_SAI6_ROOT>, 376 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 377 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 378 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 379 dma-names = "rx", "tx"; 380 status = "disabled"; 381 }; 382 383 micfil: audio-controller@30080000 { 384 compatible = "fsl,imx8mm-micfil"; 385 reg = <0x30080000 0x10000>; 386 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&clk IMX8MM_CLK_PDM_IPG>, 391 <&clk IMX8MM_CLK_PDM_ROOT>, 392 <&clk IMX8MM_AUDIO_PLL1_OUT>, 393 <&clk IMX8MM_AUDIO_PLL2_OUT>, 394 <&clk IMX8MM_CLK_EXT3>; 395 clock-names = "ipg_clk", "ipg_clk_app", 396 "pll8k", "pll11k", "clkext3"; 397 dmas = <&sdma2 24 25 0x80000000>; 398 dma-names = "rx"; 399 status = "disabled"; 400 }; 401 402 spdif1: spdif@30090000 { 403 compatible = "fsl,imx35-spdif"; 404 reg = <0x30090000 0x10000>; 405 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ 407 <&clk IMX8MM_CLK_24M>, /* rxtx0 */ 408 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ 409 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ 410 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ 411 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ 412 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ 413 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ 414 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ 415 <&clk IMX8MM_CLK_DUMMY>; /* spba */ 416 clock-names = "core", "rxtx0", 417 "rxtx1", "rxtx2", 418 "rxtx3", "rxtx4", 419 "rxtx5", "rxtx6", 420 "rxtx7", "spba"; 421 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 422 dma-names = "rx", "tx"; 423 status = "disabled"; 424 }; 425 }; 426 427 gpio1: gpio@30200000 { 428 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 429 reg = <0x30200000 0x10000>; 430 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; 433 gpio-controller; 434 #gpio-cells = <2>; 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 gpio-ranges = <&iomuxc 0 10 30>; 438 }; 439 440 gpio2: gpio@30210000 { 441 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 442 reg = <0x30210000 0x10000>; 443 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; 446 gpio-controller; 447 #gpio-cells = <2>; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 gpio-ranges = <&iomuxc 0 40 21>; 451 }; 452 453 gpio3: gpio@30220000 { 454 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 455 reg = <0x30220000 0x10000>; 456 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; 459 gpio-controller; 460 #gpio-cells = <2>; 461 interrupt-controller; 462 #interrupt-cells = <2>; 463 gpio-ranges = <&iomuxc 0 61 26>; 464 }; 465 466 gpio4: gpio@30230000 { 467 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 468 reg = <0x30230000 0x10000>; 469 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; 472 gpio-controller; 473 #gpio-cells = <2>; 474 interrupt-controller; 475 #interrupt-cells = <2>; 476 gpio-ranges = <&iomuxc 0 87 32>; 477 }; 478 479 gpio5: gpio@30240000 { 480 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 481 reg = <0x30240000 0x10000>; 482 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; 485 gpio-controller; 486 #gpio-cells = <2>; 487 interrupt-controller; 488 #interrupt-cells = <2>; 489 gpio-ranges = <&iomuxc 0 119 30>; 490 }; 491 492 tmu: tmu@30260000 { 493 compatible = "fsl,imx8mm-tmu"; 494 reg = <0x30260000 0x10000>; 495 clocks = <&clk IMX8MM_CLK_TMU_ROOT>; 496 #thermal-sensor-cells = <0>; 497 }; 498 499 wdog1: watchdog@30280000 { 500 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 501 reg = <0x30280000 0x10000>; 502 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; 504 status = "disabled"; 505 }; 506 507 wdog2: watchdog@30290000 { 508 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 509 reg = <0x30290000 0x10000>; 510 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; 512 status = "disabled"; 513 }; 514 515 wdog3: watchdog@302a0000 { 516 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 517 reg = <0x302a0000 0x10000>; 518 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; 520 status = "disabled"; 521 }; 522 523 sdma2: dma-controller@302c0000 { 524 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 525 reg = <0x302c0000 0x10000>; 526 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, 528 <&clk IMX8MM_CLK_SDMA2_ROOT>; 529 clock-names = "ipg", "ahb"; 530 #dma-cells = <3>; 531 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 532 }; 533 534 sdma3: dma-controller@302b0000 { 535 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 536 reg = <0x302b0000 0x10000>; 537 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, 539 <&clk IMX8MM_CLK_SDMA3_ROOT>; 540 clock-names = "ipg", "ahb"; 541 #dma-cells = <3>; 542 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 543 }; 544 545 iomuxc: pinctrl@30330000 { 546 compatible = "fsl,imx8mm-iomuxc"; 547 reg = <0x30330000 0x10000>; 548 }; 549 550 gpr: iomuxc-gpr@30340000 { 551 compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; 552 reg = <0x30340000 0x10000>; 553 }; 554 555 ocotp: efuse@30350000 { 556 compatible = "fsl,imx8mm-ocotp", "syscon"; 557 reg = <0x30350000 0x10000>; 558 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; 559 /* For nvmem subnodes */ 560 #address-cells = <1>; 561 #size-cells = <1>; 562 563 imx8mm_uid: unique-id@410 { 564 reg = <0x4 0x8>; 565 }; 566 567 cpu_speed_grade: speed-grade@10 { 568 reg = <0x10 4>; 569 }; 570 571 fec_mac_address: mac-address@90 { 572 reg = <0x90 6>; 573 }; 574 }; 575 576 anatop: anatop@30360000 { 577 compatible = "fsl,imx8mm-anatop", "syscon"; 578 reg = <0x30360000 0x10000>; 579 }; 580 581 snvs: snvs@30370000 { 582 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 583 reg = <0x30370000 0x10000>; 584 585 snvs_rtc: snvs-rtc-lp { 586 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 587 regmap = <&snvs>; 588 offset = <0x34>; 589 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 592 clock-names = "snvs-rtc"; 593 }; 594 595 snvs_pwrkey: snvs-powerkey { 596 compatible = "fsl,sec-v4.0-pwrkey"; 597 regmap = <&snvs>; 598 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 600 clock-names = "snvs-pwrkey"; 601 linux,keycode = <KEY_POWER>; 602 wakeup-source; 603 status = "disabled"; 604 }; 605 }; 606 607 clk: clock-controller@30380000 { 608 compatible = "fsl,imx8mm-ccm"; 609 reg = <0x30380000 0x10000>; 610 #clock-cells = <1>; 611 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 612 <&clk_ext3>, <&clk_ext4>; 613 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 614 "clk_ext3", "clk_ext4"; 615 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, 616 <&clk IMX8MM_CLK_A53_CORE>, 617 <&clk IMX8MM_CLK_NOC>, 618 <&clk IMX8MM_CLK_AUDIO_AHB>, 619 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, 620 <&clk IMX8MM_SYS_PLL3>, 621 <&clk IMX8MM_VIDEO_PLL1>, 622 <&clk IMX8MM_AUDIO_PLL1>; 623 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 624 <&clk IMX8MM_ARM_PLL_OUT>, 625 <&clk IMX8MM_SYS_PLL3_OUT>, 626 <&clk IMX8MM_SYS_PLL1_800M>; 627 assigned-clock-rates = <0>, <0>, <0>, 628 <400000000>, 629 <400000000>, 630 <750000000>, 631 <594000000>, 632 <393216000>; 633 }; 634 635 src: reset-controller@30390000 { 636 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; 637 reg = <0x30390000 0x10000>; 638 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 639 #reset-cells = <1>; 640 }; 641 642 gpc: gpc@303a0000 { 643 compatible = "fsl,imx8mm-gpc"; 644 reg = <0x303a0000 0x10000>; 645 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 646 interrupt-parent = <&gic>; 647 interrupt-controller; 648 #interrupt-cells = <3>; 649 650 pgc { 651 #address-cells = <1>; 652 #size-cells = <0>; 653 654 pgc_hsiomix: power-domain@0 { 655 #power-domain-cells = <0>; 656 reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>; 657 clocks = <&clk IMX8MM_CLK_USB_BUS>; 658 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 659 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 660 }; 661 662 pgc_pcie: power-domain@1 { 663 #power-domain-cells = <0>; 664 reg = <IMX8MM_POWER_DOMAIN_PCIE>; 665 power-domains = <&pgc_hsiomix>; 666 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>; 667 }; 668 669 pgc_otg1: power-domain@2 { 670 #power-domain-cells = <0>; 671 reg = <IMX8MM_POWER_DOMAIN_OTG1>; 672 power-domains = <&pgc_hsiomix>; 673 }; 674 675 pgc_otg2: power-domain@3 { 676 #power-domain-cells = <0>; 677 reg = <IMX8MM_POWER_DOMAIN_OTG2>; 678 power-domains = <&pgc_hsiomix>; 679 }; 680 681 pgc_gpumix: power-domain@4 { 682 #power-domain-cells = <0>; 683 reg = <IMX8MM_POWER_DOMAIN_GPUMIX>; 684 clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 685 <&clk IMX8MM_CLK_GPU_AHB>; 686 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>, 687 <&clk IMX8MM_CLK_GPU_AHB>; 688 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 689 <&clk IMX8MM_SYS_PLL1_800M>; 690 assigned-clock-rates = <800000000>, <400000000>; 691 }; 692 693 pgc_gpu: power-domain@5 { 694 #power-domain-cells = <0>; 695 reg = <IMX8MM_POWER_DOMAIN_GPU>; 696 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 697 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 698 <&clk IMX8MM_CLK_GPU2D_ROOT>, 699 <&clk IMX8MM_CLK_GPU3D_ROOT>; 700 resets = <&src IMX8MQ_RESET_GPU_RESET>; 701 power-domains = <&pgc_gpumix>; 702 }; 703 704 pgc_vpumix: power-domain@6 { 705 #power-domain-cells = <0>; 706 reg = <IMX8MM_POWER_DOMAIN_VPUMIX>; 707 clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; 708 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>; 709 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>; 710 }; 711 712 pgc_vpu_g1: power-domain@7 { 713 #power-domain-cells = <0>; 714 reg = <IMX8MM_POWER_DOMAIN_VPUG1>; 715 }; 716 717 pgc_vpu_g2: power-domain@8 { 718 #power-domain-cells = <0>; 719 reg = <IMX8MM_POWER_DOMAIN_VPUG2>; 720 }; 721 722 pgc_vpu_h1: power-domain@9 { 723 #power-domain-cells = <0>; 724 reg = <IMX8MM_POWER_DOMAIN_VPUH1>; 725 }; 726 727 pgc_dispmix: power-domain@10 { 728 #power-domain-cells = <0>; 729 reg = <IMX8MM_POWER_DOMAIN_DISPMIX>; 730 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, 731 <&clk IMX8MM_CLK_DISP_AXI_ROOT>; 732 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>, 733 <&clk IMX8MM_CLK_DISP_APB>; 734 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, 735 <&clk IMX8MM_SYS_PLL1_800M>; 736 assigned-clock-rates = <500000000>, <200000000>; 737 }; 738 739 pgc_mipi: power-domain@11 { 740 #power-domain-cells = <0>; 741 reg = <IMX8MM_POWER_DOMAIN_MIPI>; 742 }; 743 }; 744 }; 745 }; 746 747 aips2: bus@30400000 { 748 compatible = "fsl,aips-bus", "simple-bus"; 749 reg = <0x30400000 0x400000>; 750 #address-cells = <1>; 751 #size-cells = <1>; 752 ranges = <0x30400000 0x30400000 0x400000>; 753 754 pwm1: pwm@30660000 { 755 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 756 reg = <0x30660000 0x10000>; 757 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, 759 <&clk IMX8MM_CLK_PWM1_ROOT>; 760 clock-names = "ipg", "per"; 761 #pwm-cells = <3>; 762 status = "disabled"; 763 }; 764 765 pwm2: pwm@30670000 { 766 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 767 reg = <0x30670000 0x10000>; 768 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, 770 <&clk IMX8MM_CLK_PWM2_ROOT>; 771 clock-names = "ipg", "per"; 772 #pwm-cells = <3>; 773 status = "disabled"; 774 }; 775 776 pwm3: pwm@30680000 { 777 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 778 reg = <0x30680000 0x10000>; 779 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, 781 <&clk IMX8MM_CLK_PWM3_ROOT>; 782 clock-names = "ipg", "per"; 783 #pwm-cells = <3>; 784 status = "disabled"; 785 }; 786 787 pwm4: pwm@30690000 { 788 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 789 reg = <0x30690000 0x10000>; 790 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, 792 <&clk IMX8MM_CLK_PWM4_ROOT>; 793 clock-names = "ipg", "per"; 794 #pwm-cells = <3>; 795 status = "disabled"; 796 }; 797 798 system_counter: timer@306a0000 { 799 compatible = "nxp,sysctr-timer"; 800 reg = <0x306a0000 0x20000>; 801 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&osc_24m>; 803 clock-names = "per"; 804 }; 805 }; 806 807 aips3: bus@30800000 { 808 compatible = "fsl,aips-bus", "simple-bus"; 809 reg = <0x30800000 0x400000>; 810 #address-cells = <1>; 811 #size-cells = <1>; 812 ranges = <0x30800000 0x30800000 0x400000>, 813 <0x8000000 0x8000000 0x10000000>; 814 815 spba1: spba-bus@30800000 { 816 compatible = "fsl,spba-bus", "simple-bus"; 817 #address-cells = <1>; 818 #size-cells = <1>; 819 reg = <0x30800000 0x100000>; 820 ranges; 821 822 ecspi1: spi@30820000 { 823 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 824 #address-cells = <1>; 825 #size-cells = <0>; 826 reg = <0x30820000 0x10000>; 827 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, 829 <&clk IMX8MM_CLK_ECSPI1_ROOT>; 830 clock-names = "ipg", "per"; 831 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 832 dma-names = "rx", "tx"; 833 status = "disabled"; 834 }; 835 836 ecspi2: spi@30830000 { 837 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 reg = <0x30830000 0x10000>; 841 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, 843 <&clk IMX8MM_CLK_ECSPI2_ROOT>; 844 clock-names = "ipg", "per"; 845 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 846 dma-names = "rx", "tx"; 847 status = "disabled"; 848 }; 849 850 ecspi3: spi@30840000 { 851 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 reg = <0x30840000 0x10000>; 855 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, 857 <&clk IMX8MM_CLK_ECSPI3_ROOT>; 858 clock-names = "ipg", "per"; 859 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 860 dma-names = "rx", "tx"; 861 status = "disabled"; 862 }; 863 864 uart1: serial@30860000 { 865 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 866 reg = <0x30860000 0x10000>; 867 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&clk IMX8MM_CLK_UART1_ROOT>, 869 <&clk IMX8MM_CLK_UART1_ROOT>; 870 clock-names = "ipg", "per"; 871 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 872 dma-names = "rx", "tx"; 873 status = "disabled"; 874 }; 875 876 uart3: serial@30880000 { 877 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 878 reg = <0x30880000 0x10000>; 879 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&clk IMX8MM_CLK_UART3_ROOT>, 881 <&clk IMX8MM_CLK_UART3_ROOT>; 882 clock-names = "ipg", "per"; 883 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 884 dma-names = "rx", "tx"; 885 status = "disabled"; 886 }; 887 888 uart2: serial@30890000 { 889 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 890 reg = <0x30890000 0x10000>; 891 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&clk IMX8MM_CLK_UART2_ROOT>, 893 <&clk IMX8MM_CLK_UART2_ROOT>; 894 clock-names = "ipg", "per"; 895 status = "disabled"; 896 }; 897 }; 898 899 crypto: crypto@30900000 { 900 compatible = "fsl,sec-v4.0"; 901 #address-cells = <1>; 902 #size-cells = <1>; 903 reg = <0x30900000 0x40000>; 904 ranges = <0 0x30900000 0x40000>; 905 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&clk IMX8MM_CLK_AHB>, 907 <&clk IMX8MM_CLK_IPG_ROOT>; 908 clock-names = "aclk", "ipg"; 909 910 sec_jr0: jr@1000 { 911 compatible = "fsl,sec-v4.0-job-ring"; 912 reg = <0x1000 0x1000>; 913 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 914 }; 915 916 sec_jr1: jr@2000 { 917 compatible = "fsl,sec-v4.0-job-ring"; 918 reg = <0x2000 0x1000>; 919 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 920 }; 921 922 sec_jr2: jr@3000 { 923 compatible = "fsl,sec-v4.0-job-ring"; 924 reg = <0x3000 0x1000>; 925 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 926 }; 927 }; 928 929 i2c1: i2c@30a20000 { 930 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 reg = <0x30a20000 0x10000>; 934 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; 936 status = "disabled"; 937 }; 938 939 i2c2: i2c@30a30000 { 940 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 reg = <0x30a30000 0x10000>; 944 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; 946 status = "disabled"; 947 }; 948 949 i2c3: i2c@30a40000 { 950 #address-cells = <1>; 951 #size-cells = <0>; 952 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 953 reg = <0x30a40000 0x10000>; 954 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; 956 status = "disabled"; 957 }; 958 959 i2c4: i2c@30a50000 { 960 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 reg = <0x30a50000 0x10000>; 964 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; 966 status = "disabled"; 967 }; 968 969 uart4: serial@30a60000 { 970 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 971 reg = <0x30a60000 0x10000>; 972 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&clk IMX8MM_CLK_UART4_ROOT>, 974 <&clk IMX8MM_CLK_UART4_ROOT>; 975 clock-names = "ipg", "per"; 976 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 977 dma-names = "rx", "tx"; 978 status = "disabled"; 979 }; 980 981 mu: mailbox@30aa0000 { 982 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; 983 reg = <0x30aa0000 0x10000>; 984 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&clk IMX8MM_CLK_MU_ROOT>; 986 #mbox-cells = <2>; 987 }; 988 989 usdhc1: mmc@30b40000 { 990 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 991 reg = <0x30b40000 0x10000>; 992 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 994 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 995 <&clk IMX8MM_CLK_USDHC1_ROOT>; 996 clock-names = "ipg", "ahb", "per"; 997 fsl,tuning-start-tap = <20>; 998 fsl,tuning-step= <2>; 999 bus-width = <4>; 1000 status = "disabled"; 1001 }; 1002 1003 usdhc2: mmc@30b50000 { 1004 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1005 reg = <0x30b50000 0x10000>; 1006 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 1008 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 1009 <&clk IMX8MM_CLK_USDHC2_ROOT>; 1010 clock-names = "ipg", "ahb", "per"; 1011 fsl,tuning-start-tap = <20>; 1012 fsl,tuning-step= <2>; 1013 bus-width = <4>; 1014 status = "disabled"; 1015 }; 1016 1017 usdhc3: mmc@30b60000 { 1018 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1019 reg = <0x30b60000 0x10000>; 1020 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 1022 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 1023 <&clk IMX8MM_CLK_USDHC3_ROOT>; 1024 clock-names = "ipg", "ahb", "per"; 1025 fsl,tuning-start-tap = <20>; 1026 fsl,tuning-step= <2>; 1027 bus-width = <4>; 1028 status = "disabled"; 1029 }; 1030 1031 flexspi: spi@30bb0000 { 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 compatible = "nxp,imx8mm-fspi"; 1035 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1036 reg-names = "fspi_base", "fspi_mmap"; 1037 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, 1039 <&clk IMX8MM_CLK_QSPI_ROOT>; 1040 clock-names = "fspi_en", "fspi"; 1041 status = "disabled"; 1042 }; 1043 1044 sdma1: dma-controller@30bd0000 { 1045 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 1046 reg = <0x30bd0000 0x10000>; 1047 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, 1049 <&clk IMX8MM_CLK_AHB>; 1050 clock-names = "ipg", "ahb"; 1051 #dma-cells = <3>; 1052 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1053 }; 1054 1055 fec1: ethernet@30be0000 { 1056 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1057 reg = <0x30be0000 0x10000>; 1058 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 1063 <&clk IMX8MM_CLK_ENET1_ROOT>, 1064 <&clk IMX8MM_CLK_ENET_TIMER>, 1065 <&clk IMX8MM_CLK_ENET_REF>, 1066 <&clk IMX8MM_CLK_ENET_PHY_REF>; 1067 clock-names = "ipg", "ahb", "ptp", 1068 "enet_clk_ref", "enet_out"; 1069 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 1070 <&clk IMX8MM_CLK_ENET_TIMER>, 1071 <&clk IMX8MM_CLK_ENET_REF>, 1072 <&clk IMX8MM_CLK_ENET_PHY_REF>; 1073 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 1074 <&clk IMX8MM_SYS_PLL2_100M>, 1075 <&clk IMX8MM_SYS_PLL2_125M>, 1076 <&clk IMX8MM_SYS_PLL2_50M>; 1077 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1078 fsl,num-tx-queues = <3>; 1079 fsl,num-rx-queues = <3>; 1080 nvmem-cells = <&fec_mac_address>; 1081 nvmem-cell-names = "mac-address"; 1082 fsl,stop-mode = <&gpr 0x10 3>; 1083 status = "disabled"; 1084 }; 1085 1086 }; 1087 1088 aips4: bus@32c00000 { 1089 compatible = "fsl,aips-bus", "simple-bus"; 1090 reg = <0x32c00000 0x400000>; 1091 #address-cells = <1>; 1092 #size-cells = <1>; 1093 ranges = <0x32c00000 0x32c00000 0x400000>; 1094 1095 csi: csi@32e20000 { 1096 compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; 1097 reg = <0x32e20000 0x1000>; 1098 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&clk IMX8MM_CLK_CSI1_ROOT>; 1100 clock-names = "mclk"; 1101 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>; 1102 status = "disabled"; 1103 1104 port { 1105 csi_in: endpoint { 1106 remote-endpoint = <&imx8mm_mipi_csi_out>; 1107 }; 1108 }; 1109 }; 1110 1111 disp_blk_ctrl: blk-ctrl@32e28000 { 1112 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; 1113 reg = <0x32e28000 0x100>; 1114 power-domains = <&pgc_dispmix>, <&pgc_dispmix>, 1115 <&pgc_dispmix>, <&pgc_mipi>, 1116 <&pgc_mipi>; 1117 power-domain-names = "bus", "csi-bridge", 1118 "lcdif", "mipi-dsi", 1119 "mipi-csi"; 1120 clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, 1121 <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1122 <&clk IMX8MM_CLK_CSI1_ROOT>, 1123 <&clk IMX8MM_CLK_DISP_AXI_ROOT>, 1124 <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1125 <&clk IMX8MM_CLK_DISP_ROOT>, 1126 <&clk IMX8MM_CLK_DSI_CORE>, 1127 <&clk IMX8MM_CLK_DSI_PHY_REF>, 1128 <&clk IMX8MM_CLK_CSI1_CORE>, 1129 <&clk IMX8MM_CLK_CSI1_PHY_REF>; 1130 clock-names = "csi-bridge-axi","csi-bridge-apb", 1131 "csi-bridge-core", "lcdif-axi", 1132 "lcdif-apb", "lcdif-pix", 1133 "dsi-pclk", "dsi-ref", 1134 "csi-aclk", "csi-pclk"; 1135 #power-domain-cells = <1>; 1136 }; 1137 1138 mipi_csi: mipi-csi@32e30000 { 1139 compatible = "fsl,imx8mm-mipi-csi2"; 1140 reg = <0x32e30000 0x1000>; 1141 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1142 assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>, 1143 <&clk IMX8MM_CLK_CSI1_PHY_REF>; 1144 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, 1145 <&clk IMX8MM_SYS_PLL2_1000M>; 1146 clock-frequency = <333000000>; 1147 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1148 <&clk IMX8MM_CLK_CSI1_ROOT>, 1149 <&clk IMX8MM_CLK_CSI1_PHY_REF>, 1150 <&clk IMX8MM_CLK_DISP_AXI_ROOT>; 1151 clock-names = "pclk", "wrap", "phy", "axi"; 1152 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>; 1153 status = "disabled"; 1154 1155 ports { 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 1159 port@0 { 1160 reg = <0>; 1161 }; 1162 1163 port@1 { 1164 reg = <1>; 1165 1166 imx8mm_mipi_csi_out: endpoint { 1167 remote-endpoint = <&csi_in>; 1168 }; 1169 }; 1170 }; 1171 }; 1172 1173 usbotg1: usb@32e40000 { 1174 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 1175 reg = <0x32e40000 0x200>; 1176 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 1178 clock-names = "usb1_ctrl_root_clk"; 1179 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 1180 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 1181 phys = <&usbphynop1>; 1182 fsl,usbmisc = <&usbmisc1 0>; 1183 power-domains = <&pgc_otg1>; 1184 status = "disabled"; 1185 }; 1186 1187 usbmisc1: usbmisc@32e40200 { 1188 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 1189 #index-cells = <1>; 1190 reg = <0x32e40200 0x200>; 1191 }; 1192 1193 usbotg2: usb@32e50000 { 1194 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 1195 reg = <0x32e50000 0x200>; 1196 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1197 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 1198 clock-names = "usb1_ctrl_root_clk"; 1199 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 1200 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 1201 phys = <&usbphynop2>; 1202 fsl,usbmisc = <&usbmisc2 0>; 1203 power-domains = <&pgc_otg2>; 1204 status = "disabled"; 1205 }; 1206 1207 usbmisc2: usbmisc@32e50200 { 1208 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 1209 #index-cells = <1>; 1210 reg = <0x32e50200 0x200>; 1211 }; 1212 1213 pcie_phy: pcie-phy@32f00000 { 1214 compatible = "fsl,imx8mm-pcie-phy"; 1215 reg = <0x32f00000 0x10000>; 1216 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 1217 clock-names = "ref"; 1218 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 1219 assigned-clock-rates = <100000000>; 1220 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>; 1221 resets = <&src IMX8MQ_RESET_PCIEPHY>; 1222 reset-names = "pciephy"; 1223 #phy-cells = <0>; 1224 status = "disabled"; 1225 }; 1226 }; 1227 1228 dma_apbh: dma-controller@33000000 { 1229 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1230 reg = <0x33000000 0x2000>; 1231 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1235 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1236 #dma-cells = <1>; 1237 dma-channels = <4>; 1238 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1239 }; 1240 1241 gpmi: nand-controller@33002000{ 1242 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1243 #address-cells = <1>; 1244 #size-cells = <1>; 1245 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1246 reg-names = "gpmi-nand", "bch"; 1247 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1248 interrupt-names = "bch"; 1249 clocks = <&clk IMX8MM_CLK_NAND_ROOT>, 1250 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1251 clock-names = "gpmi_io", "gpmi_bch_apb"; 1252 dmas = <&dma_apbh 0>; 1253 dma-names = "rx-tx"; 1254 status = "disabled"; 1255 }; 1256 1257 pcie0: pcie@33800000 { 1258 compatible = "fsl,imx8mm-pcie"; 1259 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 1260 reg-names = "dbi", "config"; 1261 #address-cells = <3>; 1262 #size-cells = <2>; 1263 device_type = "pci"; 1264 bus-range = <0x00 0xff>; 1265 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ 1266 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1267 num-lanes = <1>; 1268 num-viewport = <4>; 1269 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1270 interrupt-names = "msi"; 1271 #interrupt-cells = <1>; 1272 interrupt-map-mask = <0 0 0 0x7>; 1273 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1274 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1275 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1276 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1277 fsl,max-link-speed = <2>; 1278 linux,pci-domain = <0>; 1279 power-domains = <&pgc_pcie>; 1280 resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1281 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1282 reset-names = "apps", "turnoff"; 1283 phys = <&pcie_phy>; 1284 phy-names = "pcie-phy"; 1285 status = "disabled"; 1286 }; 1287 1288 gpu_3d: gpu@38000000 { 1289 compatible = "vivante,gc"; 1290 reg = <0x38000000 0x8000>; 1291 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1292 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 1293 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 1294 <&clk IMX8MM_CLK_GPU3D_ROOT>, 1295 <&clk IMX8MM_CLK_GPU3D_ROOT>; 1296 clock-names = "reg", "bus", "core", "shader"; 1297 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, 1298 <&clk IMX8MM_GPU_PLL_OUT>; 1299 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; 1300 assigned-clock-rates = <0>, <1000000000>; 1301 power-domains = <&pgc_gpu>; 1302 }; 1303 1304 gpu_2d: gpu@38008000 { 1305 compatible = "vivante,gc"; 1306 reg = <0x38008000 0x8000>; 1307 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1308 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 1309 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 1310 <&clk IMX8MM_CLK_GPU2D_ROOT>; 1311 clock-names = "reg", "bus", "core"; 1312 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, 1313 <&clk IMX8MM_GPU_PLL_OUT>; 1314 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; 1315 assigned-clock-rates = <0>, <1000000000>; 1316 power-domains = <&pgc_gpu>; 1317 }; 1318 1319 vpu_g1: video-codec@38300000 { 1320 compatible = "nxp,imx8mm-vpu-g1"; 1321 reg = <0x38300000 0x10000>; 1322 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1323 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; 1324 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; 1325 }; 1326 1327 vpu_g2: video-codec@38310000 { 1328 compatible = "nxp,imx8mq-vpu-g2"; 1329 reg = <0x38310000 0x10000>; 1330 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1331 clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; 1332 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; 1333 }; 1334 1335 vpu_blk_ctrl: blk-ctrl@38330000 { 1336 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; 1337 reg = <0x38330000 0x100>; 1338 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 1339 <&pgc_vpu_g2>, <&pgc_vpu_h1>; 1340 power-domain-names = "bus", "g1", "g2", "h1"; 1341 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, 1342 <&clk IMX8MM_CLK_VPU_G2_ROOT>, 1343 <&clk IMX8MM_CLK_VPU_H1_ROOT>; 1344 clock-names = "g1", "g2", "h1"; 1345 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, 1346 <&clk IMX8MM_CLK_VPU_G2>; 1347 assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, 1348 <&clk IMX8MM_VPU_PLL_OUT>; 1349 assigned-clock-rates = <600000000>, 1350 <600000000>; 1351 #power-domain-cells = <1>; 1352 }; 1353 1354 gic: interrupt-controller@38800000 { 1355 compatible = "arm,gic-v3"; 1356 reg = <0x38800000 0x10000>, /* GIC Dist */ 1357 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ 1358 #interrupt-cells = <3>; 1359 interrupt-controller; 1360 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1361 }; 1362 1363 ddrc: memory-controller@3d400000 { 1364 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; 1365 reg = <0x3d400000 0x400000>; 1366 clock-names = "core", "pll", "alt", "apb"; 1367 clocks = <&clk IMX8MM_CLK_DRAM_CORE>, 1368 <&clk IMX8MM_DRAM_PLL>, 1369 <&clk IMX8MM_CLK_DRAM_ALT>, 1370 <&clk IMX8MM_CLK_DRAM_APB>; 1371 }; 1372 1373 ddr-pmu@3d800000 { 1374 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1375 reg = <0x3d800000 0x400000>; 1376 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1377 }; 1378 }; 1379}; 1380