1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mm-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/thermal/thermal.h>
11
12#include "imx8mm-pinfunc.h"
13
14/ {
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	aliases {
20		ethernet0 = &fec1;
21		gpio0 = &gpio1;
22		gpio1 = &gpio2;
23		gpio2 = &gpio3;
24		gpio3 = &gpio4;
25		gpio4 = &gpio5;
26		i2c0 = &i2c1;
27		i2c1 = &i2c2;
28		i2c2 = &i2c3;
29		i2c3 = &i2c4;
30		mmc0 = &usdhc1;
31		mmc1 = &usdhc2;
32		mmc2 = &usdhc3;
33		serial0 = &uart1;
34		serial1 = &uart2;
35		serial2 = &uart3;
36		serial3 = &uart4;
37		spi0 = &ecspi1;
38		spi1 = &ecspi2;
39		spi2 = &ecspi3;
40	};
41
42	cpus {
43		#address-cells = <1>;
44		#size-cells = <0>;
45
46		idle-states {
47			entry-method = "psci";
48
49			cpu_pd_wait: cpu-pd-wait {
50				compatible = "arm,idle-state";
51				arm,psci-suspend-param = <0x0010033>;
52				local-timer-stop;
53				entry-latency-us = <1000>;
54				exit-latency-us = <700>;
55				min-residency-us = <2700>;
56			};
57		};
58
59		A53_0: cpu@0 {
60			device_type = "cpu";
61			compatible = "arm,cortex-a53";
62			reg = <0x0>;
63			clock-latency = <61036>; /* two CLK32 periods */
64			clocks = <&clk IMX8MM_CLK_ARM>;
65			enable-method = "psci";
66			next-level-cache = <&A53_L2>;
67			operating-points-v2 = <&a53_opp_table>;
68			nvmem-cells = <&cpu_speed_grade>;
69			nvmem-cell-names = "speed_grade";
70			cpu-idle-states = <&cpu_pd_wait>;
71			#cooling-cells = <2>;
72		};
73
74		A53_1: cpu@1 {
75			device_type = "cpu";
76			compatible = "arm,cortex-a53";
77			reg = <0x1>;
78			clock-latency = <61036>; /* two CLK32 periods */
79			clocks = <&clk IMX8MM_CLK_ARM>;
80			enable-method = "psci";
81			next-level-cache = <&A53_L2>;
82			operating-points-v2 = <&a53_opp_table>;
83			cpu-idle-states = <&cpu_pd_wait>;
84			#cooling-cells = <2>;
85		};
86
87		A53_2: cpu@2 {
88			device_type = "cpu";
89			compatible = "arm,cortex-a53";
90			reg = <0x2>;
91			clock-latency = <61036>; /* two CLK32 periods */
92			clocks = <&clk IMX8MM_CLK_ARM>;
93			enable-method = "psci";
94			next-level-cache = <&A53_L2>;
95			operating-points-v2 = <&a53_opp_table>;
96			cpu-idle-states = <&cpu_pd_wait>;
97			#cooling-cells = <2>;
98		};
99
100		A53_3: cpu@3 {
101			device_type = "cpu";
102			compatible = "arm,cortex-a53";
103			reg = <0x3>;
104			clock-latency = <61036>; /* two CLK32 periods */
105			clocks = <&clk IMX8MM_CLK_ARM>;
106			enable-method = "psci";
107			next-level-cache = <&A53_L2>;
108			operating-points-v2 = <&a53_opp_table>;
109			cpu-idle-states = <&cpu_pd_wait>;
110			#cooling-cells = <2>;
111		};
112
113		A53_L2: l2-cache0 {
114			compatible = "cache";
115		};
116	};
117
118	a53_opp_table: opp-table {
119		compatible = "operating-points-v2";
120		opp-shared;
121
122		opp-1200000000 {
123			opp-hz = /bits/ 64 <1200000000>;
124			opp-microvolt = <850000>;
125			opp-supported-hw = <0xe>, <0x7>;
126			clock-latency-ns = <150000>;
127			opp-suspend;
128		};
129
130		opp-1600000000 {
131			opp-hz = /bits/ 64 <1600000000>;
132			opp-microvolt = <950000>;
133			opp-supported-hw = <0xc>, <0x7>;
134			clock-latency-ns = <150000>;
135			opp-suspend;
136		};
137
138		opp-1800000000 {
139			opp-hz = /bits/ 64 <1800000000>;
140			opp-microvolt = <1000000>;
141			opp-supported-hw = <0x8>, <0x3>;
142			clock-latency-ns = <150000>;
143			opp-suspend;
144		};
145	};
146
147	osc_32k: clock-osc-32k {
148		compatible = "fixed-clock";
149		#clock-cells = <0>;
150		clock-frequency = <32768>;
151		clock-output-names = "osc_32k";
152	};
153
154	osc_24m: clock-osc-24m {
155		compatible = "fixed-clock";
156		#clock-cells = <0>;
157		clock-frequency = <24000000>;
158		clock-output-names = "osc_24m";
159	};
160
161	clk_ext1: clock-ext1 {
162		compatible = "fixed-clock";
163		#clock-cells = <0>;
164		clock-frequency = <133000000>;
165		clock-output-names = "clk_ext1";
166	};
167
168	clk_ext2: clock-ext2 {
169		compatible = "fixed-clock";
170		#clock-cells = <0>;
171		clock-frequency = <133000000>;
172		clock-output-names = "clk_ext2";
173	};
174
175	clk_ext3: clock-ext3 {
176		compatible = "fixed-clock";
177		#clock-cells = <0>;
178		clock-frequency = <133000000>;
179		clock-output-names = "clk_ext3";
180	};
181
182	clk_ext4: clock-ext4 {
183		compatible = "fixed-clock";
184		#clock-cells = <0>;
185		clock-frequency= <133000000>;
186		clock-output-names = "clk_ext4";
187	};
188
189	psci {
190		compatible = "arm,psci-1.0";
191		method = "smc";
192	};
193
194	pmu {
195		compatible = "arm,armv8-pmuv3";
196		interrupts = <GIC_PPI 7
197			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
198		interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
199	};
200
201	timer {
202		compatible = "arm,armv8-timer";
203		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
204			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
205			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
206			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
207		clock-frequency = <8000000>;
208		arm,no-tick-in-suspend;
209	};
210
211	thermal-zones {
212		cpu-thermal {
213			polling-delay-passive = <250>;
214			polling-delay = <2000>;
215			thermal-sensors = <&tmu>;
216			trips {
217				cpu_alert0: trip0 {
218					temperature = <85000>;
219					hysteresis = <2000>;
220					type = "passive";
221				};
222
223				cpu_crit0: trip1 {
224					temperature = <95000>;
225					hysteresis = <2000>;
226					type = "critical";
227				};
228			};
229
230			cooling-maps {
231				map0 {
232					trip = <&cpu_alert0>;
233					cooling-device =
234						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
235						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
236						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
237						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
238				};
239			};
240		};
241	};
242
243	usbphynop1: usbphynop1 {
244		compatible = "usb-nop-xceiv";
245		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
246		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
247		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
248		clock-names = "main_clk";
249	};
250
251	usbphynop2: usbphynop2 {
252		compatible = "usb-nop-xceiv";
253		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
254		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
255		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
256		clock-names = "main_clk";
257	};
258
259	soc@0 {
260		compatible = "fsl,imx8mm-soc", "simple-bus";
261		#address-cells = <1>;
262		#size-cells = <1>;
263		ranges = <0x0 0x0 0x0 0x3e000000>;
264		dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
265		nvmem-cells = <&imx8mm_uid>;
266		nvmem-cell-names = "soc_unique_id";
267
268		aips1: bus@30000000 {
269			compatible = "fsl,aips-bus", "simple-bus";
270			reg = <0x30000000 0x400000>;
271			#address-cells = <1>;
272			#size-cells = <1>;
273			ranges = <0x30000000 0x30000000 0x400000>;
274
275			spba2: spba-bus@30000000 {
276				compatible = "fsl,spba-bus", "simple-bus";
277				#address-cells = <1>;
278				#size-cells = <1>;
279				reg = <0x30000000 0x100000>;
280				ranges;
281
282				sai1: sai@30010000 {
283					#sound-dai-cells = <0>;
284					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
285					reg = <0x30010000 0x10000>;
286					interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
287					clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
288						 <&clk IMX8MM_CLK_SAI1_ROOT>,
289						 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
290					clock-names = "bus", "mclk1", "mclk2", "mclk3";
291					dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
292					dma-names = "rx", "tx";
293					status = "disabled";
294				};
295
296				sai2: sai@30020000 {
297					#sound-dai-cells = <0>;
298					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
299					reg = <0x30020000 0x10000>;
300					interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
301					clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
302						<&clk IMX8MM_CLK_SAI2_ROOT>,
303						<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
304					clock-names = "bus", "mclk1", "mclk2", "mclk3";
305					dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
306					dma-names = "rx", "tx";
307					status = "disabled";
308				};
309
310				sai3: sai@30030000 {
311					#sound-dai-cells = <0>;
312					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
313					reg = <0x30030000 0x10000>;
314					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
315					clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
316						 <&clk IMX8MM_CLK_SAI3_ROOT>,
317						 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
318					clock-names = "bus", "mclk1", "mclk2", "mclk3";
319					dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
320					dma-names = "rx", "tx";
321					status = "disabled";
322				};
323
324				sai5: sai@30050000 {
325					#sound-dai-cells = <0>;
326					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
327					reg = <0x30050000 0x10000>;
328					interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
329					clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
330						 <&clk IMX8MM_CLK_SAI5_ROOT>,
331						 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
332					clock-names = "bus", "mclk1", "mclk2", "mclk3";
333					dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
334					dma-names = "rx", "tx";
335					status = "disabled";
336				};
337
338				sai6: sai@30060000 {
339					#sound-dai-cells = <0>;
340					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
341					reg = <0x30060000 0x10000>;
342					interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
343					clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
344						 <&clk IMX8MM_CLK_SAI6_ROOT>,
345						 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
346					clock-names = "bus", "mclk1", "mclk2", "mclk3";
347					dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
348					dma-names = "rx", "tx";
349					status = "disabled";
350				};
351
352				micfil: audio-controller@30080000 {
353					compatible = "fsl,imx8mm-micfil";
354					reg = <0x30080000 0x10000>;
355					interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
356						     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
357						     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
358						     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
359					clocks = <&clk IMX8MM_CLK_PDM_IPG>,
360						 <&clk IMX8MM_CLK_PDM_ROOT>,
361						 <&clk IMX8MM_AUDIO_PLL1_OUT>,
362						 <&clk IMX8MM_AUDIO_PLL2_OUT>,
363						 <&clk IMX8MM_CLK_EXT3>;
364					clock-names = "ipg_clk", "ipg_clk_app",
365						      "pll8k", "pll11k", "clkext3";
366					dmas = <&sdma2 24 25 0x80000000>;
367					dma-names = "rx";
368					status = "disabled";
369				};
370
371				spdif1: spdif@30090000 {
372					compatible = "fsl,imx35-spdif";
373					reg = <0x30090000 0x10000>;
374					interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
375					clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
376						 <&clk IMX8MM_CLK_24M>, /* rxtx0 */
377						 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
378						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
379						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
380						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
381						 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
382						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
383						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
384						 <&clk IMX8MM_CLK_DUMMY>; /* spba */
385					clock-names = "core", "rxtx0",
386						      "rxtx1", "rxtx2",
387						      "rxtx3", "rxtx4",
388						      "rxtx5", "rxtx6",
389						      "rxtx7", "spba";
390					dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
391					dma-names = "rx", "tx";
392					status = "disabled";
393				};
394			};
395
396			gpio1: gpio@30200000 {
397				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
398				reg = <0x30200000 0x10000>;
399				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
400					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
401				clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
402				gpio-controller;
403				#gpio-cells = <2>;
404				interrupt-controller;
405				#interrupt-cells = <2>;
406				gpio-ranges = <&iomuxc 0 10 30>;
407			};
408
409			gpio2: gpio@30210000 {
410				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
411				reg = <0x30210000 0x10000>;
412				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
413					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
414				clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
415				gpio-controller;
416				#gpio-cells = <2>;
417				interrupt-controller;
418				#interrupt-cells = <2>;
419				gpio-ranges = <&iomuxc 0 40 21>;
420			};
421
422			gpio3: gpio@30220000 {
423				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
424				reg = <0x30220000 0x10000>;
425				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
426					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
427				clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
428				gpio-controller;
429				#gpio-cells = <2>;
430				interrupt-controller;
431				#interrupt-cells = <2>;
432				gpio-ranges = <&iomuxc 0 61 26>;
433			};
434
435			gpio4: gpio@30230000 {
436				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
437				reg = <0x30230000 0x10000>;
438				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
439					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
440				clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
441				gpio-controller;
442				#gpio-cells = <2>;
443				interrupt-controller;
444				#interrupt-cells = <2>;
445				gpio-ranges = <&iomuxc 0 87 32>;
446			};
447
448			gpio5: gpio@30240000 {
449				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
450				reg = <0x30240000 0x10000>;
451				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
452					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
453				clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
454				gpio-controller;
455				#gpio-cells = <2>;
456				interrupt-controller;
457				#interrupt-cells = <2>;
458				gpio-ranges = <&iomuxc 0 119 30>;
459			};
460
461			tmu: tmu@30260000 {
462				compatible = "fsl,imx8mm-tmu";
463				reg = <0x30260000 0x10000>;
464				clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
465				#thermal-sensor-cells = <0>;
466			};
467
468			wdog1: watchdog@30280000 {
469				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
470				reg = <0x30280000 0x10000>;
471				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
472				clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
473				status = "disabled";
474			};
475
476			wdog2: watchdog@30290000 {
477				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
478				reg = <0x30290000 0x10000>;
479				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
480				clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
481				status = "disabled";
482			};
483
484			wdog3: watchdog@302a0000 {
485				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
486				reg = <0x302a0000 0x10000>;
487				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
488				clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
489				status = "disabled";
490			};
491
492			sdma2: dma-controller@302c0000 {
493				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
494				reg = <0x302c0000 0x10000>;
495				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
496				clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
497					 <&clk IMX8MM_CLK_SDMA2_ROOT>;
498				clock-names = "ipg", "ahb";
499				#dma-cells = <3>;
500				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
501			};
502
503			sdma3: dma-controller@302b0000 {
504				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
505				reg = <0x302b0000 0x10000>;
506				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
507				clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
508				 <&clk IMX8MM_CLK_SDMA3_ROOT>;
509				clock-names = "ipg", "ahb";
510				#dma-cells = <3>;
511				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
512			};
513
514			iomuxc: pinctrl@30330000 {
515				compatible = "fsl,imx8mm-iomuxc";
516				reg = <0x30330000 0x10000>;
517			};
518
519			gpr: iomuxc-gpr@30340000 {
520				compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
521				reg = <0x30340000 0x10000>;
522			};
523
524			ocotp: efuse@30350000 {
525				compatible = "fsl,imx8mm-ocotp", "syscon";
526				reg = <0x30350000 0x10000>;
527				clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
528				/* For nvmem subnodes */
529				#address-cells = <1>;
530				#size-cells = <1>;
531
532				imx8mm_uid: unique-id@410 {
533					reg = <0x4 0x8>;
534				};
535
536				cpu_speed_grade: speed-grade@10 {
537					reg = <0x10 4>;
538				};
539
540				fec_mac_address: mac-address@90 {
541					reg = <0x90 6>;
542				};
543			};
544
545			anatop: anatop@30360000 {
546				compatible = "fsl,imx8mm-anatop", "syscon";
547				reg = <0x30360000 0x10000>;
548			};
549
550			snvs: snvs@30370000 {
551				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
552				reg = <0x30370000 0x10000>;
553
554				snvs_rtc: snvs-rtc-lp {
555					compatible = "fsl,sec-v4.0-mon-rtc-lp";
556					regmap = <&snvs>;
557					offset = <0x34>;
558					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
559						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
560					clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
561					clock-names = "snvs-rtc";
562				};
563
564				snvs_pwrkey: snvs-powerkey {
565					compatible = "fsl,sec-v4.0-pwrkey";
566					regmap = <&snvs>;
567					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
568					clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
569					clock-names = "snvs-pwrkey";
570					linux,keycode = <KEY_POWER>;
571					wakeup-source;
572					status = "disabled";
573				};
574			};
575
576			clk: clock-controller@30380000 {
577				compatible = "fsl,imx8mm-ccm";
578				reg = <0x30380000 0x10000>;
579				#clock-cells = <1>;
580				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
581					 <&clk_ext3>, <&clk_ext4>;
582				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
583					      "clk_ext3", "clk_ext4";
584				assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
585						<&clk IMX8MM_CLK_A53_CORE>,
586						<&clk IMX8MM_CLK_NOC>,
587						<&clk IMX8MM_CLK_AUDIO_AHB>,
588						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
589						<&clk IMX8MM_SYS_PLL3>,
590						<&clk IMX8MM_VIDEO_PLL1>,
591						<&clk IMX8MM_AUDIO_PLL1>,
592						<&clk IMX8MM_AUDIO_PLL2>;
593				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
594							 <&clk IMX8MM_ARM_PLL_OUT>,
595							 <&clk IMX8MM_SYS_PLL3_OUT>,
596							 <&clk IMX8MM_SYS_PLL1_800M>;
597				assigned-clock-rates = <0>, <0>, <0>,
598							<400000000>,
599							<400000000>,
600							<750000000>,
601							<594000000>,
602							<393216000>,
603							<361267200>;
604			};
605
606			src: reset-controller@30390000 {
607				compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
608				reg = <0x30390000 0x10000>;
609				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
610				#reset-cells = <1>;
611			};
612		};
613
614		aips2: bus@30400000 {
615			compatible = "fsl,aips-bus", "simple-bus";
616			reg = <0x30400000 0x400000>;
617			#address-cells = <1>;
618			#size-cells = <1>;
619			ranges = <0x30400000 0x30400000 0x400000>;
620
621			pwm1: pwm@30660000 {
622				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
623				reg = <0x30660000 0x10000>;
624				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
625				clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
626					<&clk IMX8MM_CLK_PWM1_ROOT>;
627				clock-names = "ipg", "per";
628				#pwm-cells = <2>;
629				status = "disabled";
630			};
631
632			pwm2: pwm@30670000 {
633				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
634				reg = <0x30670000 0x10000>;
635				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
636				clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
637					 <&clk IMX8MM_CLK_PWM2_ROOT>;
638				clock-names = "ipg", "per";
639				#pwm-cells = <2>;
640				status = "disabled";
641			};
642
643			pwm3: pwm@30680000 {
644				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
645				reg = <0x30680000 0x10000>;
646				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
647				clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
648					 <&clk IMX8MM_CLK_PWM3_ROOT>;
649				clock-names = "ipg", "per";
650				#pwm-cells = <2>;
651				status = "disabled";
652			};
653
654			pwm4: pwm@30690000 {
655				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
656				reg = <0x30690000 0x10000>;
657				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
658				clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
659					 <&clk IMX8MM_CLK_PWM4_ROOT>;
660				clock-names = "ipg", "per";
661				#pwm-cells = <2>;
662				status = "disabled";
663			};
664
665			system_counter: timer@306a0000 {
666				compatible = "nxp,sysctr-timer";
667				reg = <0x306a0000 0x20000>;
668				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
669				clocks = <&osc_24m>;
670				clock-names = "per";
671			};
672		};
673
674		aips3: bus@30800000 {
675			compatible = "fsl,aips-bus", "simple-bus";
676			reg = <0x30800000 0x400000>;
677			#address-cells = <1>;
678			#size-cells = <1>;
679			ranges = <0x30800000 0x30800000 0x400000>,
680				 <0x8000000 0x8000000 0x10000000>;
681
682			spba1: spba-bus@30800000 {
683				compatible = "fsl,spba-bus", "simple-bus";
684				#address-cells = <1>;
685				#size-cells = <1>;
686				reg = <0x30800000 0x100000>;
687				ranges;
688
689				ecspi1: spi@30820000 {
690					compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
691					#address-cells = <1>;
692					#size-cells = <0>;
693					reg = <0x30820000 0x10000>;
694					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
695					clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
696						 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
697					clock-names = "ipg", "per";
698					dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
699					dma-names = "rx", "tx";
700					status = "disabled";
701				};
702
703				ecspi2: spi@30830000 {
704					compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
705					#address-cells = <1>;
706					#size-cells = <0>;
707					reg = <0x30830000 0x10000>;
708					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
709					clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
710						 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
711					clock-names = "ipg", "per";
712					dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
713					dma-names = "rx", "tx";
714					status = "disabled";
715				};
716
717				ecspi3: spi@30840000 {
718					compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
719					#address-cells = <1>;
720					#size-cells = <0>;
721					reg = <0x30840000 0x10000>;
722					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
723					clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
724						 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
725					clock-names = "ipg", "per";
726					dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
727					dma-names = "rx", "tx";
728					status = "disabled";
729				};
730
731				uart1: serial@30860000 {
732					compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
733					reg = <0x30860000 0x10000>;
734					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
735					clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
736						 <&clk IMX8MM_CLK_UART1_ROOT>;
737					clock-names = "ipg", "per";
738					dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
739					dma-names = "rx", "tx";
740					status = "disabled";
741				};
742
743				uart3: serial@30880000 {
744					compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
745					reg = <0x30880000 0x10000>;
746					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
747					clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
748						 <&clk IMX8MM_CLK_UART3_ROOT>;
749					clock-names = "ipg", "per";
750					dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
751					dma-names = "rx", "tx";
752					status = "disabled";
753				};
754
755				uart2: serial@30890000 {
756					compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
757					reg = <0x30890000 0x10000>;
758					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
759					clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
760						 <&clk IMX8MM_CLK_UART2_ROOT>;
761					clock-names = "ipg", "per";
762					status = "disabled";
763				};
764			};
765
766			crypto: crypto@30900000 {
767				compatible = "fsl,sec-v4.0";
768				#address-cells = <1>;
769				#size-cells = <1>;
770				reg = <0x30900000 0x40000>;
771				ranges = <0 0x30900000 0x40000>;
772				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
773				clocks = <&clk IMX8MM_CLK_AHB>,
774					 <&clk IMX8MM_CLK_IPG_ROOT>;
775				clock-names = "aclk", "ipg";
776
777				sec_jr0: jr@1000 {
778					compatible = "fsl,sec-v4.0-job-ring";
779					reg = <0x1000 0x1000>;
780					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
781				};
782
783				sec_jr1: jr@2000 {
784					compatible = "fsl,sec-v4.0-job-ring";
785					reg = <0x2000 0x1000>;
786					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
787				};
788
789				sec_jr2: jr@3000 {
790					compatible = "fsl,sec-v4.0-job-ring";
791					reg = <0x3000 0x1000>;
792					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
793				};
794			};
795
796			i2c1: i2c@30a20000 {
797				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
798				#address-cells = <1>;
799				#size-cells = <0>;
800				reg = <0x30a20000 0x10000>;
801				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
802				clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
803				status = "disabled";
804			};
805
806			i2c2: i2c@30a30000 {
807				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
808				#address-cells = <1>;
809				#size-cells = <0>;
810				reg = <0x30a30000 0x10000>;
811				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
812				clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
813				status = "disabled";
814			};
815
816			i2c3: i2c@30a40000 {
817				#address-cells = <1>;
818				#size-cells = <0>;
819				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
820				reg = <0x30a40000 0x10000>;
821				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
822				clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
823				status = "disabled";
824			};
825
826			i2c4: i2c@30a50000 {
827				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
828				#address-cells = <1>;
829				#size-cells = <0>;
830				reg = <0x30a50000 0x10000>;
831				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
832				clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
833				status = "disabled";
834			};
835
836			uart4: serial@30a60000 {
837				compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
838				reg = <0x30a60000 0x10000>;
839				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
840				clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
841					 <&clk IMX8MM_CLK_UART4_ROOT>;
842				clock-names = "ipg", "per";
843				dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
844				dma-names = "rx", "tx";
845				status = "disabled";
846			};
847
848			mu: mailbox@30aa0000 {
849				compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
850				reg = <0x30aa0000 0x10000>;
851				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
852				clocks = <&clk IMX8MM_CLK_MU_ROOT>;
853				#mbox-cells = <2>;
854			};
855
856			usdhc1: mmc@30b40000 {
857				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
858				reg = <0x30b40000 0x10000>;
859				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
860				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
861					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
862					 <&clk IMX8MM_CLK_USDHC1_ROOT>;
863				clock-names = "ipg", "ahb", "per";
864				fsl,tuning-start-tap = <20>;
865				fsl,tuning-step= <2>;
866				bus-width = <4>;
867				status = "disabled";
868			};
869
870			usdhc2: mmc@30b50000 {
871				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
872				reg = <0x30b50000 0x10000>;
873				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
874				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
875					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
876					 <&clk IMX8MM_CLK_USDHC2_ROOT>;
877				clock-names = "ipg", "ahb", "per";
878				fsl,tuning-start-tap = <20>;
879				fsl,tuning-step= <2>;
880				bus-width = <4>;
881				status = "disabled";
882			};
883
884			usdhc3: mmc@30b60000 {
885				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
886				reg = <0x30b60000 0x10000>;
887				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
888				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
889					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
890					 <&clk IMX8MM_CLK_USDHC3_ROOT>;
891				clock-names = "ipg", "ahb", "per";
892				fsl,tuning-start-tap = <20>;
893				fsl,tuning-step= <2>;
894				bus-width = <4>;
895				status = "disabled";
896			};
897
898			flexspi: spi@30bb0000 {
899				#address-cells = <1>;
900				#size-cells = <0>;
901				compatible = "nxp,imx8mm-fspi";
902				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
903				reg-names = "fspi_base", "fspi_mmap";
904				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
905				clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
906					 <&clk IMX8MM_CLK_QSPI_ROOT>;
907				clock-names = "fspi_en", "fspi";
908				status = "disabled";
909			};
910
911			sdma1: dma-controller@30bd0000 {
912				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
913				reg = <0x30bd0000 0x10000>;
914				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
915				clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
916					 <&clk IMX8MM_CLK_AHB>;
917				clock-names = "ipg", "ahb";
918				#dma-cells = <3>;
919				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
920			};
921
922			fec1: ethernet@30be0000 {
923				compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
924				reg = <0x30be0000 0x10000>;
925				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
926					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
927					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
928					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
929				clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
930					 <&clk IMX8MM_CLK_ENET1_ROOT>,
931					 <&clk IMX8MM_CLK_ENET_TIMER>,
932					 <&clk IMX8MM_CLK_ENET_REF>,
933					 <&clk IMX8MM_CLK_ENET_PHY_REF>;
934				clock-names = "ipg", "ahb", "ptp",
935					      "enet_clk_ref", "enet_out";
936				assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
937						  <&clk IMX8MM_CLK_ENET_TIMER>,
938						  <&clk IMX8MM_CLK_ENET_REF>,
939						  <&clk IMX8MM_CLK_ENET_PHY_REF>;
940				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
941							 <&clk IMX8MM_SYS_PLL2_100M>,
942							 <&clk IMX8MM_SYS_PLL2_125M>,
943							 <&clk IMX8MM_SYS_PLL2_50M>;
944				assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
945				fsl,num-tx-queues = <3>;
946				fsl,num-rx-queues = <3>;
947				nvmem-cells = <&fec_mac_address>;
948				nvmem-cell-names = "mac-address";
949				nvmem_macaddr_swap;
950				fsl,stop-mode = <&gpr 0x10 3>;
951				status = "disabled";
952			};
953
954		};
955
956		aips4: bus@32c00000 {
957			compatible = "fsl,aips-bus", "simple-bus";
958			reg = <0x32c00000 0x400000>;
959			#address-cells = <1>;
960			#size-cells = <1>;
961			ranges = <0x32c00000 0x32c00000 0x400000>;
962
963			usbotg1: usb@32e40000 {
964				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
965				reg = <0x32e40000 0x200>;
966				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
967				clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
968				clock-names = "usb1_ctrl_root_clk";
969				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
970				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
971				fsl,usbphy = <&usbphynop1>;
972				fsl,usbmisc = <&usbmisc1 0>;
973				status = "disabled";
974			};
975
976			usbmisc1: usbmisc@32e40200 {
977				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
978				#index-cells = <1>;
979				reg = <0x32e40200 0x200>;
980			};
981
982			usbotg2: usb@32e50000 {
983				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
984				reg = <0x32e50000 0x200>;
985				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
986				clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
987				clock-names = "usb1_ctrl_root_clk";
988				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
989				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
990				fsl,usbphy = <&usbphynop2>;
991				fsl,usbmisc = <&usbmisc2 0>;
992				status = "disabled";
993			};
994
995			usbmisc2: usbmisc@32e50200 {
996				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
997				#index-cells = <1>;
998				reg = <0x32e50200 0x200>;
999			};
1000
1001		};
1002
1003		dma_apbh: dma-controller@33000000 {
1004			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1005			reg = <0x33000000 0x2000>;
1006			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1007				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1008				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1009				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1010			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1011			#dma-cells = <1>;
1012			dma-channels = <4>;
1013			clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1014		};
1015
1016		gpmi: nand-controller@33002000{
1017			compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1018			#address-cells = <1>;
1019			#size-cells = <1>;
1020			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1021			reg-names = "gpmi-nand", "bch";
1022			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1023			interrupt-names = "bch";
1024			clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
1025				 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1026			clock-names = "gpmi_io", "gpmi_bch_apb";
1027			dmas = <&dma_apbh 0>;
1028			dma-names = "rx-tx";
1029			status = "disabled";
1030		};
1031
1032		gic: interrupt-controller@38800000 {
1033			compatible = "arm,gic-v3";
1034			reg = <0x38800000 0x10000>, /* GIC Dist */
1035			      <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
1036			#interrupt-cells = <3>;
1037			interrupt-controller;
1038			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1039		};
1040
1041		ddrc: memory-controller@3d400000 {
1042			compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1043			reg = <0x3d400000 0x400000>;
1044			clock-names = "core", "pll", "alt", "apb";
1045			clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
1046				 <&clk IMX8MM_DRAM_PLL>,
1047				 <&clk IMX8MM_CLK_DRAM_ALT>,
1048				 <&clk IMX8MM_CLK_DRAM_APB>;
1049		};
1050
1051		ddr-pmu@3d800000 {
1052			compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
1053			reg = <0x3d800000 0x400000>;
1054			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1055		};
1056	};
1057};
1058