1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mm-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/imx8mm-power.h>
11#include <dt-bindings/reset/imx8mq-reset.h>
12#include <dt-bindings/thermal/thermal.h>
13
14#include "imx8mm-pinfunc.h"
15
16/ {
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		ethernet0 = &fec1;
23		gpio0 = &gpio1;
24		gpio1 = &gpio2;
25		gpio2 = &gpio3;
26		gpio3 = &gpio4;
27		gpio4 = &gpio5;
28		i2c0 = &i2c1;
29		i2c1 = &i2c2;
30		i2c2 = &i2c3;
31		i2c3 = &i2c4;
32		mmc0 = &usdhc1;
33		mmc1 = &usdhc2;
34		mmc2 = &usdhc3;
35		serial0 = &uart1;
36		serial1 = &uart2;
37		serial2 = &uart3;
38		serial3 = &uart4;
39		spi0 = &ecspi1;
40		spi1 = &ecspi2;
41		spi2 = &ecspi3;
42	};
43
44	cpus {
45		#address-cells = <1>;
46		#size-cells = <0>;
47
48		idle-states {
49			entry-method = "psci";
50
51			cpu_pd_wait: cpu-pd-wait {
52				compatible = "arm,idle-state";
53				arm,psci-suspend-param = <0x0010033>;
54				local-timer-stop;
55				entry-latency-us = <1000>;
56				exit-latency-us = <700>;
57				min-residency-us = <2700>;
58			};
59		};
60
61		A53_0: cpu@0 {
62			device_type = "cpu";
63			compatible = "arm,cortex-a53";
64			reg = <0x0>;
65			clock-latency = <61036>; /* two CLK32 periods */
66			clocks = <&clk IMX8MM_CLK_ARM>;
67			enable-method = "psci";
68			i-cache-size = <0x8000>;
69			i-cache-line-size = <64>;
70			i-cache-sets = <256>;
71			d-cache-size = <0x8000>;
72			d-cache-line-size = <64>;
73			d-cache-sets = <128>;
74			next-level-cache = <&A53_L2>;
75			operating-points-v2 = <&a53_opp_table>;
76			nvmem-cells = <&cpu_speed_grade>;
77			nvmem-cell-names = "speed_grade";
78			cpu-idle-states = <&cpu_pd_wait>;
79			#cooling-cells = <2>;
80		};
81
82		A53_1: cpu@1 {
83			device_type = "cpu";
84			compatible = "arm,cortex-a53";
85			reg = <0x1>;
86			clock-latency = <61036>; /* two CLK32 periods */
87			clocks = <&clk IMX8MM_CLK_ARM>;
88			enable-method = "psci";
89			i-cache-size = <0x8000>;
90			i-cache-line-size = <64>;
91			i-cache-sets = <256>;
92			d-cache-size = <0x8000>;
93			d-cache-line-size = <64>;
94			d-cache-sets = <128>;
95			next-level-cache = <&A53_L2>;
96			operating-points-v2 = <&a53_opp_table>;
97			cpu-idle-states = <&cpu_pd_wait>;
98			#cooling-cells = <2>;
99		};
100
101		A53_2: cpu@2 {
102			device_type = "cpu";
103			compatible = "arm,cortex-a53";
104			reg = <0x2>;
105			clock-latency = <61036>; /* two CLK32 periods */
106			clocks = <&clk IMX8MM_CLK_ARM>;
107			enable-method = "psci";
108			i-cache-size = <0x8000>;
109			i-cache-line-size = <64>;
110			i-cache-sets = <256>;
111			d-cache-size = <0x8000>;
112			d-cache-line-size = <64>;
113			d-cache-sets = <128>;
114			next-level-cache = <&A53_L2>;
115			operating-points-v2 = <&a53_opp_table>;
116			cpu-idle-states = <&cpu_pd_wait>;
117			#cooling-cells = <2>;
118		};
119
120		A53_3: cpu@3 {
121			device_type = "cpu";
122			compatible = "arm,cortex-a53";
123			reg = <0x3>;
124			clock-latency = <61036>; /* two CLK32 periods */
125			clocks = <&clk IMX8MM_CLK_ARM>;
126			enable-method = "psci";
127			i-cache-size = <0x8000>;
128			i-cache-line-size = <64>;
129			i-cache-sets = <256>;
130			d-cache-size = <0x8000>;
131			d-cache-line-size = <64>;
132			d-cache-sets = <128>;
133			next-level-cache = <&A53_L2>;
134			operating-points-v2 = <&a53_opp_table>;
135			cpu-idle-states = <&cpu_pd_wait>;
136			#cooling-cells = <2>;
137		};
138
139		A53_L2: l2-cache0 {
140			compatible = "cache";
141			cache-level = <2>;
142			cache-unified;
143			cache-size = <0x80000>;
144			cache-line-size = <64>;
145			cache-sets = <512>;
146		};
147	};
148
149	a53_opp_table: opp-table {
150		compatible = "operating-points-v2";
151		opp-shared;
152
153		opp-1200000000 {
154			opp-hz = /bits/ 64 <1200000000>;
155			opp-microvolt = <850000>;
156			opp-supported-hw = <0xe>, <0x7>;
157			clock-latency-ns = <150000>;
158			opp-suspend;
159		};
160
161		opp-1600000000 {
162			opp-hz = /bits/ 64 <1600000000>;
163			opp-microvolt = <950000>;
164			opp-supported-hw = <0xc>, <0x7>;
165			clock-latency-ns = <150000>;
166			opp-suspend;
167		};
168
169		opp-1800000000 {
170			opp-hz = /bits/ 64 <1800000000>;
171			opp-microvolt = <1000000>;
172			opp-supported-hw = <0x8>, <0x3>;
173			clock-latency-ns = <150000>;
174			opp-suspend;
175		};
176	};
177
178	osc_32k: clock-osc-32k {
179		compatible = "fixed-clock";
180		#clock-cells = <0>;
181		clock-frequency = <32768>;
182		clock-output-names = "osc_32k";
183	};
184
185	osc_24m: clock-osc-24m {
186		compatible = "fixed-clock";
187		#clock-cells = <0>;
188		clock-frequency = <24000000>;
189		clock-output-names = "osc_24m";
190	};
191
192	clk_ext1: clock-ext1 {
193		compatible = "fixed-clock";
194		#clock-cells = <0>;
195		clock-frequency = <133000000>;
196		clock-output-names = "clk_ext1";
197	};
198
199	clk_ext2: clock-ext2 {
200		compatible = "fixed-clock";
201		#clock-cells = <0>;
202		clock-frequency = <133000000>;
203		clock-output-names = "clk_ext2";
204	};
205
206	clk_ext3: clock-ext3 {
207		compatible = "fixed-clock";
208		#clock-cells = <0>;
209		clock-frequency = <133000000>;
210		clock-output-names = "clk_ext3";
211	};
212
213	clk_ext4: clock-ext4 {
214		compatible = "fixed-clock";
215		#clock-cells = <0>;
216		clock-frequency = <133000000>;
217		clock-output-names = "clk_ext4";
218	};
219
220	psci {
221		compatible = "arm,psci-1.0";
222		method = "smc";
223	};
224
225	pmu {
226		compatible = "arm,cortex-a53-pmu";
227		interrupts = <GIC_PPI 7
228			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
229	};
230
231	timer {
232		compatible = "arm,armv8-timer";
233		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
234			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
235			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
236			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
237		clock-frequency = <8000000>;
238		arm,no-tick-in-suspend;
239	};
240
241	thermal-zones {
242		cpu-thermal {
243			polling-delay-passive = <250>;
244			polling-delay = <2000>;
245			thermal-sensors = <&tmu>;
246			trips {
247				cpu_alert0: trip0 {
248					temperature = <85000>;
249					hysteresis = <2000>;
250					type = "passive";
251				};
252
253				cpu_crit0: trip1 {
254					temperature = <95000>;
255					hysteresis = <2000>;
256					type = "critical";
257				};
258			};
259
260			cooling-maps {
261				map0 {
262					trip = <&cpu_alert0>;
263					cooling-device =
264						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
265						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
266						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
267						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
268				};
269			};
270		};
271	};
272
273	usbphynop1: usbphynop1 {
274		#phy-cells = <0>;
275		compatible = "usb-nop-xceiv";
276		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
277		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
278		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
279		clock-names = "main_clk";
280		power-domains = <&pgc_otg1>;
281	};
282
283	usbphynop2: usbphynop2 {
284		#phy-cells = <0>;
285		compatible = "usb-nop-xceiv";
286		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
287		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
288		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
289		clock-names = "main_clk";
290		power-domains = <&pgc_otg2>;
291	};
292
293	soc: soc@0 {
294		compatible = "fsl,imx8mm-soc", "simple-bus";
295		#address-cells = <1>;
296		#size-cells = <1>;
297		ranges = <0x0 0x0 0x0 0x3e000000>;
298		dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
299		nvmem-cells = <&imx8mm_uid>;
300		nvmem-cell-names = "soc_unique_id";
301
302		aips1: bus@30000000 {
303			compatible = "fsl,aips-bus", "simple-bus";
304			reg = <0x30000000 0x400000>;
305			#address-cells = <1>;
306			#size-cells = <1>;
307			ranges = <0x30000000 0x30000000 0x400000>;
308
309			spba2: spba-bus@30000000 {
310				compatible = "fsl,spba-bus", "simple-bus";
311				#address-cells = <1>;
312				#size-cells = <1>;
313				reg = <0x30000000 0x100000>;
314				ranges;
315
316				sai1: sai@30010000 {
317					#sound-dai-cells = <0>;
318					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
319					reg = <0x30010000 0x10000>;
320					interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
321					clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
322						 <&clk IMX8MM_CLK_SAI1_ROOT>,
323						 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
324					clock-names = "bus", "mclk1", "mclk2", "mclk3";
325					dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
326					dma-names = "rx", "tx";
327					status = "disabled";
328				};
329
330				sai2: sai@30020000 {
331					#sound-dai-cells = <0>;
332					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
333					reg = <0x30020000 0x10000>;
334					interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
335					clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
336						<&clk IMX8MM_CLK_SAI2_ROOT>,
337						<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
338					clock-names = "bus", "mclk1", "mclk2", "mclk3";
339					dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
340					dma-names = "rx", "tx";
341					status = "disabled";
342				};
343
344				sai3: sai@30030000 {
345					#sound-dai-cells = <0>;
346					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
347					reg = <0x30030000 0x10000>;
348					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
349					clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
350						 <&clk IMX8MM_CLK_SAI3_ROOT>,
351						 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
352					clock-names = "bus", "mclk1", "mclk2", "mclk3";
353					dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
354					dma-names = "rx", "tx";
355					status = "disabled";
356				};
357
358				sai5: sai@30050000 {
359					#sound-dai-cells = <0>;
360					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
361					reg = <0x30050000 0x10000>;
362					interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
363					clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
364						 <&clk IMX8MM_CLK_SAI5_ROOT>,
365						 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
366					clock-names = "bus", "mclk1", "mclk2", "mclk3";
367					dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
368					dma-names = "rx", "tx";
369					status = "disabled";
370				};
371
372				sai6: sai@30060000 {
373					#sound-dai-cells = <0>;
374					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
375					reg = <0x30060000 0x10000>;
376					interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
377					clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
378						 <&clk IMX8MM_CLK_SAI6_ROOT>,
379						 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
380					clock-names = "bus", "mclk1", "mclk2", "mclk3";
381					dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
382					dma-names = "rx", "tx";
383					status = "disabled";
384				};
385
386				micfil: audio-controller@30080000 {
387					compatible = "fsl,imx8mm-micfil";
388					reg = <0x30080000 0x10000>;
389					interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
390						     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
391						     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
392						     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
393					clocks = <&clk IMX8MM_CLK_PDM_IPG>,
394						 <&clk IMX8MM_CLK_PDM_ROOT>,
395						 <&clk IMX8MM_AUDIO_PLL1_OUT>,
396						 <&clk IMX8MM_AUDIO_PLL2_OUT>,
397						 <&clk IMX8MM_CLK_EXT3>;
398					clock-names = "ipg_clk", "ipg_clk_app",
399						      "pll8k", "pll11k", "clkext3";
400					dmas = <&sdma2 24 25 0x80000000>;
401					dma-names = "rx";
402					#sound-dai-cells = <0>;
403					status = "disabled";
404				};
405
406				spdif1: spdif@30090000 {
407					compatible = "fsl,imx35-spdif";
408					reg = <0x30090000 0x10000>;
409					interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
410					clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
411						 <&clk IMX8MM_CLK_24M>, /* rxtx0 */
412						 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
413						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
414						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
415						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
416						 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
417						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
418						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
419						 <&clk IMX8MM_CLK_DUMMY>; /* spba */
420					clock-names = "core", "rxtx0",
421						      "rxtx1", "rxtx2",
422						      "rxtx3", "rxtx4",
423						      "rxtx5", "rxtx6",
424						      "rxtx7", "spba";
425					dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
426					dma-names = "rx", "tx";
427					status = "disabled";
428				};
429			};
430
431			gpio1: gpio@30200000 {
432				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
433				reg = <0x30200000 0x10000>;
434				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
435					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
436				clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
437				gpio-controller;
438				#gpio-cells = <2>;
439				interrupt-controller;
440				#interrupt-cells = <2>;
441				gpio-ranges = <&iomuxc 0 10 30>;
442			};
443
444			gpio2: gpio@30210000 {
445				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
446				reg = <0x30210000 0x10000>;
447				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
448					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
449				clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
450				gpio-controller;
451				#gpio-cells = <2>;
452				interrupt-controller;
453				#interrupt-cells = <2>;
454				gpio-ranges = <&iomuxc 0 40 21>;
455			};
456
457			gpio3: gpio@30220000 {
458				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
459				reg = <0x30220000 0x10000>;
460				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
461					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
462				clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
463				gpio-controller;
464				#gpio-cells = <2>;
465				interrupt-controller;
466				#interrupt-cells = <2>;
467				gpio-ranges = <&iomuxc 0 61 26>;
468			};
469
470			gpio4: gpio@30230000 {
471				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
472				reg = <0x30230000 0x10000>;
473				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
474					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
475				clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
476				gpio-controller;
477				#gpio-cells = <2>;
478				interrupt-controller;
479				#interrupt-cells = <2>;
480				gpio-ranges = <&iomuxc 0 87 32>;
481			};
482
483			gpio5: gpio@30240000 {
484				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
485				reg = <0x30240000 0x10000>;
486				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
487					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
488				clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
489				gpio-controller;
490				#gpio-cells = <2>;
491				interrupt-controller;
492				#interrupt-cells = <2>;
493				gpio-ranges = <&iomuxc 0 119 30>;
494			};
495
496			tmu: tmu@30260000 {
497				compatible = "fsl,imx8mm-tmu";
498				reg = <0x30260000 0x10000>;
499				clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
500				nvmem-cells = <&tmu_calib>;
501				nvmem-cell-names = "calib";
502				#thermal-sensor-cells = <0>;
503			};
504
505			wdog1: watchdog@30280000 {
506				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
507				reg = <0x30280000 0x10000>;
508				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
509				clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
510				status = "disabled";
511			};
512
513			wdog2: watchdog@30290000 {
514				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
515				reg = <0x30290000 0x10000>;
516				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
517				clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
518				status = "disabled";
519			};
520
521			wdog3: watchdog@302a0000 {
522				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
523				reg = <0x302a0000 0x10000>;
524				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
525				clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
526				status = "disabled";
527			};
528
529			sdma2: dma-controller@302c0000 {
530				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
531				reg = <0x302c0000 0x10000>;
532				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
533				clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
534					 <&clk IMX8MM_CLK_SDMA2_ROOT>;
535				clock-names = "ipg", "ahb";
536				#dma-cells = <3>;
537				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
538			};
539
540			sdma3: dma-controller@302b0000 {
541				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
542				reg = <0x302b0000 0x10000>;
543				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
544				clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
545				 <&clk IMX8MM_CLK_SDMA3_ROOT>;
546				clock-names = "ipg", "ahb";
547				#dma-cells = <3>;
548				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
549			};
550
551			iomuxc: pinctrl@30330000 {
552				compatible = "fsl,imx8mm-iomuxc";
553				reg = <0x30330000 0x10000>;
554			};
555
556			gpr: syscon@30340000 {
557				compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
558				reg = <0x30340000 0x10000>;
559			};
560
561			ocotp: efuse@30350000 {
562				compatible = "fsl,imx8mm-ocotp", "syscon";
563				reg = <0x30350000 0x10000>;
564				clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
565				/* For nvmem subnodes */
566				#address-cells = <1>;
567				#size-cells = <1>;
568
569				/*
570				 * The register address below maps to the MX8M
571				 * Fusemap Description Table entries this way.
572				 * Assuming
573				 *   reg = <ADDR SIZE>;
574				 * then
575				 *   Fuse Address = (ADDR * 4) + 0x400
576				 * Note that if SIZE is greater than 4, then
577				 * each subsequent fuse is located at offset
578				 * +0x10 in Fusemap Description Table (e.g.
579				 * reg = <0x4 0x8> describes fuses 0x410 and
580				 * 0x420).
581				 */
582				imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
583					reg = <0x4 0x8>;
584				};
585
586				cpu_speed_grade: speed-grade@10 { /* 0x440 */
587					reg = <0x10 4>;
588				};
589
590				tmu_calib: calib@3c { /* 0x4f0 */
591					reg = <0x3c 4>;
592				};
593
594				fec_mac_address: mac-address@90 { /* 0x640 */
595					reg = <0x90 6>;
596				};
597			};
598
599			anatop: clock-controller@30360000 {
600				compatible = "fsl,imx8mm-anatop";
601				reg = <0x30360000 0x10000>;
602				#clock-cells = <1>;
603			};
604
605			snvs: snvs@30370000 {
606				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
607				reg = <0x30370000 0x10000>;
608
609				snvs_rtc: snvs-rtc-lp {
610					compatible = "fsl,sec-v4.0-mon-rtc-lp";
611					regmap = <&snvs>;
612					offset = <0x34>;
613					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
614						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
615					clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
616					clock-names = "snvs-rtc";
617				};
618
619				snvs_pwrkey: snvs-powerkey {
620					compatible = "fsl,sec-v4.0-pwrkey";
621					regmap = <&snvs>;
622					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
623					clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
624					clock-names = "snvs-pwrkey";
625					linux,keycode = <KEY_POWER>;
626					wakeup-source;
627					status = "disabled";
628				};
629
630				snvs_lpgpr: snvs-lpgpr {
631					compatible = "fsl,imx8mm-snvs-lpgpr",
632						     "fsl,imx7d-snvs-lpgpr";
633				};
634			};
635
636			clk: clock-controller@30380000 {
637				compatible = "fsl,imx8mm-ccm";
638				reg = <0x30380000 0x10000>;
639				#clock-cells = <1>;
640				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
641					 <&clk_ext3>, <&clk_ext4>;
642				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
643					      "clk_ext3", "clk_ext4";
644				assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
645						<&clk IMX8MM_CLK_A53_CORE>,
646						<&clk IMX8MM_CLK_NOC>,
647						<&clk IMX8MM_CLK_AUDIO_AHB>,
648						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
649						<&clk IMX8MM_SYS_PLL3>,
650						<&clk IMX8MM_VIDEO_PLL1>,
651						<&clk IMX8MM_AUDIO_PLL1>;
652				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
653							 <&clk IMX8MM_ARM_PLL_OUT>,
654							 <&clk IMX8MM_SYS_PLL3_OUT>,
655							 <&clk IMX8MM_SYS_PLL1_800M>;
656				assigned-clock-rates = <0>, <0>, <0>,
657							<400000000>,
658							<400000000>,
659							<750000000>,
660							<594000000>,
661							<393216000>;
662			};
663
664			src: reset-controller@30390000 {
665				compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
666				reg = <0x30390000 0x10000>;
667				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
668				#reset-cells = <1>;
669			};
670
671			gpc: gpc@303a0000 {
672				compatible = "fsl,imx8mm-gpc";
673				reg = <0x303a0000 0x10000>;
674				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
675				interrupt-parent = <&gic>;
676				interrupt-controller;
677				#interrupt-cells = <3>;
678
679				pgc {
680					#address-cells = <1>;
681					#size-cells = <0>;
682
683					pgc_hsiomix: power-domain@0 {
684						#power-domain-cells = <0>;
685						reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
686						clocks = <&clk IMX8MM_CLK_USB_BUS>;
687						assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
688						assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
689					};
690
691					pgc_pcie: power-domain@1 {
692						#power-domain-cells = <0>;
693						reg = <IMX8MM_POWER_DOMAIN_PCIE>;
694						power-domains = <&pgc_hsiomix>;
695						clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
696					};
697
698					pgc_otg1: power-domain@2 {
699						#power-domain-cells = <0>;
700						reg = <IMX8MM_POWER_DOMAIN_OTG1>;
701					};
702
703					pgc_otg2: power-domain@3 {
704						#power-domain-cells = <0>;
705						reg = <IMX8MM_POWER_DOMAIN_OTG2>;
706					};
707
708					pgc_gpumix: power-domain@4 {
709						#power-domain-cells = <0>;
710						reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
711						clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
712							 <&clk IMX8MM_CLK_GPU_AHB>;
713						assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
714								  <&clk IMX8MM_CLK_GPU_AHB>;
715						assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
716									 <&clk IMX8MM_SYS_PLL1_800M>;
717						assigned-clock-rates = <800000000>, <400000000>;
718					};
719
720					pgc_gpu: power-domain@5 {
721						#power-domain-cells = <0>;
722						reg = <IMX8MM_POWER_DOMAIN_GPU>;
723						clocks = <&clk IMX8MM_CLK_GPU_AHB>,
724							 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
725							 <&clk IMX8MM_CLK_GPU2D_ROOT>,
726							 <&clk IMX8MM_CLK_GPU3D_ROOT>;
727						resets = <&src IMX8MQ_RESET_GPU_RESET>;
728						power-domains = <&pgc_gpumix>;
729					};
730
731					pgc_vpumix: power-domain@6 {
732						#power-domain-cells = <0>;
733						reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
734						clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
735						assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
736						assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
737					};
738
739					pgc_vpu_g1: power-domain@7 {
740						#power-domain-cells = <0>;
741						reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
742					};
743
744					pgc_vpu_g2: power-domain@8 {
745						#power-domain-cells = <0>;
746						reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
747					};
748
749					pgc_vpu_h1: power-domain@9 {
750						#power-domain-cells = <0>;
751						reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
752					};
753
754					pgc_dispmix: power-domain@10 {
755						#power-domain-cells = <0>;
756						reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
757						clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
758							 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
759						assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
760								  <&clk IMX8MM_CLK_DISP_APB>;
761						assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
762									 <&clk IMX8MM_SYS_PLL1_800M>;
763						assigned-clock-rates = <500000000>, <200000000>;
764					};
765
766					pgc_mipi: power-domain@11 {
767						#power-domain-cells = <0>;
768						reg = <IMX8MM_POWER_DOMAIN_MIPI>;
769					};
770				};
771			};
772		};
773
774		aips2: bus@30400000 {
775			compatible = "fsl,aips-bus", "simple-bus";
776			reg = <0x30400000 0x400000>;
777			#address-cells = <1>;
778			#size-cells = <1>;
779			ranges = <0x30400000 0x30400000 0x400000>;
780
781			pwm1: pwm@30660000 {
782				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
783				reg = <0x30660000 0x10000>;
784				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
785				clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
786					<&clk IMX8MM_CLK_PWM1_ROOT>;
787				clock-names = "ipg", "per";
788				#pwm-cells = <3>;
789				status = "disabled";
790			};
791
792			pwm2: pwm@30670000 {
793				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
794				reg = <0x30670000 0x10000>;
795				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
796				clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
797					 <&clk IMX8MM_CLK_PWM2_ROOT>;
798				clock-names = "ipg", "per";
799				#pwm-cells = <3>;
800				status = "disabled";
801			};
802
803			pwm3: pwm@30680000 {
804				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
805				reg = <0x30680000 0x10000>;
806				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
807				clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
808					 <&clk IMX8MM_CLK_PWM3_ROOT>;
809				clock-names = "ipg", "per";
810				#pwm-cells = <3>;
811				status = "disabled";
812			};
813
814			pwm4: pwm@30690000 {
815				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
816				reg = <0x30690000 0x10000>;
817				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
818				clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
819					 <&clk IMX8MM_CLK_PWM4_ROOT>;
820				clock-names = "ipg", "per";
821				#pwm-cells = <3>;
822				status = "disabled";
823			};
824
825			system_counter: timer@306a0000 {
826				compatible = "nxp,sysctr-timer";
827				reg = <0x306a0000 0x20000>;
828				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
829				clocks = <&osc_24m>;
830				clock-names = "per";
831			};
832		};
833
834		aips3: bus@30800000 {
835			compatible = "fsl,aips-bus", "simple-bus";
836			reg = <0x30800000 0x400000>;
837			#address-cells = <1>;
838			#size-cells = <1>;
839			ranges = <0x30800000 0x30800000 0x400000>,
840				 <0x8000000 0x8000000 0x10000000>;
841
842			spba1: spba-bus@30800000 {
843				compatible = "fsl,spba-bus", "simple-bus";
844				#address-cells = <1>;
845				#size-cells = <1>;
846				reg = <0x30800000 0x100000>;
847				ranges;
848
849				ecspi1: spi@30820000 {
850					compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
851					#address-cells = <1>;
852					#size-cells = <0>;
853					reg = <0x30820000 0x10000>;
854					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
855					clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
856						 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
857					clock-names = "ipg", "per";
858					dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
859					dma-names = "rx", "tx";
860					status = "disabled";
861				};
862
863				ecspi2: spi@30830000 {
864					compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
865					#address-cells = <1>;
866					#size-cells = <0>;
867					reg = <0x30830000 0x10000>;
868					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
869					clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
870						 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
871					clock-names = "ipg", "per";
872					dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
873					dma-names = "rx", "tx";
874					status = "disabled";
875				};
876
877				ecspi3: spi@30840000 {
878					compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
879					#address-cells = <1>;
880					#size-cells = <0>;
881					reg = <0x30840000 0x10000>;
882					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
883					clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
884						 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
885					clock-names = "ipg", "per";
886					dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
887					dma-names = "rx", "tx";
888					status = "disabled";
889				};
890
891				uart1: serial@30860000 {
892					compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
893					reg = <0x30860000 0x10000>;
894					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
895					clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
896						 <&clk IMX8MM_CLK_UART1_ROOT>;
897					clock-names = "ipg", "per";
898					dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
899					dma-names = "rx", "tx";
900					status = "disabled";
901				};
902
903				uart3: serial@30880000 {
904					compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
905					reg = <0x30880000 0x10000>;
906					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
907					clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
908						 <&clk IMX8MM_CLK_UART3_ROOT>;
909					clock-names = "ipg", "per";
910					dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
911					dma-names = "rx", "tx";
912					status = "disabled";
913				};
914
915				uart2: serial@30890000 {
916					compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
917					reg = <0x30890000 0x10000>;
918					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
919					clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
920						 <&clk IMX8MM_CLK_UART2_ROOT>;
921					clock-names = "ipg", "per";
922					status = "disabled";
923				};
924			};
925
926			crypto: crypto@30900000 {
927				compatible = "fsl,sec-v4.0";
928				#address-cells = <1>;
929				#size-cells = <1>;
930				reg = <0x30900000 0x40000>;
931				ranges = <0 0x30900000 0x40000>;
932				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
933				clocks = <&clk IMX8MM_CLK_AHB>,
934					 <&clk IMX8MM_CLK_IPG_ROOT>;
935				clock-names = "aclk", "ipg";
936
937				sec_jr0: jr@1000 {
938					compatible = "fsl,sec-v4.0-job-ring";
939					reg = <0x1000 0x1000>;
940					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
941					status = "disabled";
942				};
943
944				sec_jr1: jr@2000 {
945					compatible = "fsl,sec-v4.0-job-ring";
946					reg = <0x2000 0x1000>;
947					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
948				};
949
950				sec_jr2: jr@3000 {
951					compatible = "fsl,sec-v4.0-job-ring";
952					reg = <0x3000 0x1000>;
953					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
954				};
955			};
956
957			i2c1: i2c@30a20000 {
958				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
959				#address-cells = <1>;
960				#size-cells = <0>;
961				reg = <0x30a20000 0x10000>;
962				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
963				clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
964				status = "disabled";
965			};
966
967			i2c2: i2c@30a30000 {
968				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
969				#address-cells = <1>;
970				#size-cells = <0>;
971				reg = <0x30a30000 0x10000>;
972				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
973				clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
974				status = "disabled";
975			};
976
977			i2c3: i2c@30a40000 {
978				#address-cells = <1>;
979				#size-cells = <0>;
980				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
981				reg = <0x30a40000 0x10000>;
982				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
983				clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
984				status = "disabled";
985			};
986
987			i2c4: i2c@30a50000 {
988				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
989				#address-cells = <1>;
990				#size-cells = <0>;
991				reg = <0x30a50000 0x10000>;
992				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
993				clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
994				status = "disabled";
995			};
996
997			uart4: serial@30a60000 {
998				compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
999				reg = <0x30a60000 0x10000>;
1000				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1001				clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
1002					 <&clk IMX8MM_CLK_UART4_ROOT>;
1003				clock-names = "ipg", "per";
1004				dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1005				dma-names = "rx", "tx";
1006				status = "disabled";
1007			};
1008
1009			mu: mailbox@30aa0000 {
1010				compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
1011				reg = <0x30aa0000 0x10000>;
1012				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1013				clocks = <&clk IMX8MM_CLK_MU_ROOT>;
1014				#mbox-cells = <2>;
1015			};
1016
1017			usdhc1: mmc@30b40000 {
1018				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1019				reg = <0x30b40000 0x10000>;
1020				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1021				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1022					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1023					 <&clk IMX8MM_CLK_USDHC1_ROOT>;
1024				clock-names = "ipg", "ahb", "per";
1025				fsl,tuning-start-tap = <20>;
1026				fsl,tuning-step = <2>;
1027				bus-width = <4>;
1028				status = "disabled";
1029			};
1030
1031			usdhc2: mmc@30b50000 {
1032				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1033				reg = <0x30b50000 0x10000>;
1034				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1035				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1036					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1037					 <&clk IMX8MM_CLK_USDHC2_ROOT>;
1038				clock-names = "ipg", "ahb", "per";
1039				fsl,tuning-start-tap = <20>;
1040				fsl,tuning-step = <2>;
1041				bus-width = <4>;
1042				status = "disabled";
1043			};
1044
1045			usdhc3: mmc@30b60000 {
1046				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1047				reg = <0x30b60000 0x10000>;
1048				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1049				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1050					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1051					 <&clk IMX8MM_CLK_USDHC3_ROOT>;
1052				clock-names = "ipg", "ahb", "per";
1053				fsl,tuning-start-tap = <20>;
1054				fsl,tuning-step = <2>;
1055				bus-width = <4>;
1056				status = "disabled";
1057			};
1058
1059			flexspi: spi@30bb0000 {
1060				#address-cells = <1>;
1061				#size-cells = <0>;
1062				compatible = "nxp,imx8mm-fspi";
1063				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1064				reg-names = "fspi_base", "fspi_mmap";
1065				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1066				clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
1067					 <&clk IMX8MM_CLK_QSPI_ROOT>;
1068				clock-names = "fspi_en", "fspi";
1069				status = "disabled";
1070			};
1071
1072			sdma1: dma-controller@30bd0000 {
1073				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
1074				reg = <0x30bd0000 0x10000>;
1075				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1076				clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
1077					 <&clk IMX8MM_CLK_AHB>;
1078				clock-names = "ipg", "ahb";
1079				#dma-cells = <3>;
1080				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1081			};
1082
1083			fec1: ethernet@30be0000 {
1084				compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1085				reg = <0x30be0000 0x10000>;
1086				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1087					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1088					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1089					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1090				clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
1091					 <&clk IMX8MM_CLK_ENET1_ROOT>,
1092					 <&clk IMX8MM_CLK_ENET_TIMER>,
1093					 <&clk IMX8MM_CLK_ENET_REF>,
1094					 <&clk IMX8MM_CLK_ENET_PHY_REF>;
1095				clock-names = "ipg", "ahb", "ptp",
1096					      "enet_clk_ref", "enet_out";
1097				assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
1098						  <&clk IMX8MM_CLK_ENET_TIMER>,
1099						  <&clk IMX8MM_CLK_ENET_REF>,
1100						  <&clk IMX8MM_CLK_ENET_PHY_REF>;
1101				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1102							 <&clk IMX8MM_SYS_PLL2_100M>,
1103							 <&clk IMX8MM_SYS_PLL2_125M>,
1104							 <&clk IMX8MM_SYS_PLL2_50M>;
1105				assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1106				fsl,num-tx-queues = <3>;
1107				fsl,num-rx-queues = <3>;
1108				nvmem-cells = <&fec_mac_address>;
1109				nvmem-cell-names = "mac-address";
1110				fsl,stop-mode = <&gpr 0x10 3>;
1111				status = "disabled";
1112			};
1113
1114		};
1115
1116		aips4: bus@32c00000 {
1117			compatible = "fsl,aips-bus", "simple-bus";
1118			reg = <0x32c00000 0x400000>;
1119			#address-cells = <1>;
1120			#size-cells = <1>;
1121			ranges = <0x32c00000 0x32c00000 0x400000>;
1122
1123			lcdif: lcdif@32e00000 {
1124				compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
1125				reg = <0x32e00000 0x10000>;
1126				clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
1127					 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1128					 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
1129				clock-names = "pix", "axi", "disp_axi";
1130				assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
1131						  <&clk IMX8MM_CLK_DISP_AXI>,
1132						  <&clk IMX8MM_CLK_DISP_APB>;
1133				assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
1134							 <&clk IMX8MM_SYS_PLL2_1000M>,
1135							 <&clk IMX8MM_SYS_PLL1_800M>;
1136				assigned-clock-rates = <594000000>, <500000000>, <200000000>;
1137				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1138				power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
1139				status = "disabled";
1140
1141				port {
1142					lcdif_to_dsim: endpoint {
1143						remote-endpoint = <&dsim_from_lcdif>;
1144					};
1145				};
1146			};
1147
1148			mipi_dsi: dsi@32e10000 {
1149				compatible = "fsl,imx8mm-mipi-dsim";
1150				reg = <0x32e10000 0x400>;
1151				clocks = <&clk IMX8MM_CLK_DSI_CORE>,
1152					 <&clk IMX8MM_CLK_DSI_PHY_REF>;
1153				clock-names = "bus_clk", "sclk_mipi";
1154				assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
1155						  <&clk IMX8MM_CLK_DSI_PHY_REF>;
1156				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1157							 <&clk IMX8MM_CLK_24M>;
1158				assigned-clock-rates = <266000000>, <24000000>;
1159				samsung,pll-clock-frequency = <24000000>;
1160				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1161				power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
1162				status = "disabled";
1163
1164				ports {
1165					#address-cells = <1>;
1166					#size-cells = <0>;
1167
1168					port@0 {
1169						reg = <0>;
1170
1171						dsim_from_lcdif: endpoint {
1172							remote-endpoint = <&lcdif_to_dsim>;
1173						};
1174					};
1175				};
1176			};
1177
1178			csi: csi@32e20000 {
1179				compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
1180				reg = <0x32e20000 0x1000>;
1181				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1182				clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
1183				clock-names = "mclk";
1184				power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
1185				status = "disabled";
1186
1187				port {
1188					csi_in: endpoint {
1189						remote-endpoint = <&imx8mm_mipi_csi_out>;
1190					};
1191				};
1192			};
1193
1194			disp_blk_ctrl: blk-ctrl@32e28000 {
1195				compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
1196				reg = <0x32e28000 0x100>;
1197				power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1198						<&pgc_dispmix>, <&pgc_mipi>,
1199						<&pgc_mipi>;
1200				power-domain-names = "bus", "csi-bridge",
1201						     "lcdif", "mipi-dsi",
1202						     "mipi-csi";
1203				clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
1204					 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1205					 <&clk IMX8MM_CLK_CSI1_ROOT>,
1206					 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
1207					 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1208					 <&clk IMX8MM_CLK_DISP_ROOT>,
1209					 <&clk IMX8MM_CLK_DSI_CORE>,
1210					 <&clk IMX8MM_CLK_DSI_PHY_REF>,
1211					 <&clk IMX8MM_CLK_CSI1_CORE>,
1212					 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
1213				clock-names = "csi-bridge-axi","csi-bridge-apb",
1214					      "csi-bridge-core", "lcdif-axi",
1215					      "lcdif-apb", "lcdif-pix",
1216					      "dsi-pclk", "dsi-ref",
1217					      "csi-aclk", "csi-pclk";
1218				#power-domain-cells = <1>;
1219			};
1220
1221			mipi_csi: mipi-csi@32e30000 {
1222				compatible = "fsl,imx8mm-mipi-csi2";
1223				reg = <0x32e30000 0x1000>;
1224				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1225				assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;
1226				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;
1227
1228				clock-frequency = <333000000>;
1229				clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1230					 <&clk IMX8MM_CLK_CSI1_ROOT>,
1231					 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
1232					 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
1233				clock-names = "pclk", "wrap", "phy", "axi";
1234				power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
1235				status = "disabled";
1236
1237				ports {
1238					#address-cells = <1>;
1239					#size-cells = <0>;
1240
1241					port@0 {
1242						reg = <0>;
1243					};
1244
1245					port@1 {
1246						reg = <1>;
1247
1248						imx8mm_mipi_csi_out: endpoint {
1249							remote-endpoint = <&csi_in>;
1250						};
1251					};
1252				};
1253			};
1254
1255			usbotg1: usb@32e40000 {
1256				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1257				reg = <0x32e40000 0x200>;
1258				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1259				clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
1260				clock-names = "usb1_ctrl_root_clk";
1261				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1262				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1263				phys = <&usbphynop1>;
1264				fsl,usbmisc = <&usbmisc1 0>;
1265				power-domains = <&pgc_hsiomix>;
1266				status = "disabled";
1267			};
1268
1269			usbmisc1: usbmisc@32e40200 {
1270				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
1271					     "fsl,imx6q-usbmisc";
1272				#index-cells = <1>;
1273				reg = <0x32e40200 0x200>;
1274			};
1275
1276			usbotg2: usb@32e50000 {
1277				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1278				reg = <0x32e50000 0x200>;
1279				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1280				clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
1281				clock-names = "usb1_ctrl_root_clk";
1282				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1283				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1284				phys = <&usbphynop2>;
1285				fsl,usbmisc = <&usbmisc2 0>;
1286				power-domains = <&pgc_hsiomix>;
1287				status = "disabled";
1288			};
1289
1290			usbmisc2: usbmisc@32e50200 {
1291				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
1292					     "fsl,imx6q-usbmisc";
1293				#index-cells = <1>;
1294				reg = <0x32e50200 0x200>;
1295			};
1296
1297			pcie_phy: pcie-phy@32f00000 {
1298				compatible = "fsl,imx8mm-pcie-phy";
1299				reg = <0x32f00000 0x10000>;
1300				clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1301				clock-names = "ref";
1302				assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1303				assigned-clock-rates = <100000000>;
1304				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
1305				resets = <&src IMX8MQ_RESET_PCIEPHY>;
1306				reset-names = "pciephy";
1307				#phy-cells = <0>;
1308				status = "disabled";
1309			};
1310		};
1311
1312		dma_apbh: dma-controller@33000000 {
1313			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1314			reg = <0x33000000 0x2000>;
1315			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1316				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1317				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1318				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1319			#dma-cells = <1>;
1320			dma-channels = <4>;
1321			clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1322		};
1323
1324		gpmi: nand-controller@33002000 {
1325			compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1326			#address-cells = <1>;
1327			#size-cells = <0>;
1328			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1329			reg-names = "gpmi-nand", "bch";
1330			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1331			interrupt-names = "bch";
1332			clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
1333				 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1334			clock-names = "gpmi_io", "gpmi_bch_apb";
1335			dmas = <&dma_apbh 0>;
1336			dma-names = "rx-tx";
1337			status = "disabled";
1338		};
1339
1340		pcie0: pcie@33800000 {
1341			compatible = "fsl,imx8mm-pcie";
1342			reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1343			reg-names = "dbi", "config";
1344			#address-cells = <3>;
1345			#size-cells = <2>;
1346			device_type = "pci";
1347			bus-range = <0x00 0xff>;
1348			ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1349				 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1350			num-lanes = <1>;
1351			num-viewport = <4>;
1352			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1353			interrupt-names = "msi";
1354			#interrupt-cells = <1>;
1355			interrupt-map-mask = <0 0 0 0x7>;
1356			interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1357					<0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1358					<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1359					<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1360			fsl,max-link-speed = <2>;
1361			linux,pci-domain = <0>;
1362			clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
1363				 <&clk IMX8MM_CLK_PCIE1_PHY>,
1364				 <&clk IMX8MM_CLK_PCIE1_AUX>;
1365			clock-names = "pcie", "pcie_bus", "pcie_aux";
1366			power-domains = <&pgc_pcie>;
1367			resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1368				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1369			reset-names = "apps", "turnoff";
1370			phys = <&pcie_phy>;
1371			phy-names = "pcie-phy";
1372			status = "disabled";
1373		};
1374
1375		pcie0_ep: pcie-ep@33800000 {
1376			compatible = "fsl,imx8mm-pcie-ep";
1377			reg = <0x33800000 0x400000>,
1378			      <0x18000000 0x8000000>;
1379			reg-names = "dbi", "addr_space";
1380			num-lanes = <1>;
1381			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1382			interrupt-names = "dma";
1383			fsl,max-link-speed = <2>;
1384			clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
1385				 <&clk IMX8MM_CLK_PCIE1_PHY>,
1386				 <&clk IMX8MM_CLK_PCIE1_AUX>;
1387			clock-names = "pcie", "pcie_bus", "pcie_aux";
1388			power-domains = <&pgc_pcie>;
1389			resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1390				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1391			reset-names = "apps", "turnoff";
1392			phys = <&pcie_phy>;
1393			phy-names = "pcie-phy";
1394			num-ib-windows = <4>;
1395			num-ob-windows = <4>;
1396			status = "disabled";
1397		};
1398
1399		gpu_3d: gpu@38000000 {
1400			compatible = "vivante,gc";
1401			reg = <0x38000000 0x8000>;
1402			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1403			clocks = <&clk IMX8MM_CLK_GPU_AHB>,
1404				 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
1405				 <&clk IMX8MM_CLK_GPU3D_ROOT>,
1406				 <&clk IMX8MM_CLK_GPU3D_ROOT>;
1407			clock-names = "reg", "bus", "core", "shader";
1408			assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
1409					  <&clk IMX8MM_GPU_PLL_OUT>;
1410			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1411			assigned-clock-rates = <0>, <1000000000>;
1412			power-domains = <&pgc_gpu>;
1413		};
1414
1415		gpu_2d: gpu@38008000 {
1416			compatible = "vivante,gc";
1417			reg = <0x38008000 0x8000>;
1418			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1419			clocks = <&clk IMX8MM_CLK_GPU_AHB>,
1420				 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
1421				 <&clk IMX8MM_CLK_GPU2D_ROOT>;
1422			clock-names = "reg", "bus", "core";
1423			assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
1424					  <&clk IMX8MM_GPU_PLL_OUT>;
1425			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1426			assigned-clock-rates = <0>, <1000000000>;
1427			power-domains = <&pgc_gpu>;
1428		};
1429
1430		vpu_g1: video-codec@38300000 {
1431			compatible = "nxp,imx8mm-vpu-g1";
1432			reg = <0x38300000 0x10000>;
1433			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1434			clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
1435			power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
1436		};
1437
1438		vpu_g2: video-codec@38310000 {
1439			compatible = "nxp,imx8mq-vpu-g2";
1440			reg = <0x38310000 0x10000>;
1441			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1442			clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
1443			power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
1444		};
1445
1446		vpu_blk_ctrl: blk-ctrl@38330000 {
1447			compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
1448			reg = <0x38330000 0x100>;
1449			power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1450					<&pgc_vpu_g2>, <&pgc_vpu_h1>;
1451			power-domain-names = "bus", "g1", "g2", "h1";
1452			clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
1453				 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
1454				 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
1455			clock-names = "g1", "g2", "h1";
1456			assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
1457					  <&clk IMX8MM_CLK_VPU_G2>;
1458			assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
1459						 <&clk IMX8MM_VPU_PLL_OUT>;
1460			assigned-clock-rates = <600000000>,
1461					       <600000000>;
1462			#power-domain-cells = <1>;
1463		};
1464
1465		gic: interrupt-controller@38800000 {
1466			compatible = "arm,gic-v3";
1467			reg = <0x38800000 0x10000>, /* GIC Dist */
1468			      <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
1469			#interrupt-cells = <3>;
1470			interrupt-controller;
1471			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1472		};
1473
1474		ddrc: memory-controller@3d400000 {
1475			compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1476			reg = <0x3d400000 0x400000>;
1477			clock-names = "core", "pll", "alt", "apb";
1478			clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
1479				 <&clk IMX8MM_DRAM_PLL>,
1480				 <&clk IMX8MM_CLK_DRAM_ALT>,
1481				 <&clk IMX8MM_CLK_DRAM_APB>;
1482		};
1483
1484		ddr-pmu@3d800000 {
1485			compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
1486			reg = <0x3d800000 0x400000>;
1487			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1488		};
1489	};
1490};
1491