1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mm-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8mm-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec1; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 i2c0 = &i2c1; 27 i2c1 = &i2c2; 28 i2c2 = &i2c3; 29 i2c3 = &i2c4; 30 mmc0 = &usdhc1; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc3; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 serial3 = &uart4; 37 spi0 = &ecspi1; 38 spi1 = &ecspi2; 39 spi2 = &ecspi3; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 idle-states { 47 entry-method = "psci"; 48 49 cpu_pd_wait: cpu-pd-wait { 50 compatible = "arm,idle-state"; 51 arm,psci-suspend-param = <0x0010033>; 52 local-timer-stop; 53 entry-latency-us = <1000>; 54 exit-latency-us = <700>; 55 min-residency-us = <2700>; 56 }; 57 }; 58 59 A53_0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0>; 63 clock-latency = <61036>; /* two CLK32 periods */ 64 clocks = <&clk IMX8MM_CLK_ARM>; 65 enable-method = "psci"; 66 next-level-cache = <&A53_L2>; 67 operating-points-v2 = <&a53_opp_table>; 68 nvmem-cells = <&cpu_speed_grade>; 69 nvmem-cell-names = "speed_grade"; 70 cpu-idle-states = <&cpu_pd_wait>; 71 #cooling-cells = <2>; 72 }; 73 74 A53_1: cpu@1 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x1>; 78 clock-latency = <61036>; /* two CLK32 periods */ 79 clocks = <&clk IMX8MM_CLK_ARM>; 80 enable-method = "psci"; 81 next-level-cache = <&A53_L2>; 82 operating-points-v2 = <&a53_opp_table>; 83 cpu-idle-states = <&cpu_pd_wait>; 84 #cooling-cells = <2>; 85 }; 86 87 A53_2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x2>; 91 clock-latency = <61036>; /* two CLK32 periods */ 92 clocks = <&clk IMX8MM_CLK_ARM>; 93 enable-method = "psci"; 94 next-level-cache = <&A53_L2>; 95 operating-points-v2 = <&a53_opp_table>; 96 cpu-idle-states = <&cpu_pd_wait>; 97 #cooling-cells = <2>; 98 }; 99 100 A53_3: cpu@3 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x3>; 104 clock-latency = <61036>; /* two CLK32 periods */ 105 clocks = <&clk IMX8MM_CLK_ARM>; 106 enable-method = "psci"; 107 next-level-cache = <&A53_L2>; 108 operating-points-v2 = <&a53_opp_table>; 109 cpu-idle-states = <&cpu_pd_wait>; 110 #cooling-cells = <2>; 111 }; 112 113 A53_L2: l2-cache0 { 114 compatible = "cache"; 115 }; 116 }; 117 118 a53_opp_table: opp-table { 119 compatible = "operating-points-v2"; 120 opp-shared; 121 122 opp-1200000000 { 123 opp-hz = /bits/ 64 <1200000000>; 124 opp-microvolt = <850000>; 125 opp-supported-hw = <0xe>, <0x7>; 126 clock-latency-ns = <150000>; 127 opp-suspend; 128 }; 129 130 opp-1600000000 { 131 opp-hz = /bits/ 64 <1600000000>; 132 opp-microvolt = <950000>; 133 opp-supported-hw = <0xc>, <0x7>; 134 clock-latency-ns = <150000>; 135 opp-suspend; 136 }; 137 138 opp-1800000000 { 139 opp-hz = /bits/ 64 <1800000000>; 140 opp-microvolt = <1000000>; 141 opp-supported-hw = <0x8>, <0x3>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 }; 146 147 osc_32k: clock-osc-32k { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <32768>; 151 clock-output-names = "osc_32k"; 152 }; 153 154 osc_24m: clock-osc-24m { 155 compatible = "fixed-clock"; 156 #clock-cells = <0>; 157 clock-frequency = <24000000>; 158 clock-output-names = "osc_24m"; 159 }; 160 161 clk_ext1: clock-ext1 { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <133000000>; 165 clock-output-names = "clk_ext1"; 166 }; 167 168 clk_ext2: clock-ext2 { 169 compatible = "fixed-clock"; 170 #clock-cells = <0>; 171 clock-frequency = <133000000>; 172 clock-output-names = "clk_ext2"; 173 }; 174 175 clk_ext3: clock-ext3 { 176 compatible = "fixed-clock"; 177 #clock-cells = <0>; 178 clock-frequency = <133000000>; 179 clock-output-names = "clk_ext3"; 180 }; 181 182 clk_ext4: clock-ext4 { 183 compatible = "fixed-clock"; 184 #clock-cells = <0>; 185 clock-frequency= <133000000>; 186 clock-output-names = "clk_ext4"; 187 }; 188 189 psci { 190 compatible = "arm,psci-1.0"; 191 method = "smc"; 192 }; 193 194 pmu { 195 compatible = "arm,cortex-a53-pmu"; 196 interrupts = <GIC_PPI 7 197 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 198 }; 199 200 timer { 201 compatible = "arm,armv8-timer"; 202 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 203 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 204 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 205 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 206 clock-frequency = <8000000>; 207 arm,no-tick-in-suspend; 208 }; 209 210 thermal-zones { 211 cpu-thermal { 212 polling-delay-passive = <250>; 213 polling-delay = <2000>; 214 thermal-sensors = <&tmu>; 215 trips { 216 cpu_alert0: trip0 { 217 temperature = <85000>; 218 hysteresis = <2000>; 219 type = "passive"; 220 }; 221 222 cpu_crit0: trip1 { 223 temperature = <95000>; 224 hysteresis = <2000>; 225 type = "critical"; 226 }; 227 }; 228 229 cooling-maps { 230 map0 { 231 trip = <&cpu_alert0>; 232 cooling-device = 233 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 234 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 235 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 236 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 237 }; 238 }; 239 }; 240 }; 241 242 usbphynop1: usbphynop1 { 243 #phy-cells = <0>; 244 compatible = "usb-nop-xceiv"; 245 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 246 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 247 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 248 clock-names = "main_clk"; 249 }; 250 251 usbphynop2: usbphynop2 { 252 #phy-cells = <0>; 253 compatible = "usb-nop-xceiv"; 254 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 255 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 256 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 257 clock-names = "main_clk"; 258 }; 259 260 soc@0 { 261 compatible = "fsl,imx8mm-soc", "simple-bus"; 262 #address-cells = <1>; 263 #size-cells = <1>; 264 ranges = <0x0 0x0 0x0 0x3e000000>; 265 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 266 nvmem-cells = <&imx8mm_uid>; 267 nvmem-cell-names = "soc_unique_id"; 268 269 aips1: bus@30000000 { 270 compatible = "fsl,aips-bus", "simple-bus"; 271 reg = <0x30000000 0x400000>; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 ranges = <0x30000000 0x30000000 0x400000>; 275 276 spba2: spba-bus@30000000 { 277 compatible = "fsl,spba-bus", "simple-bus"; 278 #address-cells = <1>; 279 #size-cells = <1>; 280 reg = <0x30000000 0x100000>; 281 ranges; 282 283 sai1: sai@30010000 { 284 #sound-dai-cells = <0>; 285 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 286 reg = <0x30010000 0x10000>; 287 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 289 <&clk IMX8MM_CLK_SAI1_ROOT>, 290 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 291 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 292 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 293 dma-names = "rx", "tx"; 294 status = "disabled"; 295 }; 296 297 sai2: sai@30020000 { 298 #sound-dai-cells = <0>; 299 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 300 reg = <0x30020000 0x10000>; 301 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&clk IMX8MM_CLK_SAI2_IPG>, 303 <&clk IMX8MM_CLK_SAI2_ROOT>, 304 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 305 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 306 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 307 dma-names = "rx", "tx"; 308 status = "disabled"; 309 }; 310 311 sai3: sai@30030000 { 312 #sound-dai-cells = <0>; 313 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 314 reg = <0x30030000 0x10000>; 315 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, 317 <&clk IMX8MM_CLK_SAI3_ROOT>, 318 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 319 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 320 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 321 dma-names = "rx", "tx"; 322 status = "disabled"; 323 }; 324 325 sai5: sai@30050000 { 326 #sound-dai-cells = <0>; 327 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 328 reg = <0x30050000 0x10000>; 329 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&clk IMX8MM_CLK_SAI5_IPG>, 331 <&clk IMX8MM_CLK_SAI5_ROOT>, 332 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 333 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 334 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 335 dma-names = "rx", "tx"; 336 status = "disabled"; 337 }; 338 339 sai6: sai@30060000 { 340 #sound-dai-cells = <0>; 341 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 342 reg = <0x30060000 0x10000>; 343 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&clk IMX8MM_CLK_SAI6_IPG>, 345 <&clk IMX8MM_CLK_SAI6_ROOT>, 346 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 347 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 348 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 349 dma-names = "rx", "tx"; 350 status = "disabled"; 351 }; 352 353 micfil: audio-controller@30080000 { 354 compatible = "fsl,imx8mm-micfil"; 355 reg = <0x30080000 0x10000>; 356 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&clk IMX8MM_CLK_PDM_IPG>, 361 <&clk IMX8MM_CLK_PDM_ROOT>, 362 <&clk IMX8MM_AUDIO_PLL1_OUT>, 363 <&clk IMX8MM_AUDIO_PLL2_OUT>, 364 <&clk IMX8MM_CLK_EXT3>; 365 clock-names = "ipg_clk", "ipg_clk_app", 366 "pll8k", "pll11k", "clkext3"; 367 dmas = <&sdma2 24 25 0x80000000>; 368 dma-names = "rx"; 369 status = "disabled"; 370 }; 371 372 spdif1: spdif@30090000 { 373 compatible = "fsl,imx35-spdif"; 374 reg = <0x30090000 0x10000>; 375 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ 377 <&clk IMX8MM_CLK_24M>, /* rxtx0 */ 378 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ 379 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ 380 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ 381 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ 382 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ 383 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ 384 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ 385 <&clk IMX8MM_CLK_DUMMY>; /* spba */ 386 clock-names = "core", "rxtx0", 387 "rxtx1", "rxtx2", 388 "rxtx3", "rxtx4", 389 "rxtx5", "rxtx6", 390 "rxtx7", "spba"; 391 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 392 dma-names = "rx", "tx"; 393 status = "disabled"; 394 }; 395 }; 396 397 gpio1: gpio@30200000 { 398 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 399 reg = <0x30200000 0x10000>; 400 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; 403 gpio-controller; 404 #gpio-cells = <2>; 405 interrupt-controller; 406 #interrupt-cells = <2>; 407 gpio-ranges = <&iomuxc 0 10 30>; 408 }; 409 410 gpio2: gpio@30210000 { 411 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 412 reg = <0x30210000 0x10000>; 413 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; 416 gpio-controller; 417 #gpio-cells = <2>; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 gpio-ranges = <&iomuxc 0 40 21>; 421 }; 422 423 gpio3: gpio@30220000 { 424 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 425 reg = <0x30220000 0x10000>; 426 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; 429 gpio-controller; 430 #gpio-cells = <2>; 431 interrupt-controller; 432 #interrupt-cells = <2>; 433 gpio-ranges = <&iomuxc 0 61 26>; 434 }; 435 436 gpio4: gpio@30230000 { 437 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 438 reg = <0x30230000 0x10000>; 439 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; 442 gpio-controller; 443 #gpio-cells = <2>; 444 interrupt-controller; 445 #interrupt-cells = <2>; 446 gpio-ranges = <&iomuxc 0 87 32>; 447 }; 448 449 gpio5: gpio@30240000 { 450 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 451 reg = <0x30240000 0x10000>; 452 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; 455 gpio-controller; 456 #gpio-cells = <2>; 457 interrupt-controller; 458 #interrupt-cells = <2>; 459 gpio-ranges = <&iomuxc 0 119 30>; 460 }; 461 462 tmu: tmu@30260000 { 463 compatible = "fsl,imx8mm-tmu"; 464 reg = <0x30260000 0x10000>; 465 clocks = <&clk IMX8MM_CLK_TMU_ROOT>; 466 #thermal-sensor-cells = <0>; 467 }; 468 469 wdog1: watchdog@30280000 { 470 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 471 reg = <0x30280000 0x10000>; 472 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; 474 status = "disabled"; 475 }; 476 477 wdog2: watchdog@30290000 { 478 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 479 reg = <0x30290000 0x10000>; 480 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; 482 status = "disabled"; 483 }; 484 485 wdog3: watchdog@302a0000 { 486 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 487 reg = <0x302a0000 0x10000>; 488 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; 490 status = "disabled"; 491 }; 492 493 sdma2: dma-controller@302c0000 { 494 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 495 reg = <0x302c0000 0x10000>; 496 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, 498 <&clk IMX8MM_CLK_SDMA2_ROOT>; 499 clock-names = "ipg", "ahb"; 500 #dma-cells = <3>; 501 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 502 }; 503 504 sdma3: dma-controller@302b0000 { 505 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 506 reg = <0x302b0000 0x10000>; 507 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, 509 <&clk IMX8MM_CLK_SDMA3_ROOT>; 510 clock-names = "ipg", "ahb"; 511 #dma-cells = <3>; 512 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 513 }; 514 515 iomuxc: pinctrl@30330000 { 516 compatible = "fsl,imx8mm-iomuxc"; 517 reg = <0x30330000 0x10000>; 518 }; 519 520 gpr: iomuxc-gpr@30340000 { 521 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; 522 reg = <0x30340000 0x10000>; 523 }; 524 525 ocotp: efuse@30350000 { 526 compatible = "fsl,imx8mm-ocotp", "syscon"; 527 reg = <0x30350000 0x10000>; 528 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; 529 /* For nvmem subnodes */ 530 #address-cells = <1>; 531 #size-cells = <1>; 532 533 imx8mm_uid: unique-id@410 { 534 reg = <0x4 0x8>; 535 }; 536 537 cpu_speed_grade: speed-grade@10 { 538 reg = <0x10 4>; 539 }; 540 541 fec_mac_address: mac-address@90 { 542 reg = <0x90 6>; 543 }; 544 }; 545 546 anatop: anatop@30360000 { 547 compatible = "fsl,imx8mm-anatop", "syscon"; 548 reg = <0x30360000 0x10000>; 549 }; 550 551 snvs: snvs@30370000 { 552 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 553 reg = <0x30370000 0x10000>; 554 555 snvs_rtc: snvs-rtc-lp { 556 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 557 regmap = <&snvs>; 558 offset = <0x34>; 559 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 562 clock-names = "snvs-rtc"; 563 }; 564 565 snvs_pwrkey: snvs-powerkey { 566 compatible = "fsl,sec-v4.0-pwrkey"; 567 regmap = <&snvs>; 568 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 570 clock-names = "snvs-pwrkey"; 571 linux,keycode = <KEY_POWER>; 572 wakeup-source; 573 status = "disabled"; 574 }; 575 }; 576 577 clk: clock-controller@30380000 { 578 compatible = "fsl,imx8mm-ccm"; 579 reg = <0x30380000 0x10000>; 580 #clock-cells = <1>; 581 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 582 <&clk_ext3>, <&clk_ext4>; 583 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 584 "clk_ext3", "clk_ext4"; 585 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, 586 <&clk IMX8MM_CLK_A53_CORE>, 587 <&clk IMX8MM_CLK_NOC>, 588 <&clk IMX8MM_CLK_AUDIO_AHB>, 589 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, 590 <&clk IMX8MM_SYS_PLL3>, 591 <&clk IMX8MM_VIDEO_PLL1>, 592 <&clk IMX8MM_AUDIO_PLL1>, 593 <&clk IMX8MM_AUDIO_PLL2>; 594 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 595 <&clk IMX8MM_ARM_PLL_OUT>, 596 <&clk IMX8MM_SYS_PLL3_OUT>, 597 <&clk IMX8MM_SYS_PLL1_800M>; 598 assigned-clock-rates = <0>, <0>, <0>, 599 <400000000>, 600 <400000000>, 601 <750000000>, 602 <594000000>, 603 <393216000>, 604 <361267200>; 605 }; 606 607 src: reset-controller@30390000 { 608 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; 609 reg = <0x30390000 0x10000>; 610 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 611 #reset-cells = <1>; 612 }; 613 }; 614 615 aips2: bus@30400000 { 616 compatible = "fsl,aips-bus", "simple-bus"; 617 reg = <0x30400000 0x400000>; 618 #address-cells = <1>; 619 #size-cells = <1>; 620 ranges = <0x30400000 0x30400000 0x400000>; 621 622 pwm1: pwm@30660000 { 623 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 624 reg = <0x30660000 0x10000>; 625 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, 627 <&clk IMX8MM_CLK_PWM1_ROOT>; 628 clock-names = "ipg", "per"; 629 #pwm-cells = <2>; 630 status = "disabled"; 631 }; 632 633 pwm2: pwm@30670000 { 634 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 635 reg = <0x30670000 0x10000>; 636 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, 638 <&clk IMX8MM_CLK_PWM2_ROOT>; 639 clock-names = "ipg", "per"; 640 #pwm-cells = <2>; 641 status = "disabled"; 642 }; 643 644 pwm3: pwm@30680000 { 645 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 646 reg = <0x30680000 0x10000>; 647 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, 649 <&clk IMX8MM_CLK_PWM3_ROOT>; 650 clock-names = "ipg", "per"; 651 #pwm-cells = <2>; 652 status = "disabled"; 653 }; 654 655 pwm4: pwm@30690000 { 656 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 657 reg = <0x30690000 0x10000>; 658 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, 660 <&clk IMX8MM_CLK_PWM4_ROOT>; 661 clock-names = "ipg", "per"; 662 #pwm-cells = <2>; 663 status = "disabled"; 664 }; 665 666 system_counter: timer@306a0000 { 667 compatible = "nxp,sysctr-timer"; 668 reg = <0x306a0000 0x20000>; 669 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&osc_24m>; 671 clock-names = "per"; 672 }; 673 }; 674 675 aips3: bus@30800000 { 676 compatible = "fsl,aips-bus", "simple-bus"; 677 reg = <0x30800000 0x400000>; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 ranges = <0x30800000 0x30800000 0x400000>, 681 <0x8000000 0x8000000 0x10000000>; 682 683 spba1: spba-bus@30800000 { 684 compatible = "fsl,spba-bus", "simple-bus"; 685 #address-cells = <1>; 686 #size-cells = <1>; 687 reg = <0x30800000 0x100000>; 688 ranges; 689 690 ecspi1: spi@30820000 { 691 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 reg = <0x30820000 0x10000>; 695 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, 697 <&clk IMX8MM_CLK_ECSPI1_ROOT>; 698 clock-names = "ipg", "per"; 699 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 700 dma-names = "rx", "tx"; 701 status = "disabled"; 702 }; 703 704 ecspi2: spi@30830000 { 705 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 reg = <0x30830000 0x10000>; 709 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, 711 <&clk IMX8MM_CLK_ECSPI2_ROOT>; 712 clock-names = "ipg", "per"; 713 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 714 dma-names = "rx", "tx"; 715 status = "disabled"; 716 }; 717 718 ecspi3: spi@30840000 { 719 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 reg = <0x30840000 0x10000>; 723 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, 725 <&clk IMX8MM_CLK_ECSPI3_ROOT>; 726 clock-names = "ipg", "per"; 727 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 728 dma-names = "rx", "tx"; 729 status = "disabled"; 730 }; 731 732 uart1: serial@30860000 { 733 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 734 reg = <0x30860000 0x10000>; 735 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&clk IMX8MM_CLK_UART1_ROOT>, 737 <&clk IMX8MM_CLK_UART1_ROOT>; 738 clock-names = "ipg", "per"; 739 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 740 dma-names = "rx", "tx"; 741 status = "disabled"; 742 }; 743 744 uart3: serial@30880000 { 745 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 746 reg = <0x30880000 0x10000>; 747 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&clk IMX8MM_CLK_UART3_ROOT>, 749 <&clk IMX8MM_CLK_UART3_ROOT>; 750 clock-names = "ipg", "per"; 751 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 752 dma-names = "rx", "tx"; 753 status = "disabled"; 754 }; 755 756 uart2: serial@30890000 { 757 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 758 reg = <0x30890000 0x10000>; 759 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&clk IMX8MM_CLK_UART2_ROOT>, 761 <&clk IMX8MM_CLK_UART2_ROOT>; 762 clock-names = "ipg", "per"; 763 status = "disabled"; 764 }; 765 }; 766 767 crypto: crypto@30900000 { 768 compatible = "fsl,sec-v4.0"; 769 #address-cells = <1>; 770 #size-cells = <1>; 771 reg = <0x30900000 0x40000>; 772 ranges = <0 0x30900000 0x40000>; 773 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&clk IMX8MM_CLK_AHB>, 775 <&clk IMX8MM_CLK_IPG_ROOT>; 776 clock-names = "aclk", "ipg"; 777 778 sec_jr0: jr@1000 { 779 compatible = "fsl,sec-v4.0-job-ring"; 780 reg = <0x1000 0x1000>; 781 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 782 }; 783 784 sec_jr1: jr@2000 { 785 compatible = "fsl,sec-v4.0-job-ring"; 786 reg = <0x2000 0x1000>; 787 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 788 }; 789 790 sec_jr2: jr@3000 { 791 compatible = "fsl,sec-v4.0-job-ring"; 792 reg = <0x3000 0x1000>; 793 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 794 }; 795 }; 796 797 i2c1: i2c@30a20000 { 798 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 reg = <0x30a20000 0x10000>; 802 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; 804 status = "disabled"; 805 }; 806 807 i2c2: i2c@30a30000 { 808 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 reg = <0x30a30000 0x10000>; 812 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; 814 status = "disabled"; 815 }; 816 817 i2c3: i2c@30a40000 { 818 #address-cells = <1>; 819 #size-cells = <0>; 820 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 821 reg = <0x30a40000 0x10000>; 822 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; 824 status = "disabled"; 825 }; 826 827 i2c4: i2c@30a50000 { 828 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 reg = <0x30a50000 0x10000>; 832 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; 834 status = "disabled"; 835 }; 836 837 uart4: serial@30a60000 { 838 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 839 reg = <0x30a60000 0x10000>; 840 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&clk IMX8MM_CLK_UART4_ROOT>, 842 <&clk IMX8MM_CLK_UART4_ROOT>; 843 clock-names = "ipg", "per"; 844 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 845 dma-names = "rx", "tx"; 846 status = "disabled"; 847 }; 848 849 mu: mailbox@30aa0000 { 850 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; 851 reg = <0x30aa0000 0x10000>; 852 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&clk IMX8MM_CLK_MU_ROOT>; 854 #mbox-cells = <2>; 855 }; 856 857 usdhc1: mmc@30b40000 { 858 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 859 reg = <0x30b40000 0x10000>; 860 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 862 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 863 <&clk IMX8MM_CLK_USDHC1_ROOT>; 864 clock-names = "ipg", "ahb", "per"; 865 fsl,tuning-start-tap = <20>; 866 fsl,tuning-step= <2>; 867 bus-width = <4>; 868 status = "disabled"; 869 }; 870 871 usdhc2: mmc@30b50000 { 872 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 873 reg = <0x30b50000 0x10000>; 874 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 876 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 877 <&clk IMX8MM_CLK_USDHC2_ROOT>; 878 clock-names = "ipg", "ahb", "per"; 879 fsl,tuning-start-tap = <20>; 880 fsl,tuning-step= <2>; 881 bus-width = <4>; 882 status = "disabled"; 883 }; 884 885 usdhc3: mmc@30b60000 { 886 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 887 reg = <0x30b60000 0x10000>; 888 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 890 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 891 <&clk IMX8MM_CLK_USDHC3_ROOT>; 892 clock-names = "ipg", "ahb", "per"; 893 fsl,tuning-start-tap = <20>; 894 fsl,tuning-step= <2>; 895 bus-width = <4>; 896 status = "disabled"; 897 }; 898 899 flexspi: spi@30bb0000 { 900 #address-cells = <1>; 901 #size-cells = <0>; 902 compatible = "nxp,imx8mm-fspi"; 903 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 904 reg-names = "fspi_base", "fspi_mmap"; 905 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, 907 <&clk IMX8MM_CLK_QSPI_ROOT>; 908 clock-names = "fspi_en", "fspi"; 909 status = "disabled"; 910 }; 911 912 sdma1: dma-controller@30bd0000 { 913 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 914 reg = <0x30bd0000 0x10000>; 915 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, 917 <&clk IMX8MM_CLK_AHB>; 918 clock-names = "ipg", "ahb"; 919 #dma-cells = <3>; 920 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 921 }; 922 923 fec1: ethernet@30be0000 { 924 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 925 reg = <0x30be0000 0x10000>; 926 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 931 <&clk IMX8MM_CLK_ENET1_ROOT>, 932 <&clk IMX8MM_CLK_ENET_TIMER>, 933 <&clk IMX8MM_CLK_ENET_REF>, 934 <&clk IMX8MM_CLK_ENET_PHY_REF>; 935 clock-names = "ipg", "ahb", "ptp", 936 "enet_clk_ref", "enet_out"; 937 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 938 <&clk IMX8MM_CLK_ENET_TIMER>, 939 <&clk IMX8MM_CLK_ENET_REF>, 940 <&clk IMX8MM_CLK_ENET_PHY_REF>; 941 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 942 <&clk IMX8MM_SYS_PLL2_100M>, 943 <&clk IMX8MM_SYS_PLL2_125M>, 944 <&clk IMX8MM_SYS_PLL2_50M>; 945 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 946 fsl,num-tx-queues = <3>; 947 fsl,num-rx-queues = <3>; 948 nvmem-cells = <&fec_mac_address>; 949 nvmem-cell-names = "mac-address"; 950 nvmem_macaddr_swap; 951 fsl,stop-mode = <&gpr 0x10 3>; 952 status = "disabled"; 953 }; 954 955 }; 956 957 aips4: bus@32c00000 { 958 compatible = "fsl,aips-bus", "simple-bus"; 959 reg = <0x32c00000 0x400000>; 960 #address-cells = <1>; 961 #size-cells = <1>; 962 ranges = <0x32c00000 0x32c00000 0x400000>; 963 964 usbotg1: usb@32e40000 { 965 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 966 reg = <0x32e40000 0x200>; 967 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 969 clock-names = "usb1_ctrl_root_clk"; 970 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 971 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 972 phys = <&usbphynop1>; 973 fsl,usbmisc = <&usbmisc1 0>; 974 status = "disabled"; 975 }; 976 977 usbmisc1: usbmisc@32e40200 { 978 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 979 #index-cells = <1>; 980 reg = <0x32e40200 0x200>; 981 }; 982 983 usbotg2: usb@32e50000 { 984 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 985 reg = <0x32e50000 0x200>; 986 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 988 clock-names = "usb1_ctrl_root_clk"; 989 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 990 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 991 phys = <&usbphynop2>; 992 fsl,usbmisc = <&usbmisc2 0>; 993 status = "disabled"; 994 }; 995 996 usbmisc2: usbmisc@32e50200 { 997 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 998 #index-cells = <1>; 999 reg = <0x32e50200 0x200>; 1000 }; 1001 1002 }; 1003 1004 dma_apbh: dma-controller@33000000 { 1005 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1006 reg = <0x33000000 0x2000>; 1007 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1008 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1011 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1012 #dma-cells = <1>; 1013 dma-channels = <4>; 1014 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1015 }; 1016 1017 gpmi: nand-controller@33002000{ 1018 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1019 #address-cells = <1>; 1020 #size-cells = <1>; 1021 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1022 reg-names = "gpmi-nand", "bch"; 1023 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1024 interrupt-names = "bch"; 1025 clocks = <&clk IMX8MM_CLK_NAND_ROOT>, 1026 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1027 clock-names = "gpmi_io", "gpmi_bch_apb"; 1028 dmas = <&dma_apbh 0>; 1029 dma-names = "rx-tx"; 1030 status = "disabled"; 1031 }; 1032 1033 gic: interrupt-controller@38800000 { 1034 compatible = "arm,gic-v3"; 1035 reg = <0x38800000 0x10000>, /* GIC Dist */ 1036 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ 1037 #interrupt-cells = <3>; 1038 interrupt-controller; 1039 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1040 }; 1041 1042 ddrc: memory-controller@3d400000 { 1043 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; 1044 reg = <0x3d400000 0x400000>; 1045 clock-names = "core", "pll", "alt", "apb"; 1046 clocks = <&clk IMX8MM_CLK_DRAM_CORE>, 1047 <&clk IMX8MM_DRAM_PLL>, 1048 <&clk IMX8MM_CLK_DRAM_ALT>, 1049 <&clk IMX8MM_CLK_DRAM_APB>; 1050 }; 1051 1052 ddr-pmu@3d800000 { 1053 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1054 reg = <0x3d800000 0x400000>; 1055 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1056 }; 1057 }; 1058}; 1059