1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mm-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8mm-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec1; 21 i2c0 = &i2c1; 22 i2c1 = &i2c2; 23 i2c2 = &i2c3; 24 i2c3 = &i2c4; 25 serial0 = &uart1; 26 serial1 = &uart2; 27 serial2 = &uart3; 28 serial3 = &uart4; 29 spi0 = &ecspi1; 30 spi1 = &ecspi2; 31 spi2 = &ecspi3; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 gpio0 = &gpio1; 36 gpio1 = &gpio2; 37 gpio2 = &gpio3; 38 gpio3 = &gpio4; 39 gpio4 = &gpio5; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 idle-states { 47 entry-method = "psci"; 48 49 cpu_pd_wait: cpu-pd-wait { 50 compatible = "arm,idle-state"; 51 arm,psci-suspend-param = <0x0010033>; 52 local-timer-stop; 53 entry-latency-us = <1000>; 54 exit-latency-us = <700>; 55 min-residency-us = <2700>; 56 }; 57 }; 58 59 A53_0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0>; 63 clock-latency = <61036>; /* two CLK32 periods */ 64 clocks = <&clk IMX8MM_CLK_ARM>; 65 enable-method = "psci"; 66 next-level-cache = <&A53_L2>; 67 operating-points-v2 = <&a53_opp_table>; 68 nvmem-cells = <&cpu_speed_grade>; 69 nvmem-cell-names = "speed_grade"; 70 cpu-idle-states = <&cpu_pd_wait>; 71 }; 72 73 A53_1: cpu@1 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x1>; 77 clock-latency = <61036>; /* two CLK32 periods */ 78 clocks = <&clk IMX8MM_CLK_ARM>; 79 enable-method = "psci"; 80 next-level-cache = <&A53_L2>; 81 operating-points-v2 = <&a53_opp_table>; 82 cpu-idle-states = <&cpu_pd_wait>; 83 }; 84 85 A53_2: cpu@2 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 reg = <0x2>; 89 clock-latency = <61036>; /* two CLK32 periods */ 90 clocks = <&clk IMX8MM_CLK_ARM>; 91 enable-method = "psci"; 92 next-level-cache = <&A53_L2>; 93 operating-points-v2 = <&a53_opp_table>; 94 cpu-idle-states = <&cpu_pd_wait>; 95 }; 96 97 A53_3: cpu@3 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x3>; 101 clock-latency = <61036>; /* two CLK32 periods */ 102 clocks = <&clk IMX8MM_CLK_ARM>; 103 enable-method = "psci"; 104 next-level-cache = <&A53_L2>; 105 operating-points-v2 = <&a53_opp_table>; 106 cpu-idle-states = <&cpu_pd_wait>; 107 }; 108 109 A53_L2: l2-cache0 { 110 compatible = "cache"; 111 }; 112 }; 113 114 a53_opp_table: opp-table { 115 compatible = "operating-points-v2"; 116 opp-shared; 117 118 opp-1200000000 { 119 opp-hz = /bits/ 64 <1200000000>; 120 opp-microvolt = <850000>; 121 opp-supported-hw = <0xe>, <0x7>; 122 clock-latency-ns = <150000>; 123 opp-suspend; 124 }; 125 126 opp-1600000000 { 127 opp-hz = /bits/ 64 <1600000000>; 128 opp-microvolt = <900000>; 129 opp-supported-hw = <0xc>, <0x7>; 130 clock-latency-ns = <150000>; 131 opp-suspend; 132 }; 133 134 opp-1800000000 { 135 opp-hz = /bits/ 64 <1800000000>; 136 opp-microvolt = <1000000>; 137 opp-supported-hw = <0x8>, <0x3>; 138 clock-latency-ns = <150000>; 139 opp-suspend; 140 }; 141 }; 142 143 osc_32k: clock-osc-32k { 144 compatible = "fixed-clock"; 145 #clock-cells = <0>; 146 clock-frequency = <32768>; 147 clock-output-names = "osc_32k"; 148 }; 149 150 osc_24m: clock-osc-24m { 151 compatible = "fixed-clock"; 152 #clock-cells = <0>; 153 clock-frequency = <24000000>; 154 clock-output-names = "osc_24m"; 155 }; 156 157 clk_ext1: clock-ext1 { 158 compatible = "fixed-clock"; 159 #clock-cells = <0>; 160 clock-frequency = <133000000>; 161 clock-output-names = "clk_ext1"; 162 }; 163 164 clk_ext2: clock-ext2 { 165 compatible = "fixed-clock"; 166 #clock-cells = <0>; 167 clock-frequency = <133000000>; 168 clock-output-names = "clk_ext2"; 169 }; 170 171 clk_ext3: clock-ext3 { 172 compatible = "fixed-clock"; 173 #clock-cells = <0>; 174 clock-frequency = <133000000>; 175 clock-output-names = "clk_ext3"; 176 }; 177 178 clk_ext4: clock-ext4 { 179 compatible = "fixed-clock"; 180 #clock-cells = <0>; 181 clock-frequency= <133000000>; 182 clock-output-names = "clk_ext4"; 183 }; 184 185 psci { 186 compatible = "arm,psci-1.0"; 187 method = "smc"; 188 }; 189 190 pmu { 191 compatible = "arm,armv8-pmuv3"; 192 interrupts = <GIC_PPI 7 193 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 194 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; 195 }; 196 197 timer { 198 compatible = "arm,armv8-timer"; 199 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 200 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 201 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 202 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 203 clock-frequency = <8000000>; 204 arm,no-tick-in-suspend; 205 }; 206 207 usbphynop1: usbphynop1 { 208 compatible = "usb-nop-xceiv"; 209 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 210 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 211 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 212 clock-names = "main_clk"; 213 }; 214 215 usbphynop2: usbphynop2 { 216 compatible = "usb-nop-xceiv"; 217 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 218 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 219 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 220 clock-names = "main_clk"; 221 }; 222 223 soc@0 { 224 compatible = "simple-bus"; 225 #address-cells = <1>; 226 #size-cells = <1>; 227 ranges = <0x0 0x0 0x0 0x3e000000>; 228 229 aips1: bus@30000000 { 230 compatible = "simple-bus"; 231 #address-cells = <1>; 232 #size-cells = <1>; 233 ranges = <0x30000000 0x30000000 0x400000>; 234 235 sai1: sai@30010000 { 236 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 237 reg = <0x30010000 0x10000>; 238 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 240 <&clk IMX8MM_CLK_SAI1_ROOT>, 241 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 242 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 243 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 244 dma-names = "rx", "tx"; 245 status = "disabled"; 246 }; 247 248 sai2: sai@30020000 { 249 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 250 reg = <0x30020000 0x10000>; 251 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&clk IMX8MM_CLK_SAI2_IPG>, 253 <&clk IMX8MM_CLK_SAI2_ROOT>, 254 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 255 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 256 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 257 dma-names = "rx", "tx"; 258 status = "disabled"; 259 }; 260 261 sai3: sai@30030000 { 262 #sound-dai-cells = <0>; 263 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 264 reg = <0x30030000 0x10000>; 265 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, 267 <&clk IMX8MM_CLK_SAI3_ROOT>, 268 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 269 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 270 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 271 dma-names = "rx", "tx"; 272 status = "disabled"; 273 }; 274 275 sai5: sai@30050000 { 276 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 277 reg = <0x30050000 0x10000>; 278 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&clk IMX8MM_CLK_SAI5_IPG>, 280 <&clk IMX8MM_CLK_SAI5_ROOT>, 281 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 282 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 283 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 284 dma-names = "rx", "tx"; 285 status = "disabled"; 286 }; 287 288 sai6: sai@30060000 { 289 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 290 reg = <0x30060000 0x10000>; 291 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&clk IMX8MM_CLK_SAI6_IPG>, 293 <&clk IMX8MM_CLK_SAI6_ROOT>, 294 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 295 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 296 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 297 dma-names = "rx", "tx"; 298 status = "disabled"; 299 }; 300 301 gpio1: gpio@30200000 { 302 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 303 reg = <0x30200000 0x10000>; 304 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; 307 gpio-controller; 308 #gpio-cells = <2>; 309 interrupt-controller; 310 #interrupt-cells = <2>; 311 gpio-ranges = <&iomuxc 0 10 30>; 312 }; 313 314 gpio2: gpio@30210000 { 315 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 316 reg = <0x30210000 0x10000>; 317 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; 320 gpio-controller; 321 #gpio-cells = <2>; 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 gpio-ranges = <&iomuxc 0 40 21>; 325 }; 326 327 gpio3: gpio@30220000 { 328 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 329 reg = <0x30220000 0x10000>; 330 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 gpio-ranges = <&iomuxc 0 61 26>; 338 }; 339 340 gpio4: gpio@30230000 { 341 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 342 reg = <0x30230000 0x10000>; 343 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; 346 gpio-controller; 347 #gpio-cells = <2>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 gpio-ranges = <&iomuxc 0 87 32>; 351 }; 352 353 gpio5: gpio@30240000 { 354 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 355 reg = <0x30240000 0x10000>; 356 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; 359 gpio-controller; 360 #gpio-cells = <2>; 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 gpio-ranges = <&iomuxc 0 119 30>; 364 }; 365 366 wdog1: watchdog@30280000 { 367 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 368 reg = <0x30280000 0x10000>; 369 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; 371 status = "disabled"; 372 }; 373 374 wdog2: watchdog@30290000 { 375 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 376 reg = <0x30290000 0x10000>; 377 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; 379 status = "disabled"; 380 }; 381 382 wdog3: watchdog@302a0000 { 383 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 384 reg = <0x302a0000 0x10000>; 385 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; 387 status = "disabled"; 388 }; 389 390 sdma2: dma-controller@302c0000 { 391 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 392 reg = <0x302c0000 0x10000>; 393 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, 395 <&clk IMX8MM_CLK_SDMA2_ROOT>; 396 clock-names = "ipg", "ahb"; 397 #dma-cells = <3>; 398 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 399 }; 400 401 sdma3: dma-controller@302b0000 { 402 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 403 reg = <0x302b0000 0x10000>; 404 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, 406 <&clk IMX8MM_CLK_SDMA3_ROOT>; 407 clock-names = "ipg", "ahb"; 408 #dma-cells = <3>; 409 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 410 }; 411 412 iomuxc: pinctrl@30330000 { 413 compatible = "fsl,imx8mm-iomuxc"; 414 reg = <0x30330000 0x10000>; 415 }; 416 417 gpr: iomuxc-gpr@30340000 { 418 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; 419 reg = <0x30340000 0x10000>; 420 }; 421 422 ocotp: ocotp-ctrl@30350000 { 423 compatible = "fsl,imx8mm-ocotp", "syscon"; 424 reg = <0x30350000 0x10000>; 425 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; 426 /* For nvmem subnodes */ 427 #address-cells = <1>; 428 #size-cells = <1>; 429 430 cpu_speed_grade: speed-grade@10 { 431 reg = <0x10 4>; 432 }; 433 }; 434 435 anatop: anatop@30360000 { 436 compatible = "fsl,imx8mm-anatop", "syscon"; 437 reg = <0x30360000 0x10000>; 438 }; 439 440 snvs: snvs@30370000 { 441 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 442 reg = <0x30370000 0x10000>; 443 444 snvs_rtc: snvs-rtc-lp { 445 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 446 regmap = <&snvs>; 447 offset = <0x34>; 448 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 451 clock-names = "snvs-rtc"; 452 }; 453 454 snvs_pwrkey: snvs-powerkey { 455 compatible = "fsl,sec-v4.0-pwrkey"; 456 regmap = <&snvs>; 457 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 458 linux,keycode = <KEY_POWER>; 459 wakeup-source; 460 status = "disabled"; 461 }; 462 }; 463 464 clk: clock-controller@30380000 { 465 compatible = "fsl,imx8mm-ccm"; 466 reg = <0x30380000 0x10000>; 467 #clock-cells = <1>; 468 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 469 <&clk_ext3>, <&clk_ext4>; 470 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 471 "clk_ext3", "clk_ext4"; 472 assigned-clocks = <&clk IMX8MM_CLK_NOC>, 473 <&clk IMX8MM_CLK_AUDIO_AHB>, 474 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, 475 <&clk IMX8MM_SYS_PLL3>, 476 <&clk IMX8MM_VIDEO_PLL1>, 477 <&clk IMX8MM_AUDIO_PLL1>, 478 <&clk IMX8MM_AUDIO_PLL2>; 479 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>, 480 <&clk IMX8MM_SYS_PLL1_800M>; 481 assigned-clock-rates = <0>, 482 <400000000>, 483 <400000000>, 484 <750000000>, 485 <594000000>, 486 <393216000>, 487 <361267200>; 488 }; 489 490 src: reset-controller@30390000 { 491 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; 492 reg = <0x30390000 0x10000>; 493 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 494 #reset-cells = <1>; 495 }; 496 }; 497 498 aips2: bus@30400000 { 499 compatible = "simple-bus"; 500 #address-cells = <1>; 501 #size-cells = <1>; 502 ranges = <0x30400000 0x30400000 0x400000>; 503 504 pwm1: pwm@30660000 { 505 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 506 reg = <0x30660000 0x10000>; 507 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, 509 <&clk IMX8MM_CLK_PWM1_ROOT>; 510 clock-names = "ipg", "per"; 511 #pwm-cells = <2>; 512 status = "disabled"; 513 }; 514 515 pwm2: pwm@30670000 { 516 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 517 reg = <0x30670000 0x10000>; 518 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, 520 <&clk IMX8MM_CLK_PWM2_ROOT>; 521 clock-names = "ipg", "per"; 522 #pwm-cells = <2>; 523 status = "disabled"; 524 }; 525 526 pwm3: pwm@30680000 { 527 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 528 reg = <0x30680000 0x10000>; 529 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, 531 <&clk IMX8MM_CLK_PWM3_ROOT>; 532 clock-names = "ipg", "per"; 533 #pwm-cells = <2>; 534 status = "disabled"; 535 }; 536 537 pwm4: pwm@30690000 { 538 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 539 reg = <0x30690000 0x10000>; 540 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, 542 <&clk IMX8MM_CLK_PWM4_ROOT>; 543 clock-names = "ipg", "per"; 544 #pwm-cells = <2>; 545 status = "disabled"; 546 }; 547 548 system_counter: timer@306a0000 { 549 compatible = "nxp,sysctr-timer"; 550 reg = <0x306a0000 0x20000>; 551 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&osc_24m>; 553 clock-names = "per"; 554 }; 555 }; 556 557 aips3: bus@30800000 { 558 compatible = "simple-bus"; 559 #address-cells = <1>; 560 #size-cells = <1>; 561 ranges = <0x30800000 0x30800000 0x400000>; 562 563 ecspi1: spi@30820000 { 564 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 reg = <0x30820000 0x10000>; 568 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, 570 <&clk IMX8MM_CLK_ECSPI1_ROOT>; 571 clock-names = "ipg", "per"; 572 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 573 dma-names = "rx", "tx"; 574 status = "disabled"; 575 }; 576 577 ecspi2: spi@30830000 { 578 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 reg = <0x30830000 0x10000>; 582 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, 584 <&clk IMX8MM_CLK_ECSPI2_ROOT>; 585 clock-names = "ipg", "per"; 586 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 587 dma-names = "rx", "tx"; 588 status = "disabled"; 589 }; 590 591 ecspi3: spi@30840000 { 592 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 reg = <0x30840000 0x10000>; 596 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, 598 <&clk IMX8MM_CLK_ECSPI3_ROOT>; 599 clock-names = "ipg", "per"; 600 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 601 dma-names = "rx", "tx"; 602 status = "disabled"; 603 }; 604 605 uart1: serial@30860000 { 606 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 607 reg = <0x30860000 0x10000>; 608 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&clk IMX8MM_CLK_UART1_ROOT>, 610 <&clk IMX8MM_CLK_UART1_ROOT>; 611 clock-names = "ipg", "per"; 612 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 613 dma-names = "rx", "tx"; 614 status = "disabled"; 615 }; 616 617 uart3: serial@30880000 { 618 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 619 reg = <0x30880000 0x10000>; 620 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&clk IMX8MM_CLK_UART3_ROOT>, 622 <&clk IMX8MM_CLK_UART3_ROOT>; 623 clock-names = "ipg", "per"; 624 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 625 dma-names = "rx", "tx"; 626 status = "disabled"; 627 }; 628 629 uart2: serial@30890000 { 630 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 631 reg = <0x30890000 0x10000>; 632 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&clk IMX8MM_CLK_UART2_ROOT>, 634 <&clk IMX8MM_CLK_UART2_ROOT>; 635 clock-names = "ipg", "per"; 636 status = "disabled"; 637 }; 638 639 crypto: crypto@30900000 { 640 compatible = "fsl,sec-v4.0"; 641 #address-cells = <1>; 642 #size-cells = <1>; 643 reg = <0x30900000 0x40000>; 644 ranges = <0 0x30900000 0x40000>; 645 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&clk IMX8MM_CLK_AHB>, 647 <&clk IMX8MM_CLK_IPG_ROOT>; 648 clock-names = "aclk", "ipg"; 649 650 sec_jr0: jr@1000 { 651 compatible = "fsl,sec-v4.0-job-ring"; 652 reg = <0x1000 0x1000>; 653 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 654 }; 655 656 sec_jr1: jr@2000 { 657 compatible = "fsl,sec-v4.0-job-ring"; 658 reg = <0x2000 0x1000>; 659 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 660 }; 661 662 sec_jr2: jr@3000 { 663 compatible = "fsl,sec-v4.0-job-ring"; 664 reg = <0x3000 0x1000>; 665 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 666 }; 667 }; 668 669 i2c1: i2c@30a20000 { 670 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 reg = <0x30a20000 0x10000>; 674 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; 676 status = "disabled"; 677 }; 678 679 i2c2: i2c@30a30000 { 680 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 681 #address-cells = <1>; 682 #size-cells = <0>; 683 reg = <0x30a30000 0x10000>; 684 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; 686 status = "disabled"; 687 }; 688 689 i2c3: i2c@30a40000 { 690 #address-cells = <1>; 691 #size-cells = <0>; 692 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 693 reg = <0x30a40000 0x10000>; 694 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; 696 status = "disabled"; 697 }; 698 699 i2c4: i2c@30a50000 { 700 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 reg = <0x30a50000 0x10000>; 704 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; 706 status = "disabled"; 707 }; 708 709 uart4: serial@30a60000 { 710 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 711 reg = <0x30a60000 0x10000>; 712 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&clk IMX8MM_CLK_UART4_ROOT>, 714 <&clk IMX8MM_CLK_UART4_ROOT>; 715 clock-names = "ipg", "per"; 716 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 717 dma-names = "rx", "tx"; 718 status = "disabled"; 719 }; 720 721 usdhc1: mmc@30b40000 { 722 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 723 reg = <0x30b40000 0x10000>; 724 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 726 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 727 <&clk IMX8MM_CLK_USDHC1_ROOT>; 728 clock-names = "ipg", "ahb", "per"; 729 fsl,tuning-start-tap = <20>; 730 fsl,tuning-step= <2>; 731 bus-width = <4>; 732 status = "disabled"; 733 }; 734 735 usdhc2: mmc@30b50000 { 736 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 737 reg = <0x30b50000 0x10000>; 738 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 740 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 741 <&clk IMX8MM_CLK_USDHC2_ROOT>; 742 clock-names = "ipg", "ahb", "per"; 743 fsl,tuning-start-tap = <20>; 744 fsl,tuning-step= <2>; 745 bus-width = <4>; 746 status = "disabled"; 747 }; 748 749 usdhc3: mmc@30b60000 { 750 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 751 reg = <0x30b60000 0x10000>; 752 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 754 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 755 <&clk IMX8MM_CLK_USDHC3_ROOT>; 756 clock-names = "ipg", "ahb", "per"; 757 fsl,tuning-start-tap = <20>; 758 fsl,tuning-step= <2>; 759 bus-width = <4>; 760 status = "disabled"; 761 }; 762 763 sdma1: dma-controller@30bd0000 { 764 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 765 reg = <0x30bd0000 0x10000>; 766 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, 768 <&clk IMX8MM_CLK_AHB>; 769 clock-names = "ipg", "ahb"; 770 #dma-cells = <3>; 771 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 772 }; 773 774 fec1: ethernet@30be0000 { 775 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec"; 776 reg = <0x30be0000 0x10000>; 777 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 781 <&clk IMX8MM_CLK_ENET1_ROOT>, 782 <&clk IMX8MM_CLK_ENET_TIMER>, 783 <&clk IMX8MM_CLK_ENET_REF>, 784 <&clk IMX8MM_CLK_ENET_PHY_REF>; 785 clock-names = "ipg", "ahb", "ptp", 786 "enet_clk_ref", "enet_out"; 787 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 788 <&clk IMX8MM_CLK_ENET_TIMER>, 789 <&clk IMX8MM_CLK_ENET_REF>, 790 <&clk IMX8MM_CLK_ENET_TIMER>; 791 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 792 <&clk IMX8MM_SYS_PLL2_100M>, 793 <&clk IMX8MM_SYS_PLL2_125M>; 794 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; 795 fsl,num-tx-queues = <3>; 796 fsl,num-rx-queues = <3>; 797 status = "disabled"; 798 }; 799 800 }; 801 802 aips4: bus@32c00000 { 803 compatible = "simple-bus"; 804 #address-cells = <1>; 805 #size-cells = <1>; 806 ranges = <0x32c00000 0x32c00000 0x400000>; 807 808 usbotg1: usb@32e40000 { 809 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 810 reg = <0x32e40000 0x200>; 811 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 813 clock-names = "usb1_ctrl_root_clk"; 814 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 815 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 816 fsl,usbphy = <&usbphynop1>; 817 fsl,usbmisc = <&usbmisc1 0>; 818 status = "disabled"; 819 }; 820 821 usbmisc1: usbmisc@32e40200 { 822 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 823 #index-cells = <1>; 824 reg = <0x32e40200 0x200>; 825 }; 826 827 usbotg2: usb@32e50000 { 828 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 829 reg = <0x32e50000 0x200>; 830 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 832 clock-names = "usb1_ctrl_root_clk"; 833 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 834 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 835 fsl,usbphy = <&usbphynop2>; 836 fsl,usbmisc = <&usbmisc2 0>; 837 status = "disabled"; 838 }; 839 840 usbmisc2: usbmisc@32e50200 { 841 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 842 #index-cells = <1>; 843 reg = <0x32e50200 0x200>; 844 }; 845 846 }; 847 848 dma_apbh: dma-controller@33000000 { 849 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 850 reg = <0x33000000 0x2000>; 851 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 855 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 856 #dma-cells = <1>; 857 dma-channels = <4>; 858 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 859 }; 860 861 gpmi: nand-controller@33002000{ 862 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; 863 #address-cells = <1>; 864 #size-cells = <1>; 865 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 866 reg-names = "gpmi-nand", "bch"; 867 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 868 interrupt-names = "bch"; 869 clocks = <&clk IMX8MM_CLK_NAND_ROOT>, 870 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 871 clock-names = "gpmi_io", "gpmi_bch_apb"; 872 dmas = <&dma_apbh 0>; 873 dma-names = "rx-tx"; 874 status = "disabled"; 875 }; 876 877 gic: interrupt-controller@38800000 { 878 compatible = "arm,gic-v3"; 879 reg = <0x38800000 0x10000>, /* GIC Dist */ 880 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ 881 #interrupt-cells = <3>; 882 interrupt-controller; 883 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 884 }; 885 886 ddrc: memory-controller@3d400000 { 887 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; 888 reg = <0x3d400000 0x400000>; 889 clock-names = "core", "pll", "alt", "apb"; 890 clocks = <&clk IMX8MM_CLK_DRAM_CORE>, 891 <&clk IMX8MM_DRAM_PLL>, 892 <&clk IMX8MM_CLK_DRAM_ALT>, 893 <&clk IMX8MM_CLK_DRAM_APB>; 894 }; 895 896 ddr-pmu@3d800000 { 897 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; 898 reg = <0x3d800000 0x400000>; 899 interrupt-parent = <&gic>; 900 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 901 }; 902 }; 903}; 904