1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mm-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8mm-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec1; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 i2c0 = &i2c1; 27 i2c1 = &i2c2; 28 i2c2 = &i2c3; 29 i2c3 = &i2c4; 30 mmc0 = &usdhc1; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc3; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 serial3 = &uart4; 37 spi0 = &ecspi1; 38 spi1 = &ecspi2; 39 spi2 = &ecspi3; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 idle-states { 47 entry-method = "psci"; 48 49 cpu_pd_wait: cpu-pd-wait { 50 compatible = "arm,idle-state"; 51 arm,psci-suspend-param = <0x0010033>; 52 local-timer-stop; 53 entry-latency-us = <1000>; 54 exit-latency-us = <700>; 55 min-residency-us = <2700>; 56 }; 57 }; 58 59 A53_0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0>; 63 clock-latency = <61036>; /* two CLK32 periods */ 64 clocks = <&clk IMX8MM_CLK_ARM>; 65 enable-method = "psci"; 66 next-level-cache = <&A53_L2>; 67 operating-points-v2 = <&a53_opp_table>; 68 nvmem-cells = <&cpu_speed_grade>; 69 nvmem-cell-names = "speed_grade"; 70 cpu-idle-states = <&cpu_pd_wait>; 71 #cooling-cells = <2>; 72 }; 73 74 A53_1: cpu@1 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x1>; 78 clock-latency = <61036>; /* two CLK32 periods */ 79 clocks = <&clk IMX8MM_CLK_ARM>; 80 enable-method = "psci"; 81 next-level-cache = <&A53_L2>; 82 operating-points-v2 = <&a53_opp_table>; 83 cpu-idle-states = <&cpu_pd_wait>; 84 #cooling-cells = <2>; 85 }; 86 87 A53_2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x2>; 91 clock-latency = <61036>; /* two CLK32 periods */ 92 clocks = <&clk IMX8MM_CLK_ARM>; 93 enable-method = "psci"; 94 next-level-cache = <&A53_L2>; 95 operating-points-v2 = <&a53_opp_table>; 96 cpu-idle-states = <&cpu_pd_wait>; 97 #cooling-cells = <2>; 98 }; 99 100 A53_3: cpu@3 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x3>; 104 clock-latency = <61036>; /* two CLK32 periods */ 105 clocks = <&clk IMX8MM_CLK_ARM>; 106 enable-method = "psci"; 107 next-level-cache = <&A53_L2>; 108 operating-points-v2 = <&a53_opp_table>; 109 cpu-idle-states = <&cpu_pd_wait>; 110 #cooling-cells = <2>; 111 }; 112 113 A53_L2: l2-cache0 { 114 compatible = "cache"; 115 }; 116 }; 117 118 a53_opp_table: opp-table { 119 compatible = "operating-points-v2"; 120 opp-shared; 121 122 opp-1200000000 { 123 opp-hz = /bits/ 64 <1200000000>; 124 opp-microvolt = <850000>; 125 opp-supported-hw = <0xe>, <0x7>; 126 clock-latency-ns = <150000>; 127 opp-suspend; 128 }; 129 130 opp-1600000000 { 131 opp-hz = /bits/ 64 <1600000000>; 132 opp-microvolt = <950000>; 133 opp-supported-hw = <0xc>, <0x7>; 134 clock-latency-ns = <150000>; 135 opp-suspend; 136 }; 137 138 opp-1800000000 { 139 opp-hz = /bits/ 64 <1800000000>; 140 opp-microvolt = <1000000>; 141 opp-supported-hw = <0x8>, <0x3>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 }; 146 147 osc_32k: clock-osc-32k { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <32768>; 151 clock-output-names = "osc_32k"; 152 }; 153 154 osc_24m: clock-osc-24m { 155 compatible = "fixed-clock"; 156 #clock-cells = <0>; 157 clock-frequency = <24000000>; 158 clock-output-names = "osc_24m"; 159 }; 160 161 clk_ext1: clock-ext1 { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <133000000>; 165 clock-output-names = "clk_ext1"; 166 }; 167 168 clk_ext2: clock-ext2 { 169 compatible = "fixed-clock"; 170 #clock-cells = <0>; 171 clock-frequency = <133000000>; 172 clock-output-names = "clk_ext2"; 173 }; 174 175 clk_ext3: clock-ext3 { 176 compatible = "fixed-clock"; 177 #clock-cells = <0>; 178 clock-frequency = <133000000>; 179 clock-output-names = "clk_ext3"; 180 }; 181 182 clk_ext4: clock-ext4 { 183 compatible = "fixed-clock"; 184 #clock-cells = <0>; 185 clock-frequency= <133000000>; 186 clock-output-names = "clk_ext4"; 187 }; 188 189 psci { 190 compatible = "arm,psci-1.0"; 191 method = "smc"; 192 }; 193 194 pmu { 195 compatible = "arm,armv8-pmuv3"; 196 interrupts = <GIC_PPI 7 197 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 198 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; 199 }; 200 201 timer { 202 compatible = "arm,armv8-timer"; 203 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 204 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 205 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 206 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 207 clock-frequency = <8000000>; 208 arm,no-tick-in-suspend; 209 }; 210 211 thermal-zones { 212 cpu-thermal { 213 polling-delay-passive = <250>; 214 polling-delay = <2000>; 215 thermal-sensors = <&tmu>; 216 trips { 217 cpu_alert0: trip0 { 218 temperature = <85000>; 219 hysteresis = <2000>; 220 type = "passive"; 221 }; 222 223 cpu_crit0: trip1 { 224 temperature = <95000>; 225 hysteresis = <2000>; 226 type = "critical"; 227 }; 228 }; 229 230 cooling-maps { 231 map0 { 232 trip = <&cpu_alert0>; 233 cooling-device = 234 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 235 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 236 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 237 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 238 }; 239 }; 240 }; 241 }; 242 243 usbphynop1: usbphynop1 { 244 compatible = "usb-nop-xceiv"; 245 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 246 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 247 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 248 clock-names = "main_clk"; 249 }; 250 251 usbphynop2: usbphynop2 { 252 compatible = "usb-nop-xceiv"; 253 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 254 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 255 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 256 clock-names = "main_clk"; 257 }; 258 259 soc@0 { 260 compatible = "simple-bus"; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 ranges = <0x0 0x0 0x0 0x3e000000>; 264 265 aips1: bus@30000000 { 266 compatible = "fsl,aips-bus", "simple-bus"; 267 reg = <0x30000000 0x400000>; 268 #address-cells = <1>; 269 #size-cells = <1>; 270 ranges = <0x30000000 0x30000000 0x400000>; 271 272 sai1: sai@30010000 { 273 #sound-dai-cells = <0>; 274 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 275 reg = <0x30010000 0x10000>; 276 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 278 <&clk IMX8MM_CLK_SAI1_ROOT>, 279 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 280 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 281 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 282 dma-names = "rx", "tx"; 283 status = "disabled"; 284 }; 285 286 sai2: sai@30020000 { 287 #sound-dai-cells = <0>; 288 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 289 reg = <0x30020000 0x10000>; 290 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&clk IMX8MM_CLK_SAI2_IPG>, 292 <&clk IMX8MM_CLK_SAI2_ROOT>, 293 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 294 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 295 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 296 dma-names = "rx", "tx"; 297 status = "disabled"; 298 }; 299 300 sai3: sai@30030000 { 301 #sound-dai-cells = <0>; 302 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 303 reg = <0x30030000 0x10000>; 304 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, 306 <&clk IMX8MM_CLK_SAI3_ROOT>, 307 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 308 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 309 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 310 dma-names = "rx", "tx"; 311 status = "disabled"; 312 }; 313 314 sai5: sai@30050000 { 315 #sound-dai-cells = <0>; 316 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 317 reg = <0x30050000 0x10000>; 318 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk IMX8MM_CLK_SAI5_IPG>, 320 <&clk IMX8MM_CLK_SAI5_ROOT>, 321 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 322 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 323 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 324 dma-names = "rx", "tx"; 325 status = "disabled"; 326 }; 327 328 sai6: sai@30060000 { 329 #sound-dai-cells = <0>; 330 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 331 reg = <0x30060000 0x10000>; 332 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&clk IMX8MM_CLK_SAI6_IPG>, 334 <&clk IMX8MM_CLK_SAI6_ROOT>, 335 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 336 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 337 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 338 dma-names = "rx", "tx"; 339 status = "disabled"; 340 }; 341 342 micfil: audio-controller@30080000 { 343 compatible = "fsl,imx8mm-micfil"; 344 reg = <0x30080000 0x10000>; 345 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&clk IMX8MM_CLK_PDM_IPG>, 350 <&clk IMX8MM_CLK_PDM_ROOT>, 351 <&clk IMX8MM_AUDIO_PLL1_OUT>, 352 <&clk IMX8MM_AUDIO_PLL2_OUT>, 353 <&clk IMX8MM_CLK_EXT3>; 354 clock-names = "ipg_clk", "ipg_clk_app", 355 "pll8k", "pll11k", "clkext3"; 356 dmas = <&sdma2 24 25 0x80000000>; 357 dma-names = "rx"; 358 status = "disabled"; 359 }; 360 361 spdif1: spdif@30090000 { 362 compatible = "fsl,imx35-spdif"; 363 reg = <0x30090000 0x10000>; 364 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ 366 <&clk IMX8MM_CLK_24M>, /* rxtx0 */ 367 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ 368 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ 369 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ 370 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ 371 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ 372 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ 373 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ 374 <&clk IMX8MM_CLK_DUMMY>; /* spba */ 375 clock-names = "core", "rxtx0", 376 "rxtx1", "rxtx2", 377 "rxtx3", "rxtx4", 378 "rxtx5", "rxtx6", 379 "rxtx7", "spba"; 380 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 381 dma-names = "rx", "tx"; 382 status = "disabled"; 383 }; 384 385 gpio1: gpio@30200000 { 386 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 387 reg = <0x30200000 0x10000>; 388 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; 391 gpio-controller; 392 #gpio-cells = <2>; 393 interrupt-controller; 394 #interrupt-cells = <2>; 395 gpio-ranges = <&iomuxc 0 10 30>; 396 }; 397 398 gpio2: gpio@30210000 { 399 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 400 reg = <0x30210000 0x10000>; 401 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; 404 gpio-controller; 405 #gpio-cells = <2>; 406 interrupt-controller; 407 #interrupt-cells = <2>; 408 gpio-ranges = <&iomuxc 0 40 21>; 409 }; 410 411 gpio3: gpio@30220000 { 412 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 413 reg = <0x30220000 0x10000>; 414 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; 417 gpio-controller; 418 #gpio-cells = <2>; 419 interrupt-controller; 420 #interrupt-cells = <2>; 421 gpio-ranges = <&iomuxc 0 61 26>; 422 }; 423 424 gpio4: gpio@30230000 { 425 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 426 reg = <0x30230000 0x10000>; 427 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; 430 gpio-controller; 431 #gpio-cells = <2>; 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 gpio-ranges = <&iomuxc 0 87 32>; 435 }; 436 437 gpio5: gpio@30240000 { 438 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 439 reg = <0x30240000 0x10000>; 440 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; 443 gpio-controller; 444 #gpio-cells = <2>; 445 interrupt-controller; 446 #interrupt-cells = <2>; 447 gpio-ranges = <&iomuxc 0 119 30>; 448 }; 449 450 tmu: tmu@30260000 { 451 compatible = "fsl,imx8mm-tmu"; 452 reg = <0x30260000 0x10000>; 453 clocks = <&clk IMX8MM_CLK_TMU_ROOT>; 454 #thermal-sensor-cells = <0>; 455 }; 456 457 wdog1: watchdog@30280000 { 458 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 459 reg = <0x30280000 0x10000>; 460 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; 462 status = "disabled"; 463 }; 464 465 wdog2: watchdog@30290000 { 466 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 467 reg = <0x30290000 0x10000>; 468 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; 470 status = "disabled"; 471 }; 472 473 wdog3: watchdog@302a0000 { 474 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 475 reg = <0x302a0000 0x10000>; 476 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; 478 status = "disabled"; 479 }; 480 481 sdma2: dma-controller@302c0000 { 482 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 483 reg = <0x302c0000 0x10000>; 484 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, 486 <&clk IMX8MM_CLK_SDMA2_ROOT>; 487 clock-names = "ipg", "ahb"; 488 #dma-cells = <3>; 489 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 490 }; 491 492 sdma3: dma-controller@302b0000 { 493 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 494 reg = <0x302b0000 0x10000>; 495 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, 497 <&clk IMX8MM_CLK_SDMA3_ROOT>; 498 clock-names = "ipg", "ahb"; 499 #dma-cells = <3>; 500 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 501 }; 502 503 iomuxc: pinctrl@30330000 { 504 compatible = "fsl,imx8mm-iomuxc"; 505 reg = <0x30330000 0x10000>; 506 }; 507 508 gpr: iomuxc-gpr@30340000 { 509 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; 510 reg = <0x30340000 0x10000>; 511 }; 512 513 ocotp: efuse@30350000 { 514 compatible = "fsl,imx8mm-ocotp", "syscon"; 515 reg = <0x30350000 0x10000>; 516 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; 517 /* For nvmem subnodes */ 518 #address-cells = <1>; 519 #size-cells = <1>; 520 521 cpu_speed_grade: speed-grade@10 { 522 reg = <0x10 4>; 523 }; 524 }; 525 526 anatop: anatop@30360000 { 527 compatible = "fsl,imx8mm-anatop", "syscon"; 528 reg = <0x30360000 0x10000>; 529 }; 530 531 snvs: snvs@30370000 { 532 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 533 reg = <0x30370000 0x10000>; 534 535 snvs_rtc: snvs-rtc-lp { 536 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 537 regmap = <&snvs>; 538 offset = <0x34>; 539 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 542 clock-names = "snvs-rtc"; 543 }; 544 545 snvs_pwrkey: snvs-powerkey { 546 compatible = "fsl,sec-v4.0-pwrkey"; 547 regmap = <&snvs>; 548 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 550 clock-names = "snvs-pwrkey"; 551 linux,keycode = <KEY_POWER>; 552 wakeup-source; 553 status = "disabled"; 554 }; 555 }; 556 557 clk: clock-controller@30380000 { 558 compatible = "fsl,imx8mm-ccm"; 559 reg = <0x30380000 0x10000>; 560 #clock-cells = <1>; 561 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 562 <&clk_ext3>, <&clk_ext4>; 563 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 564 "clk_ext3", "clk_ext4"; 565 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, 566 <&clk IMX8MM_CLK_A53_CORE>, 567 <&clk IMX8MM_CLK_NOC>, 568 <&clk IMX8MM_CLK_AUDIO_AHB>, 569 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, 570 <&clk IMX8MM_SYS_PLL3>, 571 <&clk IMX8MM_VIDEO_PLL1>, 572 <&clk IMX8MM_AUDIO_PLL1>, 573 <&clk IMX8MM_AUDIO_PLL2>; 574 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 575 <&clk IMX8MM_ARM_PLL_OUT>, 576 <&clk IMX8MM_SYS_PLL3_OUT>, 577 <&clk IMX8MM_SYS_PLL1_800M>; 578 assigned-clock-rates = <0>, <0>, <0>, 579 <400000000>, 580 <400000000>, 581 <750000000>, 582 <594000000>, 583 <393216000>, 584 <361267200>; 585 }; 586 587 src: reset-controller@30390000 { 588 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; 589 reg = <0x30390000 0x10000>; 590 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 591 #reset-cells = <1>; 592 }; 593 }; 594 595 aips2: bus@30400000 { 596 compatible = "fsl,aips-bus", "simple-bus"; 597 reg = <0x30400000 0x400000>; 598 #address-cells = <1>; 599 #size-cells = <1>; 600 ranges = <0x30400000 0x30400000 0x400000>; 601 602 pwm1: pwm@30660000 { 603 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 604 reg = <0x30660000 0x10000>; 605 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, 607 <&clk IMX8MM_CLK_PWM1_ROOT>; 608 clock-names = "ipg", "per"; 609 #pwm-cells = <2>; 610 status = "disabled"; 611 }; 612 613 pwm2: pwm@30670000 { 614 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 615 reg = <0x30670000 0x10000>; 616 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, 618 <&clk IMX8MM_CLK_PWM2_ROOT>; 619 clock-names = "ipg", "per"; 620 #pwm-cells = <2>; 621 status = "disabled"; 622 }; 623 624 pwm3: pwm@30680000 { 625 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 626 reg = <0x30680000 0x10000>; 627 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, 629 <&clk IMX8MM_CLK_PWM3_ROOT>; 630 clock-names = "ipg", "per"; 631 #pwm-cells = <2>; 632 status = "disabled"; 633 }; 634 635 pwm4: pwm@30690000 { 636 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 637 reg = <0x30690000 0x10000>; 638 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, 640 <&clk IMX8MM_CLK_PWM4_ROOT>; 641 clock-names = "ipg", "per"; 642 #pwm-cells = <2>; 643 status = "disabled"; 644 }; 645 646 system_counter: timer@306a0000 { 647 compatible = "nxp,sysctr-timer"; 648 reg = <0x306a0000 0x20000>; 649 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&osc_24m>; 651 clock-names = "per"; 652 }; 653 }; 654 655 aips3: bus@30800000 { 656 compatible = "fsl,aips-bus", "simple-bus"; 657 reg = <0x30800000 0x400000>; 658 #address-cells = <1>; 659 #size-cells = <1>; 660 ranges = <0x30800000 0x30800000 0x400000>, 661 <0x8000000 0x8000000 0x10000000>; 662 663 ecspi1: spi@30820000 { 664 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 reg = <0x30820000 0x10000>; 668 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, 670 <&clk IMX8MM_CLK_ECSPI1_ROOT>; 671 clock-names = "ipg", "per"; 672 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 673 dma-names = "rx", "tx"; 674 status = "disabled"; 675 }; 676 677 ecspi2: spi@30830000 { 678 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 reg = <0x30830000 0x10000>; 682 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, 684 <&clk IMX8MM_CLK_ECSPI2_ROOT>; 685 clock-names = "ipg", "per"; 686 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 687 dma-names = "rx", "tx"; 688 status = "disabled"; 689 }; 690 691 ecspi3: spi@30840000 { 692 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 reg = <0x30840000 0x10000>; 696 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, 698 <&clk IMX8MM_CLK_ECSPI3_ROOT>; 699 clock-names = "ipg", "per"; 700 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 701 dma-names = "rx", "tx"; 702 status = "disabled"; 703 }; 704 705 uart1: serial@30860000 { 706 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 707 reg = <0x30860000 0x10000>; 708 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&clk IMX8MM_CLK_UART1_ROOT>, 710 <&clk IMX8MM_CLK_UART1_ROOT>; 711 clock-names = "ipg", "per"; 712 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 713 dma-names = "rx", "tx"; 714 status = "disabled"; 715 }; 716 717 uart3: serial@30880000 { 718 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 719 reg = <0x30880000 0x10000>; 720 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&clk IMX8MM_CLK_UART3_ROOT>, 722 <&clk IMX8MM_CLK_UART3_ROOT>; 723 clock-names = "ipg", "per"; 724 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 725 dma-names = "rx", "tx"; 726 status = "disabled"; 727 }; 728 729 uart2: serial@30890000 { 730 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 731 reg = <0x30890000 0x10000>; 732 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&clk IMX8MM_CLK_UART2_ROOT>, 734 <&clk IMX8MM_CLK_UART2_ROOT>; 735 clock-names = "ipg", "per"; 736 status = "disabled"; 737 }; 738 739 crypto: crypto@30900000 { 740 compatible = "fsl,sec-v4.0"; 741 #address-cells = <1>; 742 #size-cells = <1>; 743 reg = <0x30900000 0x40000>; 744 ranges = <0 0x30900000 0x40000>; 745 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&clk IMX8MM_CLK_AHB>, 747 <&clk IMX8MM_CLK_IPG_ROOT>; 748 clock-names = "aclk", "ipg"; 749 750 sec_jr0: jr@1000 { 751 compatible = "fsl,sec-v4.0-job-ring"; 752 reg = <0x1000 0x1000>; 753 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 754 }; 755 756 sec_jr1: jr@2000 { 757 compatible = "fsl,sec-v4.0-job-ring"; 758 reg = <0x2000 0x1000>; 759 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 760 }; 761 762 sec_jr2: jr@3000 { 763 compatible = "fsl,sec-v4.0-job-ring"; 764 reg = <0x3000 0x1000>; 765 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 766 }; 767 }; 768 769 i2c1: i2c@30a20000 { 770 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 reg = <0x30a20000 0x10000>; 774 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; 776 status = "disabled"; 777 }; 778 779 i2c2: i2c@30a30000 { 780 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 reg = <0x30a30000 0x10000>; 784 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; 786 status = "disabled"; 787 }; 788 789 i2c3: i2c@30a40000 { 790 #address-cells = <1>; 791 #size-cells = <0>; 792 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 793 reg = <0x30a40000 0x10000>; 794 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; 796 status = "disabled"; 797 }; 798 799 i2c4: i2c@30a50000 { 800 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 reg = <0x30a50000 0x10000>; 804 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; 806 status = "disabled"; 807 }; 808 809 uart4: serial@30a60000 { 810 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 811 reg = <0x30a60000 0x10000>; 812 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&clk IMX8MM_CLK_UART4_ROOT>, 814 <&clk IMX8MM_CLK_UART4_ROOT>; 815 clock-names = "ipg", "per"; 816 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 817 dma-names = "rx", "tx"; 818 status = "disabled"; 819 }; 820 821 mu: mailbox@30aa0000 { 822 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; 823 reg = <0x30aa0000 0x10000>; 824 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&clk IMX8MM_CLK_MU_ROOT>; 826 #mbox-cells = <2>; 827 }; 828 829 usdhc1: mmc@30b40000 { 830 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 831 reg = <0x30b40000 0x10000>; 832 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 834 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 835 <&clk IMX8MM_CLK_USDHC1_ROOT>; 836 clock-names = "ipg", "ahb", "per"; 837 fsl,tuning-start-tap = <20>; 838 fsl,tuning-step= <2>; 839 bus-width = <4>; 840 status = "disabled"; 841 }; 842 843 usdhc2: mmc@30b50000 { 844 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 845 reg = <0x30b50000 0x10000>; 846 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 848 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 849 <&clk IMX8MM_CLK_USDHC2_ROOT>; 850 clock-names = "ipg", "ahb", "per"; 851 fsl,tuning-start-tap = <20>; 852 fsl,tuning-step= <2>; 853 bus-width = <4>; 854 status = "disabled"; 855 }; 856 857 usdhc3: mmc@30b60000 { 858 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 859 reg = <0x30b60000 0x10000>; 860 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 862 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 863 <&clk IMX8MM_CLK_USDHC3_ROOT>; 864 clock-names = "ipg", "ahb", "per"; 865 fsl,tuning-start-tap = <20>; 866 fsl,tuning-step= <2>; 867 bus-width = <4>; 868 status = "disabled"; 869 }; 870 871 flexspi: spi@30bb0000 { 872 #address-cells = <1>; 873 #size-cells = <0>; 874 compatible = "nxp,imx8mm-fspi"; 875 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 876 reg-names = "fspi_base", "fspi_mmap"; 877 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, 879 <&clk IMX8MM_CLK_QSPI_ROOT>; 880 clock-names = "fspi", "fspi_en"; 881 status = "disabled"; 882 }; 883 884 sdma1: dma-controller@30bd0000 { 885 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 886 reg = <0x30bd0000 0x10000>; 887 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, 889 <&clk IMX8MM_CLK_AHB>; 890 clock-names = "ipg", "ahb"; 891 #dma-cells = <3>; 892 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 893 }; 894 895 fec1: ethernet@30be0000 { 896 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec"; 897 reg = <0x30be0000 0x10000>; 898 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 903 <&clk IMX8MM_CLK_ENET1_ROOT>, 904 <&clk IMX8MM_CLK_ENET_TIMER>, 905 <&clk IMX8MM_CLK_ENET_REF>, 906 <&clk IMX8MM_CLK_ENET_PHY_REF>; 907 clock-names = "ipg", "ahb", "ptp", 908 "enet_clk_ref", "enet_out"; 909 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 910 <&clk IMX8MM_CLK_ENET_TIMER>, 911 <&clk IMX8MM_CLK_ENET_REF>, 912 <&clk IMX8MM_CLK_ENET_TIMER>; 913 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 914 <&clk IMX8MM_SYS_PLL2_100M>, 915 <&clk IMX8MM_SYS_PLL2_125M>; 916 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; 917 fsl,num-tx-queues = <3>; 918 fsl,num-rx-queues = <3>; 919 status = "disabled"; 920 }; 921 922 }; 923 924 aips4: bus@32c00000 { 925 compatible = "fsl,aips-bus", "simple-bus"; 926 reg = <0x32c00000 0x400000>; 927 #address-cells = <1>; 928 #size-cells = <1>; 929 ranges = <0x32c00000 0x32c00000 0x400000>; 930 931 usbotg1: usb@32e40000 { 932 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 933 reg = <0x32e40000 0x200>; 934 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 936 clock-names = "usb1_ctrl_root_clk"; 937 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 938 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 939 fsl,usbphy = <&usbphynop1>; 940 fsl,usbmisc = <&usbmisc1 0>; 941 status = "disabled"; 942 }; 943 944 usbmisc1: usbmisc@32e40200 { 945 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 946 #index-cells = <1>; 947 reg = <0x32e40200 0x200>; 948 }; 949 950 usbotg2: usb@32e50000 { 951 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 952 reg = <0x32e50000 0x200>; 953 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 955 clock-names = "usb1_ctrl_root_clk"; 956 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 957 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 958 fsl,usbphy = <&usbphynop2>; 959 fsl,usbmisc = <&usbmisc2 0>; 960 status = "disabled"; 961 }; 962 963 usbmisc2: usbmisc@32e50200 { 964 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 965 #index-cells = <1>; 966 reg = <0x32e50200 0x200>; 967 }; 968 969 }; 970 971 dma_apbh: dma-controller@33000000 { 972 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 973 reg = <0x33000000 0x2000>; 974 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 978 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 979 #dma-cells = <1>; 980 dma-channels = <4>; 981 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 982 }; 983 984 gpmi: nand-controller@33002000{ 985 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; 986 #address-cells = <1>; 987 #size-cells = <1>; 988 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 989 reg-names = "gpmi-nand", "bch"; 990 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 991 interrupt-names = "bch"; 992 clocks = <&clk IMX8MM_CLK_NAND_ROOT>, 993 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 994 clock-names = "gpmi_io", "gpmi_bch_apb"; 995 dmas = <&dma_apbh 0>; 996 dma-names = "rx-tx"; 997 status = "disabled"; 998 }; 999 1000 gic: interrupt-controller@38800000 { 1001 compatible = "arm,gic-v3"; 1002 reg = <0x38800000 0x10000>, /* GIC Dist */ 1003 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ 1004 #interrupt-cells = <3>; 1005 interrupt-controller; 1006 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1007 }; 1008 1009 ddrc: memory-controller@3d400000 { 1010 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; 1011 reg = <0x3d400000 0x400000>; 1012 clock-names = "core", "pll", "alt", "apb"; 1013 clocks = <&clk IMX8MM_CLK_DRAM_CORE>, 1014 <&clk IMX8MM_DRAM_PLL>, 1015 <&clk IMX8MM_CLK_DRAM_ALT>, 1016 <&clk IMX8MM_CLK_DRAM_APB>; 1017 }; 1018 1019 ddr-pmu@3d800000 { 1020 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1021 reg = <0x3d800000 0x400000>; 1022 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1023 }; 1024 }; 1025}; 1026