1a05ea40eSJacky Bai// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2a05ea40eSJacky Bai/* 3a05ea40eSJacky Bai * Copyright 2019 NXP 4a05ea40eSJacky Bai */ 5a05ea40eSJacky Bai 6a05ea40eSJacky Bai#include <dt-bindings/clock/imx8mm-clock.h> 7a05ea40eSJacky Bai#include <dt-bindings/gpio/gpio.h> 8a05ea40eSJacky Bai#include <dt-bindings/input/input.h> 9a05ea40eSJacky Bai#include <dt-bindings/interrupt-controller/arm-gic.h> 10a05ea40eSJacky Bai#include <dt-bindings/thermal/thermal.h> 11a05ea40eSJacky Bai 12a05ea40eSJacky Bai#include "imx8mm-pinfunc.h" 13a05ea40eSJacky Bai 14a05ea40eSJacky Bai/ { 15a05ea40eSJacky Bai compatible = "fsl,imx8mm"; 16a05ea40eSJacky Bai interrupt-parent = <&gic>; 17a05ea40eSJacky Bai #address-cells = <2>; 18a05ea40eSJacky Bai #size-cells = <2>; 19a05ea40eSJacky Bai 20a05ea40eSJacky Bai aliases { 21a05ea40eSJacky Bai ethernet0 = &fec1; 22a05ea40eSJacky Bai i2c0 = &i2c1; 23a05ea40eSJacky Bai i2c1 = &i2c2; 24a05ea40eSJacky Bai i2c2 = &i2c3; 25a05ea40eSJacky Bai i2c3 = &i2c4; 26a05ea40eSJacky Bai serial0 = &uart1; 27a05ea40eSJacky Bai serial1 = &uart2; 28a05ea40eSJacky Bai serial2 = &uart3; 29a05ea40eSJacky Bai serial3 = &uart4; 30a05ea40eSJacky Bai spi0 = &ecspi1; 31a05ea40eSJacky Bai spi1 = &ecspi2; 32a05ea40eSJacky Bai spi2 = &ecspi3; 33a05ea40eSJacky Bai mmc0 = &usdhc1; 34a05ea40eSJacky Bai mmc1 = &usdhc2; 35a05ea40eSJacky Bai mmc2 = &usdhc3; 36a05ea40eSJacky Bai gpio0 = &gpio1; 37a05ea40eSJacky Bai gpio1 = &gpio2; 38a05ea40eSJacky Bai gpio2 = &gpio3; 39a05ea40eSJacky Bai gpio3 = &gpio4; 40a05ea40eSJacky Bai gpio4 = &gpio5; 41a05ea40eSJacky Bai }; 42a05ea40eSJacky Bai 43a05ea40eSJacky Bai cpus { 44a05ea40eSJacky Bai #address-cells = <1>; 45a05ea40eSJacky Bai #size-cells = <0>; 46a05ea40eSJacky Bai 47a05ea40eSJacky Bai A53_0: cpu@0 { 48a05ea40eSJacky Bai device_type = "cpu"; 49a05ea40eSJacky Bai compatible = "arm,cortex-a53"; 50a05ea40eSJacky Bai reg = <0x0>; 51a05ea40eSJacky Bai enable-method = "psci"; 52a05ea40eSJacky Bai next-level-cache = <&A53_L2>; 53a05ea40eSJacky Bai }; 54a05ea40eSJacky Bai 55a05ea40eSJacky Bai A53_1: cpu@1 { 56a05ea40eSJacky Bai device_type = "cpu"; 57a05ea40eSJacky Bai compatible = "arm,cortex-a53"; 58a05ea40eSJacky Bai reg = <0x1>; 59a05ea40eSJacky Bai enable-method = "psci"; 60a05ea40eSJacky Bai next-level-cache = <&A53_L2>; 61a05ea40eSJacky Bai }; 62a05ea40eSJacky Bai 63a05ea40eSJacky Bai A53_2: cpu@2 { 64a05ea40eSJacky Bai device_type = "cpu"; 65a05ea40eSJacky Bai compatible = "arm,cortex-a53"; 66a05ea40eSJacky Bai reg = <0x2>; 67a05ea40eSJacky Bai enable-method = "psci"; 68a05ea40eSJacky Bai next-level-cache = <&A53_L2>; 69a05ea40eSJacky Bai }; 70a05ea40eSJacky Bai 71a05ea40eSJacky Bai A53_3: cpu@3 { 72a05ea40eSJacky Bai device_type = "cpu"; 73a05ea40eSJacky Bai compatible = "arm,cortex-a53"; 74a05ea40eSJacky Bai reg = <0x3>; 75a05ea40eSJacky Bai enable-method = "psci"; 76a05ea40eSJacky Bai next-level-cache = <&A53_L2>; 77a05ea40eSJacky Bai }; 78a05ea40eSJacky Bai 79a05ea40eSJacky Bai A53_L2: l2-cache0 { 80a05ea40eSJacky Bai compatible = "cache"; 81a05ea40eSJacky Bai }; 82a05ea40eSJacky Bai }; 83a05ea40eSJacky Bai 84a05ea40eSJacky Bai memory@40000000 { 85a05ea40eSJacky Bai device_type = "memory"; 86a05ea40eSJacky Bai reg = <0x0 0x40000000 0 0x80000000>; 87a05ea40eSJacky Bai }; 88a05ea40eSJacky Bai 89a05ea40eSJacky Bai osc_32k: clock-osc-32k { 90a05ea40eSJacky Bai compatible = "fixed-clock"; 91a05ea40eSJacky Bai #clock-cells = <0>; 92a05ea40eSJacky Bai clock-frequency = <32768>; 93a05ea40eSJacky Bai clock-output-names = "osc_32k"; 94a05ea40eSJacky Bai }; 95a05ea40eSJacky Bai 96a05ea40eSJacky Bai osc_24m: clock-osc-24m { 97a05ea40eSJacky Bai compatible = "fixed-clock"; 98a05ea40eSJacky Bai #clock-cells = <0>; 99a05ea40eSJacky Bai clock-frequency = <24000000>; 100a05ea40eSJacky Bai clock-output-names = "osc_24m"; 101a05ea40eSJacky Bai }; 102a05ea40eSJacky Bai 103a05ea40eSJacky Bai clk_ext1: clock-ext1 { 104a05ea40eSJacky Bai compatible = "fixed-clock"; 105a05ea40eSJacky Bai #clock-cells = <0>; 106a05ea40eSJacky Bai clock-frequency = <133000000>; 107a05ea40eSJacky Bai clock-output-names = "clk_ext1"; 108a05ea40eSJacky Bai }; 109a05ea40eSJacky Bai 110a05ea40eSJacky Bai clk_ext2: clock-ext2 { 111a05ea40eSJacky Bai compatible = "fixed-clock"; 112a05ea40eSJacky Bai #clock-cells = <0>; 113a05ea40eSJacky Bai clock-frequency = <133000000>; 114a05ea40eSJacky Bai clock-output-names = "clk_ext2"; 115a05ea40eSJacky Bai }; 116a05ea40eSJacky Bai 117a05ea40eSJacky Bai clk_ext3: clock-ext3 { 118a05ea40eSJacky Bai compatible = "fixed-clock"; 119a05ea40eSJacky Bai #clock-cells = <0>; 120a05ea40eSJacky Bai clock-frequency = <133000000>; 121a05ea40eSJacky Bai clock-output-names = "clk_ext3"; 122a05ea40eSJacky Bai }; 123a05ea40eSJacky Bai 124a05ea40eSJacky Bai clk_ext4: clock-ext4 { 125a05ea40eSJacky Bai compatible = "fixed-clock"; 126a05ea40eSJacky Bai #clock-cells = <0>; 127a05ea40eSJacky Bai clock-frequency= <133000000>; 128a05ea40eSJacky Bai clock-output-names = "clk_ext4"; 129a05ea40eSJacky Bai }; 130a05ea40eSJacky Bai 131a05ea40eSJacky Bai gic: interrupt-controller@38800000 { 132a05ea40eSJacky Bai compatible = "arm,gic-v3"; 133a05ea40eSJacky Bai reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ 134a05ea40eSJacky Bai <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ 135a05ea40eSJacky Bai #interrupt-cells = <3>; 136a05ea40eSJacky Bai interrupt-controller; 137a05ea40eSJacky Bai interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 138a05ea40eSJacky Bai }; 139a05ea40eSJacky Bai 140a05ea40eSJacky Bai psci { 141a05ea40eSJacky Bai compatible = "arm,psci-1.0"; 142a05ea40eSJacky Bai method = "smc"; 143a05ea40eSJacky Bai }; 144a05ea40eSJacky Bai 145a05ea40eSJacky Bai pmu { 146a05ea40eSJacky Bai compatible = "arm,armv8-pmuv3"; 147a05ea40eSJacky Bai interrupts = <GIC_PPI 7 148a05ea40eSJacky Bai (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 149a05ea40eSJacky Bai interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; 150a05ea40eSJacky Bai }; 151a05ea40eSJacky Bai 152a05ea40eSJacky Bai timer { 153a05ea40eSJacky Bai compatible = "arm,armv8-timer"; 154a05ea40eSJacky Bai interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 155a05ea40eSJacky Bai <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 156a05ea40eSJacky Bai <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 157a05ea40eSJacky Bai <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 158a05ea40eSJacky Bai clock-frequency = <8000000>; 159a05ea40eSJacky Bai arm,no-tick-in-suspend; 160a05ea40eSJacky Bai }; 161a05ea40eSJacky Bai 162a05ea40eSJacky Bai soc { 163a05ea40eSJacky Bai compatible = "simple-bus"; 164a05ea40eSJacky Bai #address-cells = <1>; 165a05ea40eSJacky Bai #size-cells = <1>; 166a05ea40eSJacky Bai ranges = <0x0 0x0 0x0 0x3e000000>; 167a05ea40eSJacky Bai 168a05ea40eSJacky Bai aips1: bus@30000000 { 169a05ea40eSJacky Bai compatible = "fsl,aips-bus", "simple-bus"; 170a05ea40eSJacky Bai #address-cells = <1>; 171a05ea40eSJacky Bai #size-cells = <1>; 172a05ea40eSJacky Bai ranges; 173a05ea40eSJacky Bai 174a05ea40eSJacky Bai gpio1: gpio@30200000 { 175a05ea40eSJacky Bai compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 176a05ea40eSJacky Bai reg = <0x30200000 0x10000>; 177a05ea40eSJacky Bai interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 178a05ea40eSJacky Bai <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 179a05ea40eSJacky Bai gpio-controller; 180a05ea40eSJacky Bai #gpio-cells = <2>; 181a05ea40eSJacky Bai interrupt-controller; 182a05ea40eSJacky Bai #interrupt-cells = <2>; 183a05ea40eSJacky Bai }; 184a05ea40eSJacky Bai 185a05ea40eSJacky Bai gpio2: gpio@30210000 { 186a05ea40eSJacky Bai compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 187a05ea40eSJacky Bai reg = <0x30210000 0x10000>; 188a05ea40eSJacky Bai interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 189a05ea40eSJacky Bai <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 190a05ea40eSJacky Bai gpio-controller; 191a05ea40eSJacky Bai #gpio-cells = <2>; 192a05ea40eSJacky Bai interrupt-controller; 193a05ea40eSJacky Bai #interrupt-cells = <2>; 194a05ea40eSJacky Bai }; 195a05ea40eSJacky Bai 196a05ea40eSJacky Bai gpio3: gpio@30220000 { 197a05ea40eSJacky Bai compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 198a05ea40eSJacky Bai reg = <0x30220000 0x10000>; 199a05ea40eSJacky Bai interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 200a05ea40eSJacky Bai <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 201a05ea40eSJacky Bai gpio-controller; 202a05ea40eSJacky Bai #gpio-cells = <2>; 203a05ea40eSJacky Bai interrupt-controller; 204a05ea40eSJacky Bai #interrupt-cells = <2>; 205a05ea40eSJacky Bai }; 206a05ea40eSJacky Bai 207a05ea40eSJacky Bai gpio4: gpio@30230000 { 208a05ea40eSJacky Bai compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 209a05ea40eSJacky Bai reg = <0x30230000 0x10000>; 210a05ea40eSJacky Bai interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 211a05ea40eSJacky Bai <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 212a05ea40eSJacky Bai gpio-controller; 213a05ea40eSJacky Bai #gpio-cells = <2>; 214a05ea40eSJacky Bai interrupt-controller; 215a05ea40eSJacky Bai #interrupt-cells = <2>; 216a05ea40eSJacky Bai }; 217a05ea40eSJacky Bai 218a05ea40eSJacky Bai gpio5: gpio@30240000 { 219a05ea40eSJacky Bai compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 220a05ea40eSJacky Bai reg = <0x30240000 0x10000>; 221a05ea40eSJacky Bai interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 222a05ea40eSJacky Bai <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 223a05ea40eSJacky Bai gpio-controller; 224a05ea40eSJacky Bai #gpio-cells = <2>; 225a05ea40eSJacky Bai interrupt-controller; 226a05ea40eSJacky Bai #interrupt-cells = <2>; 227a05ea40eSJacky Bai }; 228a05ea40eSJacky Bai 229a05ea40eSJacky Bai wdog1: watchdog@30280000 { 230a05ea40eSJacky Bai compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 231a05ea40eSJacky Bai reg = <0x30280000 0x10000>; 232a05ea40eSJacky Bai interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 233a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; 234a05ea40eSJacky Bai status = "disabled"; 235a05ea40eSJacky Bai }; 236a05ea40eSJacky Bai 237a05ea40eSJacky Bai wdog2: watchdog@30290000 { 238a05ea40eSJacky Bai compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 239a05ea40eSJacky Bai reg = <0x30290000 0x10000>; 240a05ea40eSJacky Bai interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 241a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; 242a05ea40eSJacky Bai status = "disabled"; 243a05ea40eSJacky Bai }; 244a05ea40eSJacky Bai 245a05ea40eSJacky Bai wdog3: watchdog@302a0000 { 246a05ea40eSJacky Bai compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 247a05ea40eSJacky Bai reg = <0x302a0000 0x10000>; 248a05ea40eSJacky Bai interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 249a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; 250a05ea40eSJacky Bai status = "disabled"; 251a05ea40eSJacky Bai }; 252a05ea40eSJacky Bai 253a05ea40eSJacky Bai sdma2: dma-controller@302c0000 { 254a05ea40eSJacky Bai compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; 255a05ea40eSJacky Bai reg = <0x302c0000 0x10000>; 256a05ea40eSJacky Bai interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 257a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, 258a05ea40eSJacky Bai <&clk IMX8MM_CLK_SDMA2_ROOT>; 259a05ea40eSJacky Bai clock-names = "ipg", "ahb"; 260a05ea40eSJacky Bai #dma-cells = <3>; 261a05ea40eSJacky Bai fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 262a05ea40eSJacky Bai }; 263a05ea40eSJacky Bai 264a05ea40eSJacky Bai sdma3: dma-controller@302b0000 { 265a05ea40eSJacky Bai compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; 266a05ea40eSJacky Bai reg = <0x302b0000 0x10000>; 267a05ea40eSJacky Bai interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 268a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, 269a05ea40eSJacky Bai <&clk IMX8MM_CLK_SDMA3_ROOT>; 270a05ea40eSJacky Bai clock-names = "ipg", "ahb"; 271a05ea40eSJacky Bai #dma-cells = <3>; 272a05ea40eSJacky Bai fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 273a05ea40eSJacky Bai }; 274a05ea40eSJacky Bai 275a05ea40eSJacky Bai iomuxc: pinctrl@30330000 { 276a05ea40eSJacky Bai compatible = "fsl,imx8mm-iomuxc"; 277a05ea40eSJacky Bai reg = <0x30330000 0x10000>; 278a05ea40eSJacky Bai }; 279a05ea40eSJacky Bai 280a05ea40eSJacky Bai gpr: iomuxc-gpr@30340000 { 281a05ea40eSJacky Bai compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; 282a05ea40eSJacky Bai reg = <0x30340000 0x10000>; 283a05ea40eSJacky Bai }; 284a05ea40eSJacky Bai 285a05ea40eSJacky Bai ocotp: ocotp-ctrl@30350000 { 286a05ea40eSJacky Bai compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon"; 287a05ea40eSJacky Bai reg = <0x30350000 0x10000>; 288a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; 289a05ea40eSJacky Bai /* For nvmem subnodes */ 290a05ea40eSJacky Bai #address-cells = <1>; 291a05ea40eSJacky Bai #size-cells = <1>; 292a05ea40eSJacky Bai }; 293a05ea40eSJacky Bai 294a05ea40eSJacky Bai anatop: anatop@30360000 { 295a05ea40eSJacky Bai compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus"; 296a05ea40eSJacky Bai reg = <0x30360000 0x10000>; 297a05ea40eSJacky Bai }; 298a05ea40eSJacky Bai 299a05ea40eSJacky Bai snvs: snvs@30370000 { 300a05ea40eSJacky Bai compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 301a05ea40eSJacky Bai reg = <0x30370000 0x10000>; 302a05ea40eSJacky Bai 303a05ea40eSJacky Bai snvs_rtc: snvs-rtc-lp { 304a05ea40eSJacky Bai compatible = "fsl,sec-v4.0-mon-rtc-lp"; 305a05ea40eSJacky Bai regmap = <&snvs>; 306a05ea40eSJacky Bai offset = <0x34>; 307a05ea40eSJacky Bai interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 308a05ea40eSJacky Bai <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 309a05ea40eSJacky Bai }; 310a05ea40eSJacky Bai 311a05ea40eSJacky Bai snvs_pwrkey: snvs-powerkey { 312a05ea40eSJacky Bai compatible = "fsl,sec-v4.0-pwrkey"; 313a05ea40eSJacky Bai regmap = <&snvs>; 314a05ea40eSJacky Bai interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 315a05ea40eSJacky Bai linux,keycode = <KEY_POWER>; 316a05ea40eSJacky Bai wakeup-source; 317a05ea40eSJacky Bai }; 318a05ea40eSJacky Bai }; 319a05ea40eSJacky Bai 320a05ea40eSJacky Bai clk: clock-controller@30380000 { 321a05ea40eSJacky Bai compatible = "fsl,imx8mm-ccm"; 322a05ea40eSJacky Bai reg = <0x30380000 0x10000>; 323a05ea40eSJacky Bai #clock-cells = <1>; 324a05ea40eSJacky Bai clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 325a05ea40eSJacky Bai <&clk_ext3>, <&clk_ext4>; 326a05ea40eSJacky Bai clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 327a05ea40eSJacky Bai "clk_ext3", "clk_ext4"; 328a05ea40eSJacky Bai }; 329a05ea40eSJacky Bai 330a05ea40eSJacky Bai src: reset-controller@30390000 { 331a05ea40eSJacky Bai compatible = "fsl,imx8mm-src", "syscon"; 332a05ea40eSJacky Bai reg = <0x30390000 0x10000>; 333a05ea40eSJacky Bai interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 334a05ea40eSJacky Bai #reset-cells = <1>; 335a05ea40eSJacky Bai }; 336a05ea40eSJacky Bai }; 337a05ea40eSJacky Bai 338a05ea40eSJacky Bai aips2: bus@30400000 { 339a05ea40eSJacky Bai compatible = "fsl,aips-bus", "simple-bus"; 340a05ea40eSJacky Bai #address-cells = <1>; 341a05ea40eSJacky Bai #size-cells = <1>; 342a05ea40eSJacky Bai ranges; 343a05ea40eSJacky Bai 344a05ea40eSJacky Bai pwm1: pwm@30660000 { 345a05ea40eSJacky Bai compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 346a05ea40eSJacky Bai reg = <0x30660000 0x10000>; 347a05ea40eSJacky Bai interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 348a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, 349a05ea40eSJacky Bai <&clk IMX8MM_CLK_PWM1_ROOT>; 350a05ea40eSJacky Bai clock-names = "ipg", "per"; 351a05ea40eSJacky Bai #pwm-cells = <2>; 352a05ea40eSJacky Bai status = "disabled"; 353a05ea40eSJacky Bai }; 354a05ea40eSJacky Bai 355a05ea40eSJacky Bai pwm2: pwm@30670000 { 356a05ea40eSJacky Bai compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 357a05ea40eSJacky Bai reg = <0x30670000 0x10000>; 358a05ea40eSJacky Bai interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 359a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, 360a05ea40eSJacky Bai <&clk IMX8MM_CLK_PWM2_ROOT>; 361a05ea40eSJacky Bai clock-names = "ipg", "per"; 362a05ea40eSJacky Bai #pwm-cells = <2>; 363a05ea40eSJacky Bai status = "disabled"; 364a05ea40eSJacky Bai }; 365a05ea40eSJacky Bai 366a05ea40eSJacky Bai pwm3: pwm@30680000 { 367a05ea40eSJacky Bai compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 368a05ea40eSJacky Bai reg = <0x30680000 0x10000>; 369a05ea40eSJacky Bai interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 370a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, 371a05ea40eSJacky Bai <&clk IMX8MM_CLK_PWM3_ROOT>; 372a05ea40eSJacky Bai clock-names = "ipg", "per"; 373a05ea40eSJacky Bai #pwm-cells = <2>; 374a05ea40eSJacky Bai status = "disabled"; 375a05ea40eSJacky Bai }; 376a05ea40eSJacky Bai 377a05ea40eSJacky Bai pwm4: pwm@30690000 { 378a05ea40eSJacky Bai compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 379a05ea40eSJacky Bai reg = <0x30690000 0x10000>; 380a05ea40eSJacky Bai interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 381a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, 382a05ea40eSJacky Bai <&clk IMX8MM_CLK_PWM4_ROOT>; 383a05ea40eSJacky Bai clock-names = "ipg", "per"; 384a05ea40eSJacky Bai #pwm-cells = <2>; 385a05ea40eSJacky Bai status = "disabled"; 386a05ea40eSJacky Bai }; 387a05ea40eSJacky Bai }; 388a05ea40eSJacky Bai 389a05ea40eSJacky Bai aips3: bus@30800000 { 390a05ea40eSJacky Bai compatible = "fsl,aips-bus", "simple-bus"; 391a05ea40eSJacky Bai #address-cells = <1>; 392a05ea40eSJacky Bai #size-cells = <1>; 393a05ea40eSJacky Bai ranges; 394a05ea40eSJacky Bai 395a05ea40eSJacky Bai ecspi1: spi@30820000 { 396a05ea40eSJacky Bai compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 397a05ea40eSJacky Bai #address-cells = <1>; 398a05ea40eSJacky Bai #size-cells = <0>; 399a05ea40eSJacky Bai reg = <0x30820000 0x10000>; 400a05ea40eSJacky Bai interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 401a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, 402a05ea40eSJacky Bai <&clk IMX8MM_CLK_ECSPI1_ROOT>; 403a05ea40eSJacky Bai clock-names = "ipg", "per"; 404a05ea40eSJacky Bai dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 405a05ea40eSJacky Bai dma-names = "rx", "tx"; 406a05ea40eSJacky Bai status = "disabled"; 407a05ea40eSJacky Bai }; 408a05ea40eSJacky Bai 409a05ea40eSJacky Bai ecspi2: spi@30830000 { 410a05ea40eSJacky Bai compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 411a05ea40eSJacky Bai #address-cells = <1>; 412a05ea40eSJacky Bai #size-cells = <0>; 413a05ea40eSJacky Bai reg = <0x30830000 0x10000>; 414a05ea40eSJacky Bai interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 415a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, 416a05ea40eSJacky Bai <&clk IMX8MM_CLK_ECSPI2_ROOT>; 417a05ea40eSJacky Bai clock-names = "ipg", "per"; 418a05ea40eSJacky Bai dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 419a05ea40eSJacky Bai dma-names = "rx", "tx"; 420a05ea40eSJacky Bai status = "disabled"; 421a05ea40eSJacky Bai }; 422a05ea40eSJacky Bai 423a05ea40eSJacky Bai ecspi3: spi@30840000 { 424a05ea40eSJacky Bai compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 425a05ea40eSJacky Bai #address-cells = <1>; 426a05ea40eSJacky Bai #size-cells = <0>; 427a05ea40eSJacky Bai reg = <0x30840000 0x10000>; 428a05ea40eSJacky Bai interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 429a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, 430a05ea40eSJacky Bai <&clk IMX8MM_CLK_ECSPI3_ROOT>; 431a05ea40eSJacky Bai clock-names = "ipg", "per"; 432a05ea40eSJacky Bai dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 433a05ea40eSJacky Bai dma-names = "rx", "tx"; 434a05ea40eSJacky Bai status = "disabled"; 435a05ea40eSJacky Bai }; 436a05ea40eSJacky Bai 437a05ea40eSJacky Bai uart1: serial@30860000 { 438a05ea40eSJacky Bai compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 439a05ea40eSJacky Bai reg = <0x30860000 0x10000>; 440a05ea40eSJacky Bai interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 441a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_UART1_ROOT>, 442a05ea40eSJacky Bai <&clk IMX8MM_CLK_UART1_ROOT>; 443a05ea40eSJacky Bai clock-names = "ipg", "per"; 444a05ea40eSJacky Bai dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 445a05ea40eSJacky Bai dma-names = "rx", "tx"; 446a05ea40eSJacky Bai status = "disabled"; 447a05ea40eSJacky Bai }; 448a05ea40eSJacky Bai 449a05ea40eSJacky Bai uart3: serial@30880000 { 450a05ea40eSJacky Bai compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 451a05ea40eSJacky Bai reg = <0x30880000 0x10000>; 452a05ea40eSJacky Bai interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 453a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_UART3_ROOT>, 454a05ea40eSJacky Bai <&clk IMX8MM_CLK_UART3_ROOT>; 455a05ea40eSJacky Bai clock-names = "ipg", "per"; 456a05ea40eSJacky Bai dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 457a05ea40eSJacky Bai dma-names = "rx", "tx"; 458a05ea40eSJacky Bai status = "disabled"; 459a05ea40eSJacky Bai }; 460a05ea40eSJacky Bai 461a05ea40eSJacky Bai uart2: serial@30890000 { 462a05ea40eSJacky Bai compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 463a05ea40eSJacky Bai reg = <0x30890000 0x10000>; 464a05ea40eSJacky Bai interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 465a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_UART2_ROOT>, 466a05ea40eSJacky Bai <&clk IMX8MM_CLK_UART2_ROOT>; 467a05ea40eSJacky Bai clock-names = "ipg", "per"; 468a05ea40eSJacky Bai status = "disabled"; 469a05ea40eSJacky Bai }; 470a05ea40eSJacky Bai 471a05ea40eSJacky Bai i2c1: i2c@30a20000 { 472a05ea40eSJacky Bai compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 473a05ea40eSJacky Bai #address-cells = <1>; 474a05ea40eSJacky Bai #size-cells = <0>; 475a05ea40eSJacky Bai reg = <0x30a20000 0x10000>; 476a05ea40eSJacky Bai interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 477a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; 478a05ea40eSJacky Bai status = "disabled"; 479a05ea40eSJacky Bai }; 480a05ea40eSJacky Bai 481a05ea40eSJacky Bai i2c2: i2c@30a30000 { 482a05ea40eSJacky Bai compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 483a05ea40eSJacky Bai #address-cells = <1>; 484a05ea40eSJacky Bai #size-cells = <0>; 485a05ea40eSJacky Bai reg = <0x30a30000 0x10000>; 486a05ea40eSJacky Bai interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 487a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; 488a05ea40eSJacky Bai status = "disabled"; 489a05ea40eSJacky Bai }; 490a05ea40eSJacky Bai 491a05ea40eSJacky Bai i2c3: i2c@30a40000 { 492a05ea40eSJacky Bai #address-cells = <1>; 493a05ea40eSJacky Bai #size-cells = <0>; 494a05ea40eSJacky Bai compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 495a05ea40eSJacky Bai reg = <0x30a40000 0x10000>; 496a05ea40eSJacky Bai interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 497a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; 498a05ea40eSJacky Bai status = "disabled"; 499a05ea40eSJacky Bai }; 500a05ea40eSJacky Bai 501a05ea40eSJacky Bai i2c4: i2c@30a50000 { 502a05ea40eSJacky Bai compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 503a05ea40eSJacky Bai #address-cells = <1>; 504a05ea40eSJacky Bai #size-cells = <0>; 505a05ea40eSJacky Bai reg = <0x30a50000 0x10000>; 506a05ea40eSJacky Bai interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 507a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; 508a05ea40eSJacky Bai status = "disabled"; 509a05ea40eSJacky Bai }; 510a05ea40eSJacky Bai 511a05ea40eSJacky Bai uart4: serial@30a60000 { 512a05ea40eSJacky Bai compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 513a05ea40eSJacky Bai reg = <0x30a60000 0x10000>; 514a05ea40eSJacky Bai interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 515a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_UART4_ROOT>, 516a05ea40eSJacky Bai <&clk IMX8MM_CLK_UART4_ROOT>; 517a05ea40eSJacky Bai clock-names = "ipg", "per"; 518a05ea40eSJacky Bai dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 519a05ea40eSJacky Bai dma-names = "rx", "tx"; 520a05ea40eSJacky Bai status = "disabled"; 521a05ea40eSJacky Bai }; 522a05ea40eSJacky Bai 523a05ea40eSJacky Bai usdhc1: mmc@30b40000 { 524a05ea40eSJacky Bai compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 525a05ea40eSJacky Bai reg = <0x30b40000 0x10000>; 526a05ea40eSJacky Bai interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 527a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_DUMMY>, 528a05ea40eSJacky Bai <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 529a05ea40eSJacky Bai <&clk IMX8MM_CLK_USDHC1_ROOT>; 530a05ea40eSJacky Bai clock-names = "ipg", "ahb", "per"; 531a05ea40eSJacky Bai assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; 532a05ea40eSJacky Bai assigned-clock-rates = <400000000>; 533a05ea40eSJacky Bai fsl,tuning-start-tap = <20>; 534a05ea40eSJacky Bai fsl,tuning-step= <2>; 535a05ea40eSJacky Bai bus-width = <4>; 536a05ea40eSJacky Bai status = "disabled"; 537a05ea40eSJacky Bai }; 538a05ea40eSJacky Bai 539a05ea40eSJacky Bai usdhc2: mmc@30b50000 { 540a05ea40eSJacky Bai compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 541a05ea40eSJacky Bai reg = <0x30b50000 0x10000>; 542a05ea40eSJacky Bai interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 543a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_DUMMY>, 544a05ea40eSJacky Bai <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 545a05ea40eSJacky Bai <&clk IMX8MM_CLK_USDHC2_ROOT>; 546a05ea40eSJacky Bai clock-names = "ipg", "ahb", "per"; 547a05ea40eSJacky Bai fsl,tuning-start-tap = <20>; 548a05ea40eSJacky Bai fsl,tuning-step= <2>; 549a05ea40eSJacky Bai bus-width = <4>; 550a05ea40eSJacky Bai status = "disabled"; 551a05ea40eSJacky Bai }; 552a05ea40eSJacky Bai 553a05ea40eSJacky Bai usdhc3: mmc@30b60000 { 554a05ea40eSJacky Bai compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 555a05ea40eSJacky Bai reg = <0x30b60000 0x10000>; 556a05ea40eSJacky Bai interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 557a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_DUMMY>, 558a05ea40eSJacky Bai <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 559a05ea40eSJacky Bai <&clk IMX8MM_CLK_USDHC3_ROOT>; 560a05ea40eSJacky Bai clock-names = "ipg", "ahb", "per"; 561a05ea40eSJacky Bai assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 562a05ea40eSJacky Bai assigned-clock-rates = <400000000>; 563a05ea40eSJacky Bai fsl,tuning-start-tap = <20>; 564a05ea40eSJacky Bai fsl,tuning-step= <2>; 565a05ea40eSJacky Bai bus-width = <4>; 566a05ea40eSJacky Bai status = "disabled"; 567a05ea40eSJacky Bai }; 568a05ea40eSJacky Bai 569a05ea40eSJacky Bai sdma1: dma-controller@30bd0000 { 570a05ea40eSJacky Bai compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; 571a05ea40eSJacky Bai reg = <0x30bd0000 0x10000>; 572a05ea40eSJacky Bai interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 573a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, 574a05ea40eSJacky Bai <&clk IMX8MM_CLK_SDMA1_ROOT>; 575a05ea40eSJacky Bai clock-names = "ipg", "ahb"; 576a05ea40eSJacky Bai #dma-cells = <3>; 577a05ea40eSJacky Bai fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 578a05ea40eSJacky Bai }; 579a05ea40eSJacky Bai 580a05ea40eSJacky Bai fec1: ethernet@30be0000 { 581a05ea40eSJacky Bai compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec"; 582a05ea40eSJacky Bai reg = <0x30be0000 0x10000>; 583a05ea40eSJacky Bai interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 584a05ea40eSJacky Bai <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 585a05ea40eSJacky Bai <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 586a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 587a05ea40eSJacky Bai <&clk IMX8MM_CLK_ENET1_ROOT>, 588a05ea40eSJacky Bai <&clk IMX8MM_CLK_ENET_TIMER>, 589a05ea40eSJacky Bai <&clk IMX8MM_CLK_ENET_REF>, 590a05ea40eSJacky Bai <&clk IMX8MM_CLK_ENET_PHY_REF>; 591a05ea40eSJacky Bai clock-names = "ipg", "ahb", "ptp", 592a05ea40eSJacky Bai "enet_clk_ref", "enet_out"; 593a05ea40eSJacky Bai assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 594a05ea40eSJacky Bai <&clk IMX8MM_CLK_ENET_TIMER>, 595a05ea40eSJacky Bai <&clk IMX8MM_CLK_ENET_REF>, 596a05ea40eSJacky Bai <&clk IMX8MM_CLK_ENET_TIMER>; 597a05ea40eSJacky Bai assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 598a05ea40eSJacky Bai <&clk IMX8MM_SYS_PLL2_100M>, 599a05ea40eSJacky Bai <&clk IMX8MM_SYS_PLL2_125M>; 600a05ea40eSJacky Bai assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; 601a05ea40eSJacky Bai fsl,num-tx-queues = <3>; 602a05ea40eSJacky Bai fsl,num-rx-queues = <3>; 603a05ea40eSJacky Bai status = "disabled"; 604a05ea40eSJacky Bai }; 605a05ea40eSJacky Bai 606a05ea40eSJacky Bai }; 607a05ea40eSJacky Bai 608a05ea40eSJacky Bai aips4: bus@32c00000 { 609a05ea40eSJacky Bai compatible = "fsl,aips-bus", "simple-bus"; 610a05ea40eSJacky Bai #address-cells = <1>; 611a05ea40eSJacky Bai #size-cells = <1>; 612a05ea40eSJacky Bai ranges; 613a05ea40eSJacky Bai 614a05ea40eSJacky Bai usbotg1: usb@32e40000 { 615a05ea40eSJacky Bai compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 616a05ea40eSJacky Bai reg = <0x32e40000 0x200>; 617a05ea40eSJacky Bai interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 618a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 619a05ea40eSJacky Bai clock-names = "usb1_ctrl_root_clk"; 620a05ea40eSJacky Bai assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>, 621a05ea40eSJacky Bai <&clk IMX8MM_CLK_USB_CORE_REF>; 622a05ea40eSJacky Bai assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, 623a05ea40eSJacky Bai <&clk IMX8MM_SYS_PLL1_100M>; 624a05ea40eSJacky Bai fsl,usbphy = <&usbphynop1>; 625a05ea40eSJacky Bai fsl,usbmisc = <&usbmisc1 0>; 626a05ea40eSJacky Bai status = "disabled"; 627a05ea40eSJacky Bai }; 628a05ea40eSJacky Bai 629a05ea40eSJacky Bai usbphynop1: usbphynop1 { 630a05ea40eSJacky Bai compatible = "usb-nop-xceiv"; 631a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 632a05ea40eSJacky Bai assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 633a05ea40eSJacky Bai assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 634a05ea40eSJacky Bai clock-names = "main_clk"; 635a05ea40eSJacky Bai }; 636a05ea40eSJacky Bai 637a05ea40eSJacky Bai usbmisc1: usbmisc@32e40200 { 638a05ea40eSJacky Bai compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 639a05ea40eSJacky Bai #index-cells = <1>; 640a05ea40eSJacky Bai reg = <0x32e40200 0x200>; 641a05ea40eSJacky Bai }; 642a05ea40eSJacky Bai 643a05ea40eSJacky Bai usbotg2: usb@32e50000 { 644a05ea40eSJacky Bai compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 645a05ea40eSJacky Bai reg = <0x32e50000 0x200>; 646a05ea40eSJacky Bai interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 647a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 648a05ea40eSJacky Bai clock-names = "usb1_ctrl_root_clk"; 649a05ea40eSJacky Bai assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>, 650a05ea40eSJacky Bai <&clk IMX8MM_CLK_USB_CORE_REF>; 651a05ea40eSJacky Bai assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, 652a05ea40eSJacky Bai <&clk IMX8MM_SYS_PLL1_100M>; 653a05ea40eSJacky Bai fsl,usbphy = <&usbphynop2>; 654a05ea40eSJacky Bai fsl,usbmisc = <&usbmisc2 0>; 655a05ea40eSJacky Bai status = "disabled"; 656a05ea40eSJacky Bai }; 657a05ea40eSJacky Bai 658a05ea40eSJacky Bai usbphynop2: usbphynop2 { 659a05ea40eSJacky Bai compatible = "usb-nop-xceiv"; 660a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 661a05ea40eSJacky Bai assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 662a05ea40eSJacky Bai assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 663a05ea40eSJacky Bai clock-names = "main_clk"; 664a05ea40eSJacky Bai }; 665a05ea40eSJacky Bai 666a05ea40eSJacky Bai usbmisc2: usbmisc@32e50200 { 667a05ea40eSJacky Bai compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 668a05ea40eSJacky Bai #index-cells = <1>; 669a05ea40eSJacky Bai reg = <0x32e50200 0x200>; 670a05ea40eSJacky Bai }; 671a05ea40eSJacky Bai 672a05ea40eSJacky Bai }; 673a05ea40eSJacky Bai 674a05ea40eSJacky Bai dma_apbh: dma-controller@33000000 { 675a05ea40eSJacky Bai compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 676a05ea40eSJacky Bai reg = <0x33000000 0x2000>; 677a05ea40eSJacky Bai interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 678a05ea40eSJacky Bai <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 679a05ea40eSJacky Bai <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 680a05ea40eSJacky Bai <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 681a05ea40eSJacky Bai interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 682a05ea40eSJacky Bai #dma-cells = <1>; 683a05ea40eSJacky Bai dma-channels = <4>; 684a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 685a05ea40eSJacky Bai }; 686a05ea40eSJacky Bai 687a05ea40eSJacky Bai gpmi: nand-controller@33002000{ 688a05ea40eSJacky Bai compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; 689a05ea40eSJacky Bai #address-cells = <1>; 690a05ea40eSJacky Bai #size-cells = <1>; 691a05ea40eSJacky Bai reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 692a05ea40eSJacky Bai reg-names = "gpmi-nand", "bch"; 693a05ea40eSJacky Bai interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 694a05ea40eSJacky Bai interrupt-names = "bch"; 695a05ea40eSJacky Bai clocks = <&clk IMX8MM_CLK_NAND_ROOT>, 696a05ea40eSJacky Bai <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 697a05ea40eSJacky Bai clock-names = "gpmi_io", "gpmi_bch_apb"; 698a05ea40eSJacky Bai dmas = <&dma_apbh 0>; 699a05ea40eSJacky Bai dma-names = "rx-tx"; 700a05ea40eSJacky Bai status = "disabled"; 701a05ea40eSJacky Bai }; 702a05ea40eSJacky Bai }; 703a05ea40eSJacky Bai}; 704