1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include "dt-bindings/phy/phy-imx8-pcie.h" 7#include "dt-bindings/pwm/pwm.h" 8#include "imx8mm.dtsi" 9 10/ { 11 chosen { 12 stdout-path = &uart1; 13 }; 14 15 aliases { 16 rtc0 = &rtc_i2c; 17 rtc1 = &snvs_rtc; 18 }; 19 20 backlight: backlight { 21 compatible = "pwm-backlight"; 22 brightness-levels = <0 45 63 88 119 158 203 255>; 23 default-brightness-level = <4>; 24 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 25 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 28 power-supply = <®_3p3v>; 29 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; 31 status = "disabled"; 32 }; 33 34 /* Fixed clock dedicated to SPI CAN controller */ 35 clk20m: oscillator { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <20000000>; 39 }; 40 41 gpio-keys { 42 compatible = "gpio-keys"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_gpio_keys>; 45 46 key-wakeup { 47 debounce-interval = <10>; 48 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 50 label = "Wake-Up"; 51 linux,code = <KEY_WAKEUP>; 52 wakeup-source; 53 }; 54 }; 55 56 panel_lvds: panel-lvds { 57 compatible = "panel-lvds"; 58 backlight = <&backlight>; 59 data-mapping = "vesa-24"; 60 status = "disabled"; 61 }; 62 63 /* Carrier Board Supplies */ 64 reg_1p8v: regulator-1p8v { 65 compatible = "regulator-fixed"; 66 regulator-max-microvolt = <1800000>; 67 regulator-min-microvolt = <1800000>; 68 regulator-name = "+V1.8_SW"; 69 }; 70 71 reg_3p3v: regulator-3p3v { 72 compatible = "regulator-fixed"; 73 regulator-max-microvolt = <3300000>; 74 regulator-min-microvolt = <3300000>; 75 regulator-name = "+V3.3_SW"; 76 }; 77 78 reg_5p0v: regulator-5p0v { 79 compatible = "regulator-fixed"; 80 regulator-max-microvolt = <5000000>; 81 regulator-min-microvolt = <5000000>; 82 regulator-name = "+V5_SW"; 83 }; 84 85 /* Non PMIC On-module Supplies */ 86 reg_ethphy: regulator-ethphy { 87 compatible = "regulator-fixed"; 88 enable-active-high; 89 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 90 off-on-delay = <500000>; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_reg_eth>; 93 regulator-boot-on; 94 regulator-max-microvolt = <3300000>; 95 regulator-min-microvolt = <3300000>; 96 regulator-name = "On-module +V3.3_ETH"; 97 startup-delay-us = <200000>; 98 }; 99 100 reg_usb_otg1_vbus: regulator-usb-otg1 { 101 compatible = "regulator-fixed"; 102 enable-active-high; 103 /* Verdin USB_1_EN (SODIMM 155) */ 104 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_reg_usb1_en>; 107 regulator-max-microvolt = <5000000>; 108 regulator-min-microvolt = <5000000>; 109 regulator-name = "USB_1_EN"; 110 }; 111 112 reg_usb_otg2_vbus: regulator-usb-otg2 { 113 compatible = "regulator-fixed"; 114 enable-active-high; 115 /* Verdin USB_2_EN (SODIMM 185) */ 116 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 117 pinctrl-names = "default"; 118 pinctrl-0 = <&pinctrl_reg_usb2_en>; 119 regulator-max-microvolt = <5000000>; 120 regulator-min-microvolt = <5000000>; 121 regulator-name = "USB_2_EN"; 122 }; 123 124 reg_usdhc2_vmmc: regulator-usdhc2 { 125 compatible = "regulator-fixed"; 126 enable-active-high; 127 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 128 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 129 off-on-delay = <100000>; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 132 regulator-max-microvolt = <3300000>; 133 regulator-min-microvolt = <3300000>; 134 regulator-name = "+V3.3_SD"; 135 startup-delay-us = <2000>; 136 }; 137 138 reserved-memory { 139 #address-cells = <2>; 140 #size-cells = <2>; 141 ranges; 142 143 /* Use the kernel configuration settings instead */ 144 /delete-node/ linux,cma; 145 }; 146}; 147 148&A53_0 { 149 cpu-supply = <®_vdd_arm>; 150}; 151 152&A53_1 { 153 cpu-supply = <®_vdd_arm>; 154}; 155 156&A53_2 { 157 cpu-supply = <®_vdd_arm>; 158}; 159 160&A53_3 { 161 cpu-supply = <®_vdd_arm>; 162}; 163 164&cpu_alert0 { 165 temperature = <95000>; 166}; 167 168&cpu_crit0 { 169 temperature = <105000>; 170}; 171 172&ddrc { 173 operating-points-v2 = <&ddrc_opp_table>; 174 175 ddrc_opp_table: opp-table { 176 compatible = "operating-points-v2"; 177 178 opp-25M { 179 opp-hz = /bits/ 64 <25000000>; 180 }; 181 182 opp-100M { 183 opp-hz = /bits/ 64 <100000000>; 184 }; 185 186 opp-750M { 187 opp-hz = /bits/ 64 <750000000>; 188 }; 189 }; 190}; 191 192/* Verdin SPI_1 */ 193&ecspi2 { 194 #address-cells = <1>; 195 #size-cells = <0>; 196 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_ecspi2>; 199}; 200 201/* Verdin CAN_1 (On-module) */ 202&ecspi3 { 203 #address-cells = <1>; 204 #size-cells = <0>; 205 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_ecspi3>; 208 status = "okay"; 209 210 can1: can@0 { 211 compatible = "microchip,mcp251xfd"; 212 clocks = <&clk20m>; 213 interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_can1_int>; 216 reg = <0>; 217 spi-max-frequency = <8500000>; 218 }; 219}; 220 221/* Verdin ETH_1 (On-module PHY) */ 222&fec1 { 223 fsl,magic-packet; 224 phy-handle = <ðphy0>; 225 phy-mode = "rgmii-id"; 226 phy-supply = <®_ethphy>; 227 pinctrl-names = "default", "sleep"; 228 pinctrl-0 = <&pinctrl_fec1>; 229 pinctrl-1 = <&pinctrl_fec1_sleep>; 230 231 mdio { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 235 ethphy0: ethernet-phy@7 { 236 compatible = "ethernet-phy-ieee802.3-c22"; 237 interrupt-parent = <&gpio1>; 238 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 239 micrel,led-mode = <0>; 240 reg = <7>; 241 }; 242 }; 243}; 244 245/* Verdin QSPI_1 */ 246&flexspi { 247 pinctrl-names = "default"; 248 pinctrl-0 = <&pinctrl_flexspi0>; 249}; 250 251&gpio1 { 252 gpio-line-names = "SODIMM_216", 253 "SODIMM_19", 254 "", 255 "", 256 "", 257 "", 258 "", 259 "", 260 "SODIMM_220", 261 "SODIMM_222", 262 "", 263 "SODIMM_218", 264 "SODIMM_155", 265 "SODIMM_157", 266 "SODIMM_185", 267 "SODIMM_187"; 268}; 269 270&gpio2 { 271 gpio-line-names = "", 272 "", 273 "", 274 "", 275 "", 276 "", 277 "", 278 "", 279 "", 280 "", 281 "", 282 "", 283 "SODIMM_84", 284 "SODIMM_78", 285 "SODIMM_74", 286 "SODIMM_80", 287 "SODIMM_82", 288 "SODIMM_70", 289 "SODIMM_72"; 290}; 291 292&gpio5 { 293 gpio-line-names = "SODIMM_131", 294 "", 295 "SODIMM_91", 296 "SODIMM_16", 297 "SODIMM_15", 298 "SODIMM_208", 299 "SODIMM_137", 300 "SODIMM_139", 301 "SODIMM_141", 302 "SODIMM_143", 303 "SODIMM_196", 304 "SODIMM_200", 305 "SODIMM_198", 306 "SODIMM_202", 307 "", 308 "", 309 "SODIMM_55", 310 "SODIMM_53", 311 "SODIMM_95", 312 "SODIMM_93", 313 "SODIMM_14", 314 "SODIMM_12", 315 "", 316 "", 317 "", 318 "", 319 "SODIMM_210", 320 "SODIMM_212", 321 "SODIMM_151", 322 "SODIMM_153"; 323 324 ctrl-sleep-moci-hog { 325 gpio-hog; 326 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 327 gpios = <1 GPIO_ACTIVE_HIGH>; 328 line-name = "CTRL_SLEEP_MOCI#"; 329 output-high; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 332 }; 333}; 334 335/* On-module I2C */ 336&i2c1 { 337 clock-frequency = <400000>; 338 pinctrl-names = "default", "gpio"; 339 pinctrl-0 = <&pinctrl_i2c1>; 340 pinctrl-1 = <&pinctrl_i2c1_gpio>; 341 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 342 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 343 status = "okay"; 344 345 pca9450: pmic@25 { 346 compatible = "nxp,pca9450a"; 347 interrupt-parent = <&gpio1>; 348 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 349 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&pinctrl_pmic>; 352 reg = <0x25>; 353 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 354 355 /* 356 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC 357 * behind this PMIC. 358 */ 359 360 regulators { 361 reg_vdd_soc: BUCK1 { 362 nxp,dvs-run-voltage = <850000>; 363 nxp,dvs-standby-voltage = <800000>; 364 regulator-always-on; 365 regulator-boot-on; 366 regulator-max-microvolt = <850000>; 367 regulator-min-microvolt = <800000>; 368 regulator-name = "On-module +VDD_SOC (BUCK1)"; 369 regulator-ramp-delay = <3125>; 370 }; 371 372 reg_vdd_arm: BUCK2 { 373 nxp,dvs-run-voltage = <950000>; 374 nxp,dvs-standby-voltage = <850000>; 375 regulator-always-on; 376 regulator-boot-on; 377 regulator-max-microvolt = <950000>; 378 regulator-min-microvolt = <850000>; 379 regulator-name = "On-module +VDD_ARM (BUCK2)"; 380 regulator-ramp-delay = <3125>; 381 }; 382 383 reg_vdd_dram: BUCK3 { 384 regulator-always-on; 385 regulator-boot-on; 386 regulator-max-microvolt = <950000>; 387 regulator-min-microvolt = <850000>; 388 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; 389 }; 390 391 reg_vdd_3v3: BUCK4 { 392 regulator-always-on; 393 regulator-boot-on; 394 regulator-max-microvolt = <3300000>; 395 regulator-min-microvolt = <3300000>; 396 regulator-name = "On-module +V3.3 (BUCK4)"; 397 }; 398 399 reg_vdd_1v8: BUCK5 { 400 regulator-always-on; 401 regulator-boot-on; 402 regulator-max-microvolt = <1800000>; 403 regulator-min-microvolt = <1800000>; 404 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 405 }; 406 407 reg_nvcc_dram: BUCK6 { 408 regulator-always-on; 409 regulator-boot-on; 410 regulator-max-microvolt = <1100000>; 411 regulator-min-microvolt = <1100000>; 412 regulator-name = "On-module +VDD_DDR (BUCK6)"; 413 }; 414 415 reg_nvcc_snvs: LDO1 { 416 regulator-always-on; 417 regulator-boot-on; 418 regulator-max-microvolt = <1800000>; 419 regulator-min-microvolt = <1800000>; 420 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 421 }; 422 423 reg_vdd_snvs: LDO2 { 424 regulator-always-on; 425 regulator-boot-on; 426 regulator-max-microvolt = <900000>; 427 regulator-min-microvolt = <800000>; 428 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 429 }; 430 431 reg_vdda: LDO3 { 432 regulator-always-on; 433 regulator-boot-on; 434 regulator-max-microvolt = <1800000>; 435 regulator-min-microvolt = <1800000>; 436 regulator-name = "On-module +V1.8A (LDO3)"; 437 }; 438 439 reg_vdd_phy: LDO4 { 440 regulator-always-on; 441 regulator-boot-on; 442 regulator-max-microvolt = <900000>; 443 regulator-min-microvolt = <900000>; 444 regulator-name = "On-module +V0.9_MIPI (LDO4)"; 445 }; 446 447 reg_nvcc_sd: LDO5 { 448 regulator-max-microvolt = <3300000>; 449 regulator-min-microvolt = <1800000>; 450 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 451 }; 452 }; 453 }; 454 455 rtc_i2c: rtc@32 { 456 compatible = "epson,rx8130"; 457 reg = <0x32>; 458 }; 459 460 adc@49 { 461 compatible = "ti,ads1015"; 462 reg = <0x49>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 466 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 467 channel@0 { 468 reg = <0>; 469 ti,datarate = <4>; 470 ti,gain = <2>; 471 }; 472 473 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 474 channel@1 { 475 reg = <1>; 476 ti,datarate = <4>; 477 ti,gain = <2>; 478 }; 479 480 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 481 channel@2 { 482 reg = <2>; 483 ti,datarate = <4>; 484 ti,gain = <2>; 485 }; 486 487 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 488 channel@3 { 489 reg = <3>; 490 ti,datarate = <4>; 491 ti,gain = <2>; 492 }; 493 494 /* Verdin I2C_1 ADC_4 */ 495 channel@4 { 496 reg = <4>; 497 ti,datarate = <4>; 498 ti,gain = <2>; 499 }; 500 501 /* Verdin I2C_1 ADC_3 */ 502 channel@5 { 503 reg = <5>; 504 ti,datarate = <4>; 505 ti,gain = <2>; 506 }; 507 508 /* Verdin I2C_1 ADC_2 */ 509 channel@6 { 510 reg = <6>; 511 ti,datarate = <4>; 512 ti,gain = <2>; 513 }; 514 515 /* Verdin I2C_1 ADC_1 */ 516 channel@7 { 517 reg = <7>; 518 ti,datarate = <4>; 519 ti,gain = <2>; 520 }; 521 }; 522 523 eeprom@50 { 524 compatible = "st,24c02"; 525 pagesize = <16>; 526 reg = <0x50>; 527 }; 528}; 529 530/* Verdin I2C_2_DSI */ 531&i2c2 { 532 clock-frequency = <10000>; 533 pinctrl-names = "default", "gpio"; 534 pinctrl-0 = <&pinctrl_i2c2>; 535 pinctrl-1 = <&pinctrl_i2c2_gpio>; 536 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 537 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 538 status = "disabled"; 539}; 540 541/* Verdin I2C_3_HDMI N/A */ 542 543/* Verdin I2C_4_CSI */ 544&i2c3 { 545 clock-frequency = <400000>; 546 pinctrl-names = "default", "gpio"; 547 pinctrl-0 = <&pinctrl_i2c3>; 548 pinctrl-1 = <&pinctrl_i2c3_gpio>; 549 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 550 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 551}; 552 553/* Verdin I2C_1 */ 554&i2c4 { 555 clock-frequency = <400000>; 556 pinctrl-names = "default", "gpio"; 557 pinctrl-0 = <&pinctrl_i2c4>; 558 pinctrl-1 = <&pinctrl_i2c4_gpio>; 559 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 560 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 561 562 gpio_expander_21: gpio-expander@21 { 563 compatible = "nxp,pcal6416"; 564 #gpio-cells = <2>; 565 gpio-controller; 566 reg = <0x21>; 567 vcc-supply = <®_3p3v>; 568 status = "disabled"; 569 }; 570 571 lvds_ti_sn65dsi84: bridge@2c { 572 compatible = "ti,sn65dsi84"; 573 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 574 /* Verdin GPIO_10_DSI (SODIMM 21) */ 575 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 576 pinctrl-names = "default"; 577 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 578 reg = <0x2c>; 579 status = "disabled"; 580 }; 581 582 /* Current measurement into module VCC */ 583 hwmon: hwmon@40 { 584 compatible = "ti,ina219"; 585 reg = <0x40>; 586 shunt-resistor = <10000>; 587 status = "disabled"; 588 }; 589 590 hdmi_lontium_lt8912: hdmi@48 { 591 compatible = "lontium,lt8912b"; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; 594 reg = <0x48>; 595 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 596 /* Verdin GPIO_10_DSI (SODIMM 21) */ 597 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; 598 status = "disabled"; 599 }; 600 601 atmel_mxt_ts: touch@4a { 602 compatible = "atmel,maxtouch"; 603 /* 604 * Verdin GPIO_9_DSI 605 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) 606 */ 607 interrupt-parent = <&gpio3>; 608 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 609 pinctrl-names = "default"; 610 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 611 reg = <0x4a>; 612 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 613 reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; 614 status = "disabled"; 615 }; 616 617 /* Temperature sensor on carrier board */ 618 hwmon_temp: sensor@4f { 619 compatible = "ti,tmp75c"; 620 reg = <0x4f>; 621 status = "disabled"; 622 }; 623 624 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 625 eeprom_display_adapter: eeprom@50 { 626 compatible = "st,24c02"; 627 pagesize = <16>; 628 reg = <0x50>; 629 status = "disabled"; 630 }; 631 632 /* EEPROM on carrier board */ 633 eeprom_carrier_board: eeprom@57 { 634 compatible = "st,24c02"; 635 pagesize = <16>; 636 reg = <0x57>; 637 status = "disabled"; 638 }; 639}; 640 641/* Verdin PCIE_1 */ 642&pcie0 { 643 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 644 <&clk IMX8MM_CLK_PCIE1_CTRL>; 645 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 646 <&clk IMX8MM_SYS_PLL2_250M>; 647 assigned-clock-rates = <10000000>, <250000000>; 648 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, 649 <&clk IMX8MM_CLK_PCIE1_PHY>; 650 clock-names = "pcie", "pcie_aux", "pcie_bus"; 651 pinctrl-names = "default"; 652 pinctrl-0 = <&pinctrl_pcie0>; 653 /* PCIE_1_RESET# (SODIMM 244) */ 654 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 655}; 656 657&pcie_phy { 658 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 659 fsl,clkreq-unsupported; 660 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 661 fsl,tx-deemph-gen1 = <0x2d>; 662 fsl,tx-deemph-gen2 = <0xf>; 663}; 664 665/* Verdin PWM_3_DSI */ 666&pwm1 { 667 pinctrl-names = "default"; 668 pinctrl-0 = <&pinctrl_pwm_1>; 669 #pwm-cells = <3>; 670}; 671 672/* Verdin PWM_1 */ 673&pwm2 { 674 pinctrl-names = "default"; 675 pinctrl-0 = <&pinctrl_pwm_2>; 676 #pwm-cells = <3>; 677}; 678 679/* Verdin PWM_2 */ 680&pwm3 { 681 pinctrl-names = "default"; 682 pinctrl-0 = <&pinctrl_pwm_3>; 683 #pwm-cells = <3>; 684}; 685 686/* Verdin I2S_1 */ 687&sai2 { 688 #sound-dai-cells = <0>; 689 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 690 assigned-clock-rates = <24576000>; 691 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&pinctrl_sai2>; 694}; 695 696&snvs_pwrkey { 697 status = "okay"; 698}; 699 700/* Verdin UART_3, used as the Linux console */ 701&uart1 { 702 pinctrl-names = "default"; 703 pinctrl-0 = <&pinctrl_uart1>; 704}; 705 706/* Verdin UART_1 */ 707&uart2 { 708 pinctrl-names = "default"; 709 pinctrl-0 = <&pinctrl_uart2>; 710 uart-has-rtscts; 711}; 712 713/* Verdin UART_2 */ 714&uart3 { 715 pinctrl-names = "default"; 716 pinctrl-0 = <&pinctrl_uart3>; 717 uart-has-rtscts; 718}; 719 720/* 721 * Verdin UART_4 722 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS 723 */ 724&uart4 { 725 pinctrl-names = "default"; 726 pinctrl-0 = <&pinctrl_uart4>; 727}; 728 729/* Verdin USB_1 */ 730&usbotg1 { 731 adp-disable; 732 dr_mode = "otg"; 733 hnp-disable; 734 over-current-active-low; 735 samsung,picophy-dc-vol-level-adjust = <7>; 736 samsung,picophy-pre-emp-curr-control = <3>; 737 srp-disable; 738 vbus-supply = <®_usb_otg1_vbus>; 739}; 740 741/* Verdin USB_2 */ 742&usbotg2 { 743 dr_mode = "host"; 744 over-current-active-low; 745 samsung,picophy-dc-vol-level-adjust = <7>; 746 samsung,picophy-pre-emp-curr-control = <3>; 747 vbus-supply = <®_usb_otg2_vbus>; 748}; 749 750&usbphynop1 { 751 vcc-supply = <®_vdd_3v3>; 752}; 753 754&usbphynop2 { 755 vcc-supply = <®_vdd_3v3>; 756}; 757 758/* On-module eMMC */ 759&usdhc1 { 760 bus-width = <8>; 761 keep-power-in-suspend; 762 non-removable; 763 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 764 pinctrl-0 = <&pinctrl_usdhc1>; 765 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 766 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 767 status = "okay"; 768}; 769 770/* Verdin SD_1 */ 771&usdhc2 { 772 bus-width = <4>; 773 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 774 disable-wp; 775 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 776 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 777 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 778 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 779 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 780 vmmc-supply = <®_usdhc2_vmmc>; 781}; 782 783&wdog1 { 784 fsl,ext-reset-output; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&pinctrl_wdog>; 787 status = "okay"; 788}; 789 790&iomuxc { 791 pinctrl-names = "default"; 792 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 793 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 794 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 795 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, 796 <&pinctrl_pmic_tpm_ena>; 797 798 pinctrl_can1_int: can1intgrp { 799 fsl,pins = 800 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */ 801 }; 802 803 pinctrl_can2_int: can2intgrp { 804 fsl,pins = 805 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */ 806 }; 807 808 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 809 fsl,pins = 810 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */ 811 }; 812 813 pinctrl_ecspi2: ecspi2grp { 814 fsl,pins = 815 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ 816 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */ 817 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */ 818 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ 819 }; 820 821 pinctrl_ecspi3: ecspi3grp { 822 fsl,pins = 823 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */ 824 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ 825 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ 826 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ 827 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */ 828 }; 829 830 pinctrl_fec1: fec1grp { 831 fsl,pins = 832 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 833 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 834 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 835 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 836 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 837 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 838 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 839 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 840 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, 841 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, 842 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, 843 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, 844 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, 845 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, 846 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; 847 }; 848 849 pinctrl_fec1_sleep: fec1-sleepgrp { 850 fsl,pins = 851 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 852 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 853 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 854 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 855 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 856 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 857 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 858 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 859 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, 860 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, 861 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, 862 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, 863 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, 864 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, 865 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; 866 }; 867 868 pinctrl_flexspi0: flexspi0grp { 869 fsl,pins = 870 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ 871 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ 872 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ 873 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ 874 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ 875 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ 876 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */ 877 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */ 878 }; 879 880 pinctrl_gpio1: gpio1grp { 881 fsl,pins = 882 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */ 883 }; 884 885 pinctrl_gpio2: gpio2grp { 886 fsl,pins = 887 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */ 888 }; 889 890 pinctrl_gpio3: gpio3grp { 891 fsl,pins = 892 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */ 893 }; 894 895 pinctrl_gpio4: gpio4grp { 896 fsl,pins = 897 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */ 898 }; 899 900 pinctrl_gpio5: gpio5grp { 901 fsl,pins = 902 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */ 903 }; 904 905 pinctrl_gpio6: gpio6grp { 906 fsl,pins = 907 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */ 908 }; 909 910 pinctrl_gpio7: gpio7grp { 911 fsl,pins = 912 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */ 913 }; 914 915 pinctrl_gpio8: gpio8grp { 916 fsl,pins = 917 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */ 918 }; 919 920 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 921 pinctrl_gpio_9_dsi: gpio9dsigrp { 922 fsl,pins = 923 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */ 924 }; 925 926 /* Verdin GPIO_10_DSI (pulled-up as active-low) */ 927 pinctrl_gpio_10_dsi: gpio10dsigrp { 928 fsl,pins = 929 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */ 930 }; 931 932 pinctrl_gpio_hog1: gpiohog1grp { 933 fsl,pins = 934 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */ 935 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */ 936 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */ 937 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */ 938 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */ 939 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */ 940 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */ 941 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */ 942 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */ 943 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */ 944 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */ 945 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */ 946 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */ 947 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */ 948 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */ 949 }; 950 951 pinctrl_gpio_hog2: gpiohog2grp { 952 fsl,pins = 953 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */ 954 }; 955 956 pinctrl_gpio_hog3: gpiohog3grp { 957 fsl,pins = 958 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */ 959 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */ 960 }; 961 962 pinctrl_gpio_keys: gpiokeysgrp { 963 fsl,pins = 964 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */ 965 }; 966 967 /* On-module I2C */ 968 pinctrl_i2c1: i2c1grp { 969 fsl,pins = 970 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */ 971 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */ 972 }; 973 974 pinctrl_i2c1_gpio: i2c1gpiogrp { 975 fsl,pins = 976 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */ 977 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */ 978 }; 979 980 /* Verdin I2C_4_CSI */ 981 pinctrl_i2c2: i2c2grp { 982 fsl,pins = 983 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */ 984 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */ 985 }; 986 987 pinctrl_i2c2_gpio: i2c2gpiogrp { 988 fsl,pins = 989 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */ 990 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */ 991 }; 992 993 /* Verdin I2C_2_DSI */ 994 pinctrl_i2c3: i2c3grp { 995 fsl,pins = 996 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */ 997 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */ 998 }; 999 1000 pinctrl_i2c3_gpio: i2c3gpiogrp { 1001 fsl,pins = 1002 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */ 1003 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */ 1004 }; 1005 1006 /* Verdin I2C_1 */ 1007 pinctrl_i2c4: i2c4grp { 1008 fsl,pins = 1009 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */ 1010 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */ 1011 }; 1012 1013 pinctrl_i2c4_gpio: i2c4gpiogrp { 1014 fsl,pins = 1015 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */ 1016 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */ 1017 }; 1018 1019 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1020 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1021 fsl,pins = 1022 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */ 1023 }; 1024 1025 /* Verdin I2S_2_D_OUT shared with SAI5 */ 1026 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1027 fsl,pins = 1028 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */ 1029 }; 1030 1031 pinctrl_pcie0: pcie0grp { 1032 fsl,pins = 1033 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ 1034 /* PMIC_EN_PCIe_CLK, unused */ 1035 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; 1036 }; 1037 1038 pinctrl_pmic: pmicirqgrp { 1039 fsl,pins = 1040 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */ 1041 }; 1042 1043 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ 1044 pinctrl_pwm_1: pwm1grp { 1045 fsl,pins = 1046 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ 1047 }; 1048 1049 pinctrl_pwm_2: pwm2grp { 1050 fsl,pins = 1051 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ 1052 }; 1053 1054 pinctrl_pwm_3: pwm3grp { 1055 fsl,pins = 1056 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ 1057 }; 1058 1059 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ 1060 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { 1061 fsl,pins = 1062 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */ 1063 }; 1064 1065 pinctrl_reg_eth: regethgrp { 1066 fsl,pins = 1067 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */ 1068 }; 1069 1070 pinctrl_reg_usb1_en: regusb1engrp { 1071 fsl,pins = 1072 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */ 1073 }; 1074 1075 pinctrl_reg_usb2_en: regusb2engrp { 1076 fsl,pins = 1077 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */ 1078 }; 1079 1080 pinctrl_sai2: sai2grp { 1081 fsl,pins = 1082 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ 1083 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */ 1084 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */ 1085 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ 1086 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ 1087 }; 1088 1089 pinctrl_sai5: sai5grp { 1090 fsl,pins = 1091 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */ 1092 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */ 1093 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */ 1094 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */ 1095 }; 1096 1097 /* control signal for optional ATTPM20P or SE050 */ 1098 pinctrl_pmic_tpm_ena: pmictpmenagrp { 1099 fsl,pins = 1100 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ 1101 }; 1102 1103 pinctrl_tsp: tspgrp { 1104 fsl,pins = 1105 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */ 1106 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */ 1107 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */ 1108 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */ 1109 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */ 1110 }; 1111 1112 pinctrl_uart1: uart1grp { 1113 fsl,pins = 1114 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */ 1115 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */ 1116 }; 1117 1118 pinctrl_uart2: uart2grp { 1119 fsl,pins = 1120 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ 1121 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */ 1122 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */ 1123 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */ 1124 }; 1125 1126 pinctrl_uart3: uart3grp { 1127 fsl,pins = 1128 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ 1129 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */ 1130 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */ 1131 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ 1132 }; 1133 1134 pinctrl_uart4: uart4grp { 1135 fsl,pins = 1136 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */ 1137 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */ 1138 }; 1139 1140 pinctrl_usdhc1: usdhc1grp { 1141 fsl,pins = 1142 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, 1143 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, 1144 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, 1145 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, 1146 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, 1147 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, 1148 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, 1149 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, 1150 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, 1151 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, 1152 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1153 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; 1154 }; 1155 1156 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1157 fsl,pins = 1158 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, 1159 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, 1160 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, 1161 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, 1162 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, 1163 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, 1164 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, 1165 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, 1166 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, 1167 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, 1168 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1169 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; 1170 }; 1171 1172 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1173 fsl,pins = 1174 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, 1175 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, 1176 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, 1177 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, 1178 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, 1179 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, 1180 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, 1181 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, 1182 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, 1183 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, 1184 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1185 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; 1186 }; 1187 1188 pinctrl_usdhc2_cd: usdhc2cdgrp { 1189 fsl,pins = 1190 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */ 1191 }; 1192 1193 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1194 fsl,pins = 1195 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */ 1196 }; 1197 1198 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1199 fsl,pins = 1200 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ 1201 }; 1202 1203 /* 1204 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the 1205 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. 1206 */ 1207 pinctrl_usdhc2: usdhc2grp { 1208 fsl,pins = 1209 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1210 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ 1211 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ 1212 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ 1213 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ 1214 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ 1215 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */ 1216 }; 1217 1218 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1219 fsl,pins = 1220 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1221 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, 1222 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, 1223 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, 1224 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, 1225 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, 1226 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>; 1227 }; 1228 1229 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1230 fsl,pins = 1231 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1232 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, 1233 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, 1234 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, 1235 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, 1236 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, 1237 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>; 1238 }; 1239 1240 /* Avoid backfeeding with removed card power */ 1241 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1242 fsl,pins = 1243 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>, 1244 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, 1245 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, 1246 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>, 1247 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>, 1248 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>, 1249 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>; 1250 }; 1251 1252 /* 1253 * On-module Wi-Fi/BT or type specific SDHC interface 1254 * (e.g. on X52 extension slot of Verdin Development Board) 1255 */ 1256 pinctrl_usdhc3: usdhc3grp { 1257 fsl,pins = 1258 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, 1259 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, 1260 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, 1261 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>, 1262 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>, 1263 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>; 1264 }; 1265 1266 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1267 fsl,pins = 1268 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, 1269 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, 1270 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, 1271 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>, 1272 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>, 1273 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>; 1274 }; 1275 1276 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1277 fsl,pins = 1278 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, 1279 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, 1280 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, 1281 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>, 1282 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>, 1283 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>; 1284 }; 1285 1286 pinctrl_wdog: wdoggrp { 1287 fsl,pins = 1288 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */ 1289 }; 1290 1291 pinctrl_wifi_ctrl: wifictrlgrp { 1292 fsl,pins = 1293 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */ 1294 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */ 1295 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */ 1296 }; 1297 1298 pinctrl_wifi_i2s: bti2sgrp { 1299 fsl,pins = 1300 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */ 1301 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */ 1302 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */ 1303 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */ 1304 }; 1305 1306 pinctrl_wifi_pwr_en: wifipwrengrp { 1307 fsl,pins = 1308 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */ 1309 }; 1310}; 1311