1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include "dt-bindings/phy/phy-imx8-pcie.h"
7#include "dt-bindings/pwm/pwm.h"
8#include "imx8mm.dtsi"
9
10/ {
11	chosen {
12		stdout-path = &uart1;
13	};
14
15	aliases {
16		rtc0 = &rtc_i2c;
17		rtc1 = &snvs_rtc;
18	};
19
20	backlight: backlight {
21		compatible = "pwm-backlight";
22		brightness-levels = <0 45 63 88 119 158 203 255>;
23		default-brightness-level = <4>;
24		/* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
25		enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
26		pinctrl-names = "default";
27		pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
28		power-supply = <&reg_3p3v>;
29		/* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
30		pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
31		status = "disabled";
32	};
33
34	/* Fixed clock dedicated to SPI CAN controller */
35	clk20m: oscillator {
36		compatible = "fixed-clock";
37		#clock-cells = <0>;
38		clock-frequency = <20000000>;
39	};
40
41	gpio-keys {
42		compatible = "gpio-keys";
43		pinctrl-names = "default";
44		pinctrl-0 = <&pinctrl_gpio_keys>;
45
46		key-wakeup {
47			debounce-interval = <10>;
48			/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
49			gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
50			label = "Wake-Up";
51			linux,code = <KEY_WAKEUP>;
52			wakeup-source;
53		};
54	};
55
56	/* Carrier Board Supplies */
57	reg_1p8v: regulator-1p8v {
58		compatible = "regulator-fixed";
59		regulator-max-microvolt = <1800000>;
60		regulator-min-microvolt = <1800000>;
61		regulator-name = "+V1.8_SW";
62	};
63
64	reg_3p3v: regulator-3p3v {
65		compatible = "regulator-fixed";
66		regulator-max-microvolt = <3300000>;
67		regulator-min-microvolt = <3300000>;
68		regulator-name = "+V3.3_SW";
69	};
70
71	reg_5p0v: regulator-5p0v {
72		compatible = "regulator-fixed";
73		regulator-max-microvolt = <5000000>;
74		regulator-min-microvolt = <5000000>;
75		regulator-name = "+V5_SW";
76	};
77
78	/* Non PMIC On-module Supplies */
79	reg_ethphy: regulator-ethphy {
80		compatible = "regulator-fixed";
81		enable-active-high;
82		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
83		off-on-delay = <500000>;
84		pinctrl-names = "default";
85		pinctrl-0 = <&pinctrl_reg_eth>;
86		regulator-boot-on;
87		regulator-max-microvolt = <3300000>;
88		regulator-min-microvolt = <3300000>;
89		regulator-name = "On-module +V3.3_ETH";
90		startup-delay-us = <200000>;
91	};
92
93	reg_usb_otg1_vbus: regulator-usb-otg1 {
94		compatible = "regulator-fixed";
95		enable-active-high;
96		/* Verdin USB_1_EN (SODIMM 155) */
97		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
98		pinctrl-names = "default";
99		pinctrl-0 = <&pinctrl_reg_usb1_en>;
100		regulator-max-microvolt = <5000000>;
101		regulator-min-microvolt = <5000000>;
102		regulator-name = "USB_1_EN";
103	};
104
105	reg_usb_otg2_vbus: regulator-usb-otg2 {
106		compatible = "regulator-fixed";
107		enable-active-high;
108		/* Verdin USB_2_EN (SODIMM 185) */
109		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
110		pinctrl-names = "default";
111		pinctrl-0 = <&pinctrl_reg_usb2_en>;
112		regulator-max-microvolt = <5000000>;
113		regulator-min-microvolt = <5000000>;
114		regulator-name = "USB_2_EN";
115	};
116
117	reg_usdhc2_vmmc: regulator-usdhc2 {
118		compatible = "regulator-fixed";
119		enable-active-high;
120		/* Verdin SD_1_PWR_EN (SODIMM 76) */
121		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
122		off-on-delay = <100000>;
123		pinctrl-names = "default";
124		pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
125		regulator-max-microvolt = <3300000>;
126		regulator-min-microvolt = <3300000>;
127		regulator-name = "+V3.3_SD";
128		startup-delay-us = <2000>;
129	};
130
131	reserved-memory {
132		#address-cells = <2>;
133		#size-cells = <2>;
134		ranges;
135
136		/* Use the kernel configuration settings instead */
137		/delete-node/ linux,cma;
138	};
139};
140
141&A53_0 {
142	cpu-supply = <&reg_vdd_arm>;
143};
144
145&A53_1 {
146	cpu-supply = <&reg_vdd_arm>;
147};
148
149&A53_2 {
150	cpu-supply = <&reg_vdd_arm>;
151};
152
153&A53_3 {
154	cpu-supply = <&reg_vdd_arm>;
155};
156
157&cpu_alert0 {
158	temperature = <95000>;
159};
160
161&cpu_crit0 {
162	temperature = <105000>;
163};
164
165&ddrc {
166	operating-points-v2 = <&ddrc_opp_table>;
167
168	ddrc_opp_table: opp-table {
169		compatible = "operating-points-v2";
170
171		opp-25M {
172			opp-hz = /bits/ 64 <25000000>;
173		};
174
175		opp-100M {
176			opp-hz = /bits/ 64 <100000000>;
177		};
178
179		opp-750M {
180			opp-hz = /bits/ 64 <750000000>;
181		};
182	};
183};
184
185/* Verdin SPI_1 */
186&ecspi2 {
187	#address-cells = <1>;
188	#size-cells = <0>;
189	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
190	pinctrl-names = "default";
191	pinctrl-0 = <&pinctrl_ecspi2>;
192};
193
194/* Verdin CAN_1 (On-module) */
195&ecspi3 {
196	#address-cells = <1>;
197	#size-cells = <0>;
198	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
199	pinctrl-names = "default";
200	pinctrl-0 = <&pinctrl_ecspi3>;
201	status = "okay";
202
203	can1: can@0 {
204		compatible = "microchip,mcp251xfd";
205		clocks = <&clk20m>;
206		interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>;
207		pinctrl-names = "default";
208		pinctrl-0 = <&pinctrl_can1_int>;
209		reg = <0>;
210		spi-max-frequency = <8500000>;
211	};
212};
213
214/* Verdin ETH_1 (On-module PHY) */
215&fec1 {
216	fsl,magic-packet;
217	phy-handle = <&ethphy0>;
218	phy-mode = "rgmii-id";
219	phy-supply = <&reg_ethphy>;
220	pinctrl-names = "default", "sleep";
221	pinctrl-0 = <&pinctrl_fec1>;
222	pinctrl-1 = <&pinctrl_fec1_sleep>;
223
224	mdio {
225		#address-cells = <1>;
226		#size-cells = <0>;
227
228		ethphy0: ethernet-phy@7 {
229			compatible = "ethernet-phy-ieee802.3-c22";
230			interrupt-parent = <&gpio1>;
231			interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
232			micrel,led-mode = <0>;
233			reg = <7>;
234		};
235	};
236};
237
238/* Verdin QSPI_1 */
239&flexspi {
240	pinctrl-names = "default";
241	pinctrl-0 = <&pinctrl_flexspi0>;
242};
243
244&gpio1 {
245	gpio-line-names = "SODIMM_216",
246			  "SODIMM_19",
247			  "",
248			  "",
249			  "",
250			  "",
251			  "",
252			  "",
253			  "SODIMM_220",
254			  "SODIMM_222",
255			  "",
256			  "SODIMM_218",
257			  "SODIMM_155",
258			  "SODIMM_157",
259			  "SODIMM_185",
260			  "SODIMM_187";
261};
262
263&gpio2 {
264	gpio-line-names = "",
265			  "",
266			  "",
267			  "",
268			  "",
269			  "",
270			  "",
271			  "",
272			  "",
273			  "",
274			  "",
275			  "",
276			  "SODIMM_84",
277			  "SODIMM_78",
278			  "SODIMM_74",
279			  "SODIMM_80",
280			  "SODIMM_82",
281			  "SODIMM_70",
282			  "SODIMM_72";
283};
284
285&gpio5 {
286	gpio-line-names = "SODIMM_131",
287			  "",
288			  "SODIMM_91",
289			  "SODIMM_16",
290			  "SODIMM_15",
291			  "SODIMM_208",
292			  "SODIMM_137",
293			  "SODIMM_139",
294			  "SODIMM_141",
295			  "SODIMM_143",
296			  "SODIMM_196",
297			  "SODIMM_200",
298			  "SODIMM_198",
299			  "SODIMM_202",
300			  "",
301			  "",
302			  "SODIMM_55",
303			  "SODIMM_53",
304			  "SODIMM_95",
305			  "SODIMM_93",
306			  "SODIMM_14",
307			  "SODIMM_12",
308			  "",
309			  "",
310			  "",
311			  "",
312			  "SODIMM_210",
313			  "SODIMM_212",
314			  "SODIMM_151",
315			  "SODIMM_153";
316
317	ctrl-sleep-moci-hog {
318		gpio-hog;
319		/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
320		gpios = <1 GPIO_ACTIVE_HIGH>;
321		line-name = "CTRL_SLEEP_MOCI#";
322		output-high;
323		pinctrl-names = "default";
324		pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
325	};
326};
327
328/* On-module I2C */
329&i2c1 {
330	clock-frequency = <400000>;
331	pinctrl-names = "default", "gpio";
332	pinctrl-0 = <&pinctrl_i2c1>;
333	pinctrl-1 = <&pinctrl_i2c1_gpio>;
334	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
335	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
336	status = "okay";
337
338	pca9450: pmic@25 {
339		compatible = "nxp,pca9450a";
340		interrupt-parent = <&gpio1>;
341		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
342		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
343		pinctrl-names = "default";
344		pinctrl-0 = <&pinctrl_pmic>;
345		reg = <0x25>;
346		sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
347
348		/*
349		 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
350		 * behind this PMIC.
351		 */
352
353		regulators {
354			reg_vdd_soc: BUCK1 {
355				nxp,dvs-run-voltage = <850000>;
356				nxp,dvs-standby-voltage = <800000>;
357				regulator-always-on;
358				regulator-boot-on;
359				regulator-max-microvolt = <850000>;
360				regulator-min-microvolt = <800000>;
361				regulator-name = "On-module +VDD_SOC (BUCK1)";
362				regulator-ramp-delay = <3125>;
363			};
364
365			reg_vdd_arm: BUCK2 {
366				nxp,dvs-run-voltage = <950000>;
367				nxp,dvs-standby-voltage = <850000>;
368				regulator-always-on;
369				regulator-boot-on;
370				regulator-max-microvolt = <950000>;
371				regulator-min-microvolt = <850000>;
372				regulator-name = "On-module +VDD_ARM (BUCK2)";
373				regulator-ramp-delay = <3125>;
374			};
375
376			reg_vdd_dram: BUCK3 {
377				regulator-always-on;
378				regulator-boot-on;
379				regulator-max-microvolt = <950000>;
380				regulator-min-microvolt = <850000>;
381				regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
382			};
383
384			reg_vdd_3v3: BUCK4 {
385				regulator-always-on;
386				regulator-boot-on;
387				regulator-max-microvolt = <3300000>;
388				regulator-min-microvolt = <3300000>;
389				regulator-name = "On-module +V3.3 (BUCK4)";
390			};
391
392			reg_vdd_1v8: BUCK5 {
393				regulator-always-on;
394				regulator-boot-on;
395				regulator-max-microvolt = <1800000>;
396				regulator-min-microvolt = <1800000>;
397				regulator-name = "PWR_1V8_MOCI (BUCK5)";
398			};
399
400			reg_nvcc_dram: BUCK6 {
401				regulator-always-on;
402				regulator-boot-on;
403				regulator-max-microvolt = <1100000>;
404				regulator-min-microvolt = <1100000>;
405				regulator-name = "On-module +VDD_DDR (BUCK6)";
406			};
407
408			reg_nvcc_snvs: LDO1 {
409				regulator-always-on;
410				regulator-boot-on;
411				regulator-max-microvolt = <1800000>;
412				regulator-min-microvolt = <1800000>;
413				regulator-name = "On-module +V1.8_SNVS (LDO1)";
414			};
415
416			reg_vdd_snvs: LDO2 {
417				regulator-always-on;
418				regulator-boot-on;
419				regulator-max-microvolt = <900000>;
420				regulator-min-microvolt = <800000>;
421				regulator-name = "On-module +V0.8_SNVS (LDO2)";
422			};
423
424			reg_vdda: LDO3 {
425				regulator-always-on;
426				regulator-boot-on;
427				regulator-max-microvolt = <1800000>;
428				regulator-min-microvolt = <1800000>;
429				regulator-name = "On-module +V1.8A (LDO3)";
430			};
431
432			reg_vdd_phy: LDO4 {
433				regulator-always-on;
434				regulator-boot-on;
435				regulator-max-microvolt = <900000>;
436				regulator-min-microvolt = <900000>;
437				regulator-name = "On-module +V0.9_MIPI (LDO4)";
438			};
439
440			reg_nvcc_sd: LDO5 {
441				regulator-max-microvolt = <3300000>;
442				regulator-min-microvolt = <1800000>;
443				regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
444			};
445		};
446	};
447
448	rtc_i2c: rtc@32 {
449		compatible = "epson,rx8130";
450		reg = <0x32>;
451	};
452
453	adc@49 {
454		compatible = "ti,ads1015";
455		reg = <0x49>;
456		#address-cells = <1>;
457		#size-cells = <0>;
458
459		/* Verdin I2C_1 (ADC_4 - ADC_3) */
460		channel@0 {
461			reg = <0>;
462			ti,datarate = <4>;
463			ti,gain = <2>;
464		};
465
466		/* Verdin I2C_1 (ADC_4 - ADC_1) */
467		channel@1 {
468			reg = <1>;
469			ti,datarate = <4>;
470			ti,gain = <2>;
471		};
472
473		/* Verdin I2C_1 (ADC_3 - ADC_1) */
474		channel@2 {
475			reg = <2>;
476			ti,datarate = <4>;
477			ti,gain = <2>;
478		};
479
480		/* Verdin I2C_1 (ADC_2 - ADC_1) */
481		channel@3 {
482			reg = <3>;
483			ti,datarate = <4>;
484			ti,gain = <2>;
485		};
486
487		/* Verdin I2C_1 ADC_4 */
488		channel@4 {
489			reg = <4>;
490			ti,datarate = <4>;
491			ti,gain = <2>;
492		};
493
494		/* Verdin I2C_1 ADC_3 */
495		channel@5 {
496			reg = <5>;
497			ti,datarate = <4>;
498			ti,gain = <2>;
499		};
500
501		/* Verdin I2C_1 ADC_2 */
502		channel@6 {
503			reg = <6>;
504			ti,datarate = <4>;
505			ti,gain = <2>;
506		};
507
508		/* Verdin I2C_1 ADC_1 */
509		channel@7 {
510			reg = <7>;
511			ti,datarate = <4>;
512			ti,gain = <2>;
513		};
514	};
515
516	eeprom@50 {
517		compatible = "st,24c02";
518		pagesize = <16>;
519		reg = <0x50>;
520	};
521};
522
523/* Verdin I2C_2_DSI */
524&i2c2 {
525	clock-frequency = <10000>;
526	pinctrl-names = "default", "gpio";
527	pinctrl-0 = <&pinctrl_i2c2>;
528	pinctrl-1 = <&pinctrl_i2c2_gpio>;
529	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
530	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
531	status = "disabled";
532};
533
534/* Verdin I2C_3_HDMI N/A */
535
536/* Verdin I2C_4_CSI */
537&i2c3 {
538	clock-frequency = <400000>;
539	pinctrl-names = "default", "gpio";
540	pinctrl-0 = <&pinctrl_i2c3>;
541	pinctrl-1 = <&pinctrl_i2c3_gpio>;
542	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
543	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
544};
545
546/* Verdin I2C_1 */
547&i2c4 {
548	clock-frequency = <400000>;
549	pinctrl-names = "default", "gpio";
550	pinctrl-0 = <&pinctrl_i2c4>;
551	pinctrl-1 = <&pinctrl_i2c4_gpio>;
552	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
553	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
554
555	gpio_expander_21: gpio-expander@21 {
556		compatible = "nxp,pcal6416";
557		#gpio-cells = <2>;
558		gpio-controller;
559		reg = <0x21>;
560		vcc-supply = <&reg_3p3v>;
561		status = "disabled";
562	};
563
564	lvds_ti_sn65dsi83: bridge@2c {
565		compatible = "ti,sn65dsi83";
566		/* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
567		/* Verdin GPIO_10_DSI (SODIMM 21) */
568		enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
569		pinctrl-names = "default";
570		pinctrl-0 = <&pinctrl_gpio_10_dsi>;
571		reg = <0x2c>;
572		status = "disabled";
573	};
574
575	/* Current measurement into module VCC */
576	hwmon: hwmon@40 {
577		compatible = "ti,ina219";
578		reg = <0x40>;
579		shunt-resistor = <10000>;
580		status = "disabled";
581	};
582
583	hdmi_lontium_lt8912: hdmi@48 {
584		compatible = "lontium,lt8912b";
585		pinctrl-names = "default";
586		pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
587		reg = <0x48>;
588		/* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
589		/* Verdin GPIO_10_DSI (SODIMM 21) */
590		reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
591		status = "disabled";
592	};
593
594	atmel_mxt_ts: touch@4a {
595		compatible = "atmel,maxtouch";
596		/*
597		 * Verdin GPIO_9_DSI
598		 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
599		 */
600		interrupt-parent = <&gpio3>;
601		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
602		pinctrl-names = "default";
603		pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
604		reg = <0x4a>;
605		/* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
606		reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
607		status = "disabled";
608	};
609
610	/* Temperature sensor on carrier board */
611	hwmon_temp: sensor@4f {
612		compatible = "ti,tmp75c";
613		reg = <0x4f>;
614		status = "disabled";
615	};
616
617	/* EEPROM on display adapter (MIPI DSI Display Adapter) */
618	eeprom_display_adapter: eeprom@50 {
619		compatible = "st,24c02";
620		pagesize = <16>;
621		reg = <0x50>;
622		status = "disabled";
623	};
624
625	/* EEPROM on carrier board */
626	eeprom_carrier_board: eeprom@57 {
627		compatible = "st,24c02";
628		pagesize = <16>;
629		reg = <0x57>;
630		status = "disabled";
631	};
632};
633
634/* Verdin PCIE_1 */
635&pcie0 {
636	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
637			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
638	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
639				 <&clk IMX8MM_SYS_PLL2_250M>;
640	assigned-clock-rates = <10000000>, <250000000>;
641	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
642		 <&clk IMX8MM_CLK_PCIE1_PHY>;
643	clock-names = "pcie", "pcie_aux", "pcie_bus";
644	pinctrl-names = "default";
645	pinctrl-0 = <&pinctrl_pcie0>;
646	/* PCIE_1_RESET# (SODIMM 244) */
647	reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
648};
649
650&pcie_phy {
651	clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
652	fsl,clkreq-unsupported;
653	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
654	fsl,tx-deemph-gen1 = <0x2d>;
655	fsl,tx-deemph-gen2 = <0xf>;
656};
657
658/* Verdin PWM_3_DSI */
659&pwm1 {
660	pinctrl-names = "default";
661	pinctrl-0 = <&pinctrl_pwm_1>;
662	#pwm-cells = <3>;
663};
664
665/* Verdin PWM_1 */
666&pwm2 {
667	pinctrl-names = "default";
668	pinctrl-0 = <&pinctrl_pwm_2>;
669	#pwm-cells = <3>;
670};
671
672/* Verdin PWM_2 */
673&pwm3 {
674	pinctrl-names = "default";
675	pinctrl-0 = <&pinctrl_pwm_3>;
676	#pwm-cells = <3>;
677};
678
679/* Verdin I2S_1 */
680&sai2 {
681	#sound-dai-cells = <0>;
682	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
683	assigned-clock-rates = <24576000>;
684	assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
685	pinctrl-names = "default";
686	pinctrl-0 = <&pinctrl_sai2>;
687};
688
689&snvs_pwrkey {
690	status = "okay";
691};
692
693/* Verdin UART_3, used as the Linux console */
694&uart1 {
695	pinctrl-names = "default";
696	pinctrl-0 = <&pinctrl_uart1>;
697};
698
699/* Verdin UART_1 */
700&uart2 {
701	pinctrl-names = "default";
702	pinctrl-0 = <&pinctrl_uart2>;
703	uart-has-rtscts;
704};
705
706/* Verdin UART_2 */
707&uart3 {
708	pinctrl-names = "default";
709	pinctrl-0 = <&pinctrl_uart3>;
710	uart-has-rtscts;
711};
712
713/*
714 * Verdin UART_4
715 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
716 */
717&uart4 {
718	pinctrl-names = "default";
719	pinctrl-0 = <&pinctrl_uart4>;
720};
721
722/* Verdin USB_1 */
723&usbotg1 {
724	adp-disable;
725	dr_mode = "otg";
726	hnp-disable;
727	over-current-active-low;
728	samsung,picophy-dc-vol-level-adjust = <7>;
729	samsung,picophy-pre-emp-curr-control = <3>;
730	srp-disable;
731	vbus-supply = <&reg_usb_otg1_vbus>;
732};
733
734/* Verdin USB_2 */
735&usbotg2 {
736	dr_mode = "host";
737	over-current-active-low;
738	samsung,picophy-dc-vol-level-adjust = <7>;
739	samsung,picophy-pre-emp-curr-control = <3>;
740	vbus-supply = <&reg_usb_otg2_vbus>;
741};
742
743&usbphynop1 {
744	vcc-supply = <&reg_vdd_3v3>;
745};
746
747&usbphynop2 {
748	vcc-supply = <&reg_vdd_3v3>;
749};
750
751/* On-module eMMC */
752&usdhc1 {
753	bus-width = <8>;
754	keep-power-in-suspend;
755	non-removable;
756	pinctrl-names = "default", "state_100mhz", "state_200mhz";
757	pinctrl-0 = <&pinctrl_usdhc1>;
758	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
759	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
760	status = "okay";
761};
762
763/* Verdin SD_1 */
764&usdhc2 {
765	bus-width = <4>;
766	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
767	disable-wp;
768	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
769	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
770	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
771	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
772	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
773	vmmc-supply = <&reg_usdhc2_vmmc>;
774};
775
776&wdog1 {
777	fsl,ext-reset-output;
778	pinctrl-names = "default";
779	pinctrl-0 = <&pinctrl_wdog>;
780	status = "okay";
781};
782
783&iomuxc {
784	pinctrl-names = "default";
785	pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
786		    <&pinctrl_gpio3>, <&pinctrl_gpio4>,
787		    <&pinctrl_gpio7>, <&pinctrl_gpio8>,
788		    <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
789		    <&pinctrl_pmic_tpm_ena>;
790
791	pinctrl_can1_int: can1intgrp {
792		fsl,pins =
793			<MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x146>;	/* CAN_1_SPI_INT#_1.8V */
794	};
795
796	pinctrl_can2_int: can2intgrp {
797		fsl,pins =
798			<MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x106>;	/* CAN_2_SPI_INT#_1.8V, unused */
799	};
800
801	pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
802		fsl,pins =
803			<MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1		0x106>;	/* SODIMM 256 */
804	};
805
806	pinctrl_ecspi2: ecspi2grp {
807		fsl,pins =
808			<MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x6>,	/* SODIMM 198 */
809			<MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x6>,	/* SODIMM 200 */
810			<MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x6>,	/* SODIMM 196 */
811			<MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x6>;	/* SODIMM 202 */
812	};
813
814	pinctrl_ecspi3: ecspi3grp {
815		fsl,pins =
816			<MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x146>,	/* CAN_2_SPI_CS#_1.8V */
817			<MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x6>,	/* CAN_SPI_SCK_1.8V */
818			<MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x6>,	/* CAN_SPI_MOSI_1.8V */
819			<MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO		0x6>,	/* CAN_SPI_MISO_1.8V */
820			<MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x6>;	/* CAN_1_SPI_CS_1.8V# */
821	};
822
823	pinctrl_fec1: fec1grp {
824		fsl,pins =
825			<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
826			<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3>,
827			<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91>,
828			<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91>,
829			<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91>,
830			<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91>,
831			<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91>,
832			<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
833			<MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f>,
834			<MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f>,
835			<MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f>,
836			<MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f>,
837			<MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f>,
838			<MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f>,
839			<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x146>;
840	};
841
842	pinctrl_fec1_sleep: fec1-sleepgrp {
843		fsl,pins =
844			<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
845			<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3>,
846			<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91>,
847			<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91>,
848			<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91>,
849			<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91>,
850			<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91>,
851			<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
852			<MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21		0x1f>,
853			<MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20		0x1f>,
854			<MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19		0x1f>,
855			<MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18		0x1f>,
856			<MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23		0x1f>,
857			<MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x1f>,
858			<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x106>;
859	};
860
861	pinctrl_flexspi0: flexspi0grp {
862		fsl,pins =
863			<MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x106>,	/* SODIMM 52 */
864			<MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x106>,	/* SODIMM 54 */
865			<MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B		0x106>,	/* SODIMM 64 */
866			<MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x106>,	/* SODIMM 56 */
867			<MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x106>,	/* SODIMM 58 */
868			<MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x106>,	/* SODIMM 60 */
869			<MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x106>,	/* SODIMM 62 */
870			<MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS		0x106>;	/* SODIMM 66 */
871	};
872
873	pinctrl_gpio1: gpio1grp {
874		fsl,pins =
875			<MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x106>;	/* SODIMM 206 */
876	};
877
878	pinctrl_gpio2: gpio2grp {
879		fsl,pins =
880			<MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5		0x106>;	/* SODIMM 208 */
881	};
882
883	pinctrl_gpio3: gpio3grp {
884		fsl,pins =
885			<MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26		0x106>;	/* SODIMM 210 */
886	};
887
888	pinctrl_gpio4: gpio4grp {
889		fsl,pins =
890			<MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27		0x106>;	/* SODIMM 212 */
891	};
892
893	pinctrl_gpio5: gpio5grp {
894		fsl,pins =
895			<MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x106>;	/* SODIMM 216 */
896	};
897
898	pinctrl_gpio6: gpio6grp {
899		fsl,pins =
900			<MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x106>;	/* SODIMM 218 */
901	};
902
903	pinctrl_gpio7: gpio7grp {
904		fsl,pins =
905			<MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x106>;	/* SODIMM 220 */
906	};
907
908	pinctrl_gpio8: gpio8grp {
909		fsl,pins =
910			<MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x106>;	/* SODIMM 222 */
911	};
912
913	/* Verdin GPIO_9_DSI (pulled-up as active-low) */
914	pinctrl_gpio_9_dsi: gpio9dsigrp {
915		fsl,pins =
916			<MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15		0x146>;	/* SODIMM 17 */
917	};
918
919	/* Verdin GPIO_10_DSI (pulled-up as active-low) */
920	pinctrl_gpio_10_dsi: gpio10dsigrp {
921		fsl,pins =
922			<MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x146>;	/* SODIMM 21 */
923	};
924
925	pinctrl_gpio_hog1: gpiohog1grp {
926		fsl,pins =
927			<MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20		0x106>,	/* SODIMM 88 */
928			<MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1		0x106>,	/* SODIMM 90 */
929			<MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2		0x106>,	/* SODIMM 92 */
930			<MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3		0x106>,	/* SODIMM 94 */
931			<MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4		0x106>,	/* SODIMM 96 */
932			<MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5		0x106>,	/* SODIMM 100 */
933			<MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0		0x106>,	/* SODIMM 102 */
934			<MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11		0x106>,	/* SODIMM 104 */
935			<MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12		0x106>,	/* SODIMM 106 */
936			<MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13		0x106>,	/* SODIMM 108 */
937			<MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x106>,	/* SODIMM 112 */
938			<MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x106>,	/* SODIMM 114 */
939			<MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16		0x106>,	/* SODIMM 116 */
940			<MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x106>,	/* SODIMM 118 */
941			<MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x106>;	/* SODIMM 120 */
942	};
943
944	pinctrl_gpio_hog2: gpiohog2grp {
945		fsl,pins =
946			<MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x106>;	/* SODIMM 91 */
947	};
948
949	pinctrl_gpio_hog3: gpiohog3grp {
950		fsl,pins =
951			<MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x146>,	/* SODIMM 157 */
952			<MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x146>;	/* SODIMM 187 */
953	};
954
955	pinctrl_gpio_keys: gpiokeysgrp {
956		fsl,pins =
957			<MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x146>;	/* SODIMM 252 */
958	};
959
960	/* On-module I2C */
961	pinctrl_i2c1: i2c1grp {
962		fsl,pins =
963			<MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x40000146>,	/* PMIC_I2C_SCL */
964			<MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x40000146>;	/* PMIC_I2C_SDA */
965	};
966
967	pinctrl_i2c1_gpio: i2c1gpiogrp {
968		fsl,pins =
969			<MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14		0x146>,	/* PMIC_I2C_SCL */
970			<MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15		0x146>;	/* PMIC_I2C_SDA */
971	};
972
973	/* Verdin I2C_4_CSI */
974	pinctrl_i2c2: i2c2grp {
975		fsl,pins =
976			<MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x40000146>,	/* SODIMM 55 */
977			<MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x40000146>;	/* SODIMM 53 */
978	};
979
980	pinctrl_i2c2_gpio: i2c2gpiogrp {
981		fsl,pins =
982			<MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x146>,	/* SODIMM 55 */
983			<MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x146>;	/* SODIMM 53 */
984	};
985
986	/* Verdin I2C_2_DSI */
987	pinctrl_i2c3: i2c3grp {
988		fsl,pins =
989			<MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000146>,	/* SODIMM 95 */
990			<MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000146>;	/* SODIMM 93 */
991	};
992
993	pinctrl_i2c3_gpio: i2c3gpiogrp {
994		fsl,pins =
995			<MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x146>,	/* SODIMM 95 */
996			<MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x146>;	/* SODIMM 93 */
997	};
998
999	/* Verdin I2C_1 */
1000	pinctrl_i2c4: i2c4grp {
1001		fsl,pins =
1002			<MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000146>,	/* SODIMM 14 */
1003			<MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000146>;	/* SODIMM 12 */
1004	};
1005
1006	pinctrl_i2c4_gpio: i2c4gpiogrp {
1007		fsl,pins =
1008			<MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20		0x146>,	/* SODIMM 14 */
1009			<MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21		0x146>;	/* SODIMM 12 */
1010	};
1011
1012	/* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1013	pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1014		fsl,pins =
1015			<MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x6>;	/* SODIMM 42 */
1016	};
1017
1018	/* Verdin I2S_2_D_OUT shared with SAI5 */
1019	pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1020		fsl,pins =
1021			<MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24		0x6>;	/* SODIMM 46 */
1022	};
1023
1024	pinctrl_pcie0: pcie0grp {
1025		fsl,pins =
1026			<MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19		0x6>,	/* SODIMM 244 */
1027			/* PMIC_EN_PCIe_CLK, unused */
1028			<MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x6>;
1029	};
1030
1031	pinctrl_pmic: pmicirqgrp {
1032		fsl,pins =
1033			<MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141>;	/* PMIC_INT# */
1034	};
1035
1036	/* Verdin PWM_3_DSI shared with GPIO1_IO1 */
1037	pinctrl_pwm_1: pwm1grp {
1038		fsl,pins =
1039			<MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT		0x6>;	/* SODIMM 19 */
1040	};
1041
1042	pinctrl_pwm_2: pwm2grp {
1043		fsl,pins =
1044			<MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT			0x6>;	/* SODIMM 15 */
1045	};
1046
1047	pinctrl_pwm_3: pwm3grp {
1048		fsl,pins =
1049			<MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT			0x6>;	/* SODIMM 16 */
1050	};
1051
1052	/* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
1053	pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
1054		fsl,pins =
1055			<MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x106>;	/* SODIMM 19 */
1056	};
1057
1058	pinctrl_reg_eth: regethgrp {
1059		fsl,pins =
1060			<MX8MM_IOMUXC_SD2_WP_GPIO2_IO20			0x146>;	/* PMIC_EN_ETH */
1061	};
1062
1063	pinctrl_reg_usb1_en: regusb1engrp {
1064		fsl,pins =
1065			<MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x106>;	/* SODIMM 155 */
1066	};
1067
1068	pinctrl_reg_usb2_en: regusb2engrp {
1069		fsl,pins =
1070			<MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x106>;	/* SODIMM 185 */
1071	};
1072
1073	pinctrl_sai2: sai2grp {
1074		fsl,pins =
1075			<MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK		0x6>,	/* SODIMM 38 */
1076			<MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0x6>,	/* SODIMM 30 */
1077			<MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0x6>,	/* SODIMM 32 */
1078			<MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0x6>,	/* SODIMM 36 */
1079			<MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0x6>;	/* SODIMM 34 */
1080	};
1081
1082	pinctrl_sai5: sai5grp {
1083		fsl,pins =
1084			<MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0		0x6>,	/* SODIMM 48 */
1085			<MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC		0x6>,	/* SODIMM 44 */
1086			<MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK		0x6>,	/* SODIMM 42 */
1087			<MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0		0x6>;	/* SODIMM 46 */
1088	};
1089
1090	/* control signal for optional ATTPM20P or SE050 */
1091	pinctrl_pmic_tpm_ena: pmictpmenagrp {
1092		fsl,pins =
1093			<MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x106>;	/* PMIC_TPM_ENA */
1094	};
1095
1096	pinctrl_tsp: tspgrp {
1097		fsl,pins =
1098			<MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6		0x6>,	/* SODIMM 148 */
1099			<MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x6>,	/* SODIMM 152 */
1100			<MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x6>,	/* SODIMM 154 */
1101			<MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x146>,	/* SODIMM 174 */
1102			<MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17		0x6>;	/* SODIMM 150 */
1103	};
1104
1105	pinctrl_uart1: uart1grp {
1106		fsl,pins =
1107			<MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX		0x146>,	/* SODIMM 147 */
1108			<MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX		0x146>;	/* SODIMM 149 */
1109	};
1110
1111	pinctrl_uart2: uart2grp {
1112		fsl,pins =
1113			<MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B		0x146>,	/* SODIMM 133 */
1114			<MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B		0x146>,	/* SODIMM 135 */
1115			<MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX		0x146>,	/* SODIMM 131 */
1116			<MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX		0x146>;	/* SODIMM 129 */
1117	};
1118
1119	pinctrl_uart3: uart3grp {
1120		fsl,pins =
1121			<MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x146>,	/* SODIMM 141 */
1122			<MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x146>,	/* SODIMM 139 */
1123			<MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x146>,	/* SODIMM 137 */
1124			<MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x146>;	/* SODIMM 143 */
1125	};
1126
1127	pinctrl_uart4: uart4grp {
1128		fsl,pins =
1129			<MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x146>,	/* SODIMM 151 */
1130			<MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x146>;	/* SODIMM 153 */
1131	};
1132
1133	pinctrl_usdhc1: usdhc1grp {
1134		fsl,pins =
1135			<MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190>,
1136			<MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0>,
1137			<MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0>,
1138			<MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0>,
1139			<MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0>,
1140			<MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0>,
1141			<MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d0>,
1142			<MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d0>,
1143			<MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d0>,
1144			<MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d0>,
1145			<MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d1>,
1146			<MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x190>;
1147	};
1148
1149	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1150		fsl,pins =
1151			<MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194>,
1152			<MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4>,
1153			<MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4>,
1154			<MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4>,
1155			<MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4>,
1156			<MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4>,
1157			<MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d4>,
1158			<MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d4>,
1159			<MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d4>,
1160			<MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d4>,
1161			<MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d1>,
1162			<MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x194>;
1163	};
1164
1165	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1166		fsl,pins =
1167			<MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196>,
1168			<MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6>,
1169			<MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6>,
1170			<MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6>,
1171			<MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6>,
1172			<MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6>,
1173			<MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d6>,
1174			<MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d6>,
1175			<MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d6>,
1176			<MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d6>,
1177			<MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d1>,
1178			<MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x196>;
1179	};
1180
1181	pinctrl_usdhc2_cd: usdhc2cdgrp {
1182		fsl,pins =
1183			<MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x6>;	/* SODIMM 84 */
1184	};
1185
1186	pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1187		fsl,pins =
1188			<MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x0>;	/* SODIMM 84 */
1189	};
1190
1191	pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1192		fsl,pins =
1193			<MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5		0x6>;	/* SODIMM 76 */
1194	};
1195
1196	/*
1197	 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
1198	 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
1199	 */
1200	pinctrl_usdhc2: usdhc2grp {
1201		fsl,pins =
1202			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,
1203			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x90>,	/* SODIMM 78 */
1204			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x90>,	/* SODIMM 74 */
1205			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x90>,	/* SODIMM 80 */
1206			<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x90>,	/* SODIMM 82 */
1207			<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x90>,	/* SODIMM 70 */
1208			<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x90>;	/* SODIMM 72 */
1209	};
1210
1211	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1212		fsl,pins =
1213			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,
1214			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x94>,
1215			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x94>,
1216			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x94>,
1217			<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x94>,
1218			<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x94>,
1219			<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x94>;
1220	};
1221
1222	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1223		fsl,pins =
1224			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,
1225			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x96>,
1226			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x96>,
1227			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x96>,
1228			<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x96>,
1229			<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x96>,
1230			<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x96>;
1231	};
1232
1233	/* Avoid backfeeding with removed card power */
1234	pinctrl_usdhc2_sleep: usdhc2slpgrp {
1235		fsl,pins =
1236			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x0>,
1237			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x0>,
1238			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x0>,
1239			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0>,
1240			<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x0>,
1241			<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x0>,
1242			<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x0>;
1243	};
1244
1245	/*
1246	 * On-module Wi-Fi/BT or type specific SDHC interface
1247	 * (e.g. on X52 extension slot of Verdin Development Board)
1248	 */
1249	pinctrl_usdhc3: usdhc3grp {
1250		fsl,pins =
1251			<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x150>,
1252			<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x150>,
1253			<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x150>,
1254			<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x150>,
1255			<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x150>,
1256			<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x150>;
1257	};
1258
1259	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1260		fsl,pins =
1261			<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x154>,
1262			<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x154>,
1263			<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x154>,
1264			<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x154>,
1265			<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x154>,
1266			<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x154>;
1267	};
1268
1269	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1270		fsl,pins =
1271			<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x156>,
1272			<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x156>,
1273			<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x156>,
1274			<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x156>,
1275			<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x156>,
1276			<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x156>;
1277	};
1278
1279	pinctrl_wdog: wdoggrp {
1280		fsl,pins =
1281			<MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166>;	/* PMIC_WDI */
1282	};
1283
1284	pinctrl_wifi_ctrl: wifictrlgrp {
1285		fsl,pins =
1286			<MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16		0x46>,	/* WIFI_WKUP_BT */
1287			<MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x146>,	/* WIFI_W_WKUP_HOST */
1288			<MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20		0x46>;	/* WIFI_WKUP_WLAN */
1289	};
1290
1291	pinctrl_wifi_i2s: bti2sgrp {
1292		fsl,pins =
1293			<MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK		0x6>,	/* WIFI_TX_BCLK */
1294			<MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0		0x6>,	/* WIFI_TX_DATA0 */
1295			<MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC		0x6>,	/* WIFI_TX_SYNC */
1296			<MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0		0x6>;	/* WIFI_RX_DATA0 */
1297	};
1298
1299	pinctrl_wifi_pwr_en: wifipwrengrp {
1300		fsl,pins =
1301			<MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x6>;	/* PMIC_EN_WIFI */
1302	};
1303};
1304