1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include <dt-bindings/phy/phy-imx8-pcie.h>
7#include <dt-bindings/pwm/pwm.h>
8#include "imx8mm.dtsi"
9
10/ {
11	chosen {
12		stdout-path = &uart1;
13	};
14
15	aliases {
16		rtc0 = &rtc_i2c;
17		rtc1 = &snvs_rtc;
18	};
19
20	backlight: backlight {
21		compatible = "pwm-backlight";
22		brightness-levels = <0 45 63 88 119 158 203 255>;
23		default-brightness-level = <4>;
24		/* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
25		enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
26		pinctrl-names = "default";
27		pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
28		power-supply = <&reg_3p3v>;
29		/* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
30		pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
31		status = "disabled";
32	};
33
34	/* Fixed clock dedicated to SPI CAN controller */
35	clk40m: oscillator {
36		compatible = "fixed-clock";
37		#clock-cells = <0>;
38		clock-frequency = <40000000>;
39	};
40
41	gpio-keys {
42		compatible = "gpio-keys";
43		pinctrl-names = "default";
44		pinctrl-0 = <&pinctrl_gpio_keys>;
45
46		key-wakeup {
47			debounce-interval = <10>;
48			/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
49			gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
50			label = "Wake-Up";
51			linux,code = <KEY_WAKEUP>;
52			wakeup-source;
53		};
54	};
55
56	hdmi_connector: hdmi-connector {
57		compatible = "hdmi-connector";
58		ddc-i2c-bus = <&i2c2>;
59		/* Verdin PWM_3_DSI (SODIMM 19) */
60		hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
61		label = "hdmi";
62		pinctrl-names = "default";
63		pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>;
64		type = "a";
65		status = "disabled";
66	};
67
68	panel_lvds: panel-lvds {
69		compatible = "panel-lvds";
70		backlight = <&backlight>;
71		data-mapping = "vesa-24";
72		status = "disabled";
73	};
74
75	/* Carrier Board Supplies */
76	reg_1p8v: regulator-1p8v {
77		compatible = "regulator-fixed";
78		regulator-max-microvolt = <1800000>;
79		regulator-min-microvolt = <1800000>;
80		regulator-name = "+V1.8_SW";
81	};
82
83	reg_3p3v: regulator-3p3v {
84		compatible = "regulator-fixed";
85		regulator-max-microvolt = <3300000>;
86		regulator-min-microvolt = <3300000>;
87		regulator-name = "+V3.3_SW";
88	};
89
90	reg_5p0v: regulator-5p0v {
91		compatible = "regulator-fixed";
92		regulator-max-microvolt = <5000000>;
93		regulator-min-microvolt = <5000000>;
94		regulator-name = "+V5_SW";
95	};
96
97	/* Non PMIC On-module Supplies */
98	reg_ethphy: regulator-ethphy {
99		compatible = "regulator-fixed";
100		enable-active-high;
101		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
102		off-on-delay-us = <500000>;
103		pinctrl-names = "default";
104		pinctrl-0 = <&pinctrl_reg_eth>;
105		regulator-always-on;
106		regulator-boot-on;
107		regulator-max-microvolt = <3300000>;
108		regulator-min-microvolt = <3300000>;
109		regulator-name = "On-module +V3.3_ETH";
110		startup-delay-us = <200000>;
111	};
112
113	reg_usb_otg1_vbus: regulator-usb-otg1 {
114		compatible = "regulator-fixed";
115		enable-active-high;
116		/* Verdin USB_1_EN (SODIMM 155) */
117		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
118		pinctrl-names = "default";
119		pinctrl-0 = <&pinctrl_reg_usb1_en>;
120		regulator-max-microvolt = <5000000>;
121		regulator-min-microvolt = <5000000>;
122		regulator-name = "USB_1_EN";
123	};
124
125	reg_usb_otg2_vbus: regulator-usb-otg2 {
126		compatible = "regulator-fixed";
127		enable-active-high;
128		/* Verdin USB_2_EN (SODIMM 185) */
129		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
130		pinctrl-names = "default";
131		pinctrl-0 = <&pinctrl_reg_usb2_en>;
132		regulator-max-microvolt = <5000000>;
133		regulator-min-microvolt = <5000000>;
134		regulator-name = "USB_2_EN";
135	};
136
137	reg_usdhc2_vmmc: regulator-usdhc2 {
138		compatible = "regulator-fixed";
139		enable-active-high;
140		/* Verdin SD_1_PWR_EN (SODIMM 76) */
141		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
142		off-on-delay-us = <100000>;
143		pinctrl-names = "default";
144		pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
145		regulator-max-microvolt = <3300000>;
146		regulator-min-microvolt = <3300000>;
147		regulator-name = "+V3.3_SD";
148		startup-delay-us = <2000>;
149	};
150
151	reserved-memory {
152		#address-cells = <2>;
153		#size-cells = <2>;
154		ranges;
155
156		/* Use the kernel configuration settings instead */
157		/delete-node/ linux,cma;
158	};
159};
160
161&A53_0 {
162	cpu-supply = <&reg_vdd_arm>;
163};
164
165&A53_1 {
166	cpu-supply = <&reg_vdd_arm>;
167};
168
169&A53_2 {
170	cpu-supply = <&reg_vdd_arm>;
171};
172
173&A53_3 {
174	cpu-supply = <&reg_vdd_arm>;
175};
176
177&cpu_alert0 {
178	temperature = <95000>;
179};
180
181&cpu_crit0 {
182	temperature = <105000>;
183};
184
185&ddrc {
186	operating-points-v2 = <&ddrc_opp_table>;
187
188	ddrc_opp_table: opp-table {
189		compatible = "operating-points-v2";
190
191		opp-25000000 {
192			opp-hz = /bits/ 64 <25000000>;
193		};
194
195		opp-100000000 {
196			opp-hz = /bits/ 64 <100000000>;
197		};
198
199		opp-750000000 {
200			opp-hz = /bits/ 64 <750000000>;
201		};
202	};
203};
204
205/* Verdin SPI_1 */
206&ecspi2 {
207	#address-cells = <1>;
208	#size-cells = <0>;
209	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
210	pinctrl-names = "default";
211	pinctrl-0 = <&pinctrl_ecspi2>;
212};
213
214/* Verdin CAN_1 (On-module) */
215&ecspi3 {
216	#address-cells = <1>;
217	#size-cells = <0>;
218	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
219	pinctrl-names = "default";
220	pinctrl-0 = <&pinctrl_ecspi3>;
221	status = "okay";
222
223	can1: can@0 {
224		compatible = "microchip,mcp251xfd";
225		clocks = <&clk40m>;
226		interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
227		pinctrl-names = "default";
228		pinctrl-0 = <&pinctrl_can1_int>;
229		reg = <0>;
230		spi-max-frequency = <8500000>;
231	};
232};
233
234/* Verdin ETH_1 (On-module PHY) */
235&fec1 {
236	fsl,magic-packet;
237	phy-handle = <&ethphy0>;
238	phy-mode = "rgmii-id";
239	phy-supply = <&reg_ethphy>;
240	pinctrl-names = "default", "sleep";
241	pinctrl-0 = <&pinctrl_fec1>;
242	pinctrl-1 = <&pinctrl_fec1_sleep>;
243
244	mdio {
245		#address-cells = <1>;
246		#size-cells = <0>;
247
248		ethphy0: ethernet-phy@7 {
249			compatible = "ethernet-phy-ieee802.3-c22";
250			interrupt-parent = <&gpio1>;
251			interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
252			micrel,led-mode = <0>;
253			reg = <7>;
254		};
255	};
256};
257
258/* Verdin QSPI_1 */
259&flexspi {
260	pinctrl-names = "default";
261	pinctrl-0 = <&pinctrl_flexspi0>;
262};
263
264&gpio1 {
265	gpio-line-names = "SODIMM_216",
266			  "SODIMM_19",
267			  "",
268			  "",
269			  "",
270			  "",
271			  "",
272			  "",
273			  "SODIMM_220",
274			  "SODIMM_222",
275			  "",
276			  "SODIMM_218",
277			  "SODIMM_155",
278			  "SODIMM_157",
279			  "SODIMM_185",
280			  "SODIMM_187";
281};
282
283&gpio2 {
284	gpio-line-names = "",
285			  "",
286			  "",
287			  "",
288			  "",
289			  "",
290			  "",
291			  "",
292			  "",
293			  "",
294			  "",
295			  "",
296			  "SODIMM_84",
297			  "SODIMM_78",
298			  "SODIMM_74",
299			  "SODIMM_80",
300			  "SODIMM_82",
301			  "SODIMM_70",
302			  "SODIMM_72";
303};
304
305&gpio5 {
306	gpio-line-names = "SODIMM_131",
307			  "",
308			  "SODIMM_91",
309			  "SODIMM_16",
310			  "SODIMM_15",
311			  "SODIMM_208",
312			  "SODIMM_137",
313			  "SODIMM_139",
314			  "SODIMM_141",
315			  "SODIMM_143",
316			  "SODIMM_196",
317			  "SODIMM_200",
318			  "SODIMM_198",
319			  "SODIMM_202",
320			  "",
321			  "",
322			  "SODIMM_55",
323			  "SODIMM_53",
324			  "SODIMM_95",
325			  "SODIMM_93",
326			  "SODIMM_14",
327			  "SODIMM_12",
328			  "",
329			  "",
330			  "",
331			  "",
332			  "SODIMM_210",
333			  "SODIMM_212",
334			  "SODIMM_151",
335			  "SODIMM_153";
336
337	ctrl-sleep-moci-hog {
338		gpio-hog;
339		/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
340		gpios = <1 GPIO_ACTIVE_HIGH>;
341		line-name = "CTRL_SLEEP_MOCI#";
342		output-high;
343		pinctrl-names = "default";
344		pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
345	};
346};
347
348/* On-module I2C */
349&i2c1 {
350	clock-frequency = <400000>;
351	pinctrl-names = "default", "gpio";
352	pinctrl-0 = <&pinctrl_i2c1>;
353	pinctrl-1 = <&pinctrl_i2c1_gpio>;
354	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
355	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
356	status = "okay";
357
358	pca9450: pmic@25 {
359		compatible = "nxp,pca9450a";
360		interrupt-parent = <&gpio1>;
361		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
362		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
363		pinctrl-names = "default";
364		pinctrl-0 = <&pinctrl_pmic>;
365		reg = <0x25>;
366
367		/*
368		 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
369		 * behind this PMIC.
370		 */
371
372		regulators {
373			reg_vdd_soc: BUCK1 {
374				nxp,dvs-run-voltage = <850000>;
375				nxp,dvs-standby-voltage = <800000>;
376				regulator-always-on;
377				regulator-boot-on;
378				regulator-max-microvolt = <850000>;
379				regulator-min-microvolt = <800000>;
380				regulator-name = "On-module +VDD_SOC (BUCK1)";
381				regulator-ramp-delay = <3125>;
382			};
383
384			reg_vdd_arm: BUCK2 {
385				nxp,dvs-run-voltage = <950000>;
386				nxp,dvs-standby-voltage = <850000>;
387				regulator-always-on;
388				regulator-boot-on;
389				regulator-max-microvolt = <1050000>;
390				regulator-min-microvolt = <805000>;
391				regulator-name = "On-module +VDD_ARM (BUCK2)";
392				regulator-ramp-delay = <3125>;
393			};
394
395			reg_vdd_dram: BUCK3 {
396				regulator-always-on;
397				regulator-boot-on;
398				regulator-max-microvolt = <1000000>;
399				regulator-min-microvolt = <805000>;
400				regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
401			};
402
403			reg_vdd_3v3: BUCK4 {
404				regulator-always-on;
405				regulator-boot-on;
406				regulator-max-microvolt = <3300000>;
407				regulator-min-microvolt = <3300000>;
408				regulator-name = "On-module +V3.3 (BUCK4)";
409			};
410
411			reg_vdd_1v8: BUCK5 {
412				regulator-always-on;
413				regulator-boot-on;
414				regulator-max-microvolt = <1800000>;
415				regulator-min-microvolt = <1800000>;
416				regulator-name = "PWR_1V8_MOCI (BUCK5)";
417			};
418
419			reg_nvcc_dram: BUCK6 {
420				regulator-always-on;
421				regulator-boot-on;
422				regulator-max-microvolt = <1100000>;
423				regulator-min-microvolt = <1100000>;
424				regulator-name = "On-module +VDD_DDR (BUCK6)";
425			};
426
427			reg_nvcc_snvs: LDO1 {
428				regulator-always-on;
429				regulator-boot-on;
430				regulator-max-microvolt = <1800000>;
431				regulator-min-microvolt = <1800000>;
432				regulator-name = "On-module +V1.8_SNVS (LDO1)";
433			};
434
435			reg_vdd_snvs: LDO2 {
436				regulator-always-on;
437				regulator-boot-on;
438				regulator-max-microvolt = <800000>;
439				regulator-min-microvolt = <800000>;
440				regulator-name = "On-module +V0.8_SNVS (LDO2)";
441			};
442
443			reg_vdda: LDO3 {
444				regulator-always-on;
445				regulator-boot-on;
446				regulator-max-microvolt = <1800000>;
447				regulator-min-microvolt = <1800000>;
448				regulator-name = "On-module +V1.8A (LDO3)";
449			};
450
451			reg_vdd_phy: LDO4 {
452				regulator-always-on;
453				regulator-boot-on;
454				regulator-max-microvolt = <900000>;
455				regulator-min-microvolt = <900000>;
456				regulator-name = "On-module +V0.9_MIPI (LDO4)";
457			};
458
459			reg_nvcc_sd: LDO5 {
460				regulator-max-microvolt = <3300000>;
461				regulator-min-microvolt = <1800000>;
462				regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
463			};
464		};
465	};
466
467	rtc_i2c: rtc@32 {
468		compatible = "epson,rx8130";
469		reg = <0x32>;
470	};
471
472	adc@49 {
473		compatible = "ti,ads1015";
474		reg = <0x49>;
475		#address-cells = <1>;
476		#size-cells = <0>;
477
478		/* Verdin I2C_1 (ADC_4 - ADC_3) */
479		channel@0 {
480			reg = <0>;
481			ti,datarate = <4>;
482			ti,gain = <2>;
483		};
484
485		/* Verdin I2C_1 (ADC_4 - ADC_1) */
486		channel@1 {
487			reg = <1>;
488			ti,datarate = <4>;
489			ti,gain = <2>;
490		};
491
492		/* Verdin I2C_1 (ADC_3 - ADC_1) */
493		channel@2 {
494			reg = <2>;
495			ti,datarate = <4>;
496			ti,gain = <2>;
497		};
498
499		/* Verdin I2C_1 (ADC_2 - ADC_1) */
500		channel@3 {
501			reg = <3>;
502			ti,datarate = <4>;
503			ti,gain = <2>;
504		};
505
506		/* Verdin I2C_1 ADC_4 */
507		channel@4 {
508			reg = <4>;
509			ti,datarate = <4>;
510			ti,gain = <2>;
511		};
512
513		/* Verdin I2C_1 ADC_3 */
514		channel@5 {
515			reg = <5>;
516			ti,datarate = <4>;
517			ti,gain = <2>;
518		};
519
520		/* Verdin I2C_1 ADC_2 */
521		channel@6 {
522			reg = <6>;
523			ti,datarate = <4>;
524			ti,gain = <2>;
525		};
526
527		/* Verdin I2C_1 ADC_1 */
528		channel@7 {
529			reg = <7>;
530			ti,datarate = <4>;
531			ti,gain = <2>;
532		};
533	};
534
535	eeprom@50 {
536		compatible = "st,24c02";
537		pagesize = <16>;
538		reg = <0x50>;
539	};
540};
541
542/* Verdin I2C_2_DSI */
543&i2c2 {
544	clock-frequency = <10000>;
545	pinctrl-names = "default", "gpio";
546	pinctrl-0 = <&pinctrl_i2c2>;
547	pinctrl-1 = <&pinctrl_i2c2_gpio>;
548	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
549	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
550	status = "disabled";
551};
552
553/* Verdin I2C_3_HDMI N/A */
554
555/* Verdin I2C_4_CSI */
556&i2c3 {
557	clock-frequency = <400000>;
558	pinctrl-names = "default", "gpio";
559	pinctrl-0 = <&pinctrl_i2c3>;
560	pinctrl-1 = <&pinctrl_i2c3_gpio>;
561	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
562	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
563};
564
565/* Verdin I2C_1 */
566&i2c4 {
567	clock-frequency = <400000>;
568	pinctrl-names = "default", "gpio";
569	pinctrl-0 = <&pinctrl_i2c4>;
570	pinctrl-1 = <&pinctrl_i2c4_gpio>;
571	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
572	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
573
574	gpio_expander_21: gpio-expander@21 {
575		compatible = "nxp,pcal6416";
576		#gpio-cells = <2>;
577		gpio-controller;
578		reg = <0x21>;
579		vcc-supply = <&reg_3p3v>;
580		status = "disabled";
581	};
582
583	lvds_ti_sn65dsi84: bridge@2c {
584		compatible = "ti,sn65dsi84";
585		/* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
586		/* Verdin GPIO_10_DSI (SODIMM 21) */
587		enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
588		pinctrl-names = "default";
589		pinctrl-0 = <&pinctrl_gpio_10_dsi>;
590		reg = <0x2c>;
591		status = "disabled";
592	};
593
594	/* Current measurement into module VCC */
595	hwmon: hwmon@40 {
596		compatible = "ti,ina219";
597		reg = <0x40>;
598		shunt-resistor = <10000>;
599		status = "disabled";
600	};
601
602	hdmi_lontium_lt8912: hdmi@48 {
603		compatible = "lontium,lt8912b";
604		pinctrl-names = "default";
605		pinctrl-0 = <&pinctrl_gpio_10_dsi>;
606		reg = <0x48>;
607		/* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
608		/* Verdin GPIO_10_DSI (SODIMM 21) */
609		reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
610		status = "disabled";
611	};
612
613	atmel_mxt_ts: touch@4a {
614		compatible = "atmel,maxtouch";
615		/*
616		 * Verdin GPIO_9_DSI
617		 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
618		 */
619		interrupt-parent = <&gpio3>;
620		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
621		pinctrl-names = "default";
622		pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
623		reg = <0x4a>;
624		/* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
625		reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
626		status = "disabled";
627	};
628
629	/* Temperature sensor on carrier board */
630	hwmon_temp: sensor@4f {
631		compatible = "ti,tmp75c";
632		reg = <0x4f>;
633		status = "disabled";
634	};
635
636	/* EEPROM on display adapter (MIPI DSI Display Adapter) */
637	eeprom_display_adapter: eeprom@50 {
638		compatible = "st,24c02";
639		pagesize = <16>;
640		reg = <0x50>;
641		status = "disabled";
642	};
643
644	/* EEPROM on carrier board */
645	eeprom_carrier_board: eeprom@57 {
646		compatible = "st,24c02";
647		pagesize = <16>;
648		reg = <0x57>;
649		status = "disabled";
650	};
651};
652
653/* Verdin PCIE_1 */
654&pcie0 {
655	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
656			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
657	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
658				 <&clk IMX8MM_SYS_PLL2_250M>;
659	assigned-clock-rates = <10000000>, <250000000>;
660	pinctrl-names = "default";
661	pinctrl-0 = <&pinctrl_pcie0>;
662	/* PCIE_1_RESET# (SODIMM 244) */
663	reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
664};
665
666&pcie_phy {
667	clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
668	clock-names = "ref";
669	fsl,clkreq-unsupported;
670	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
671	fsl,tx-deemph-gen1 = <0x2d>;
672	fsl,tx-deemph-gen2 = <0xf>;
673};
674
675/* Verdin PWM_3_DSI */
676&pwm1 {
677	pinctrl-names = "default";
678	pinctrl-0 = <&pinctrl_pwm_1>;
679	#pwm-cells = <3>;
680};
681
682/* Verdin PWM_1 */
683&pwm2 {
684	pinctrl-names = "default";
685	pinctrl-0 = <&pinctrl_pwm_2>;
686	#pwm-cells = <3>;
687};
688
689/* Verdin PWM_2 */
690&pwm3 {
691	pinctrl-names = "default";
692	pinctrl-0 = <&pinctrl_pwm_3>;
693	#pwm-cells = <3>;
694};
695
696/* Verdin I2S_1 */
697&sai2 {
698	#sound-dai-cells = <0>;
699	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
700	assigned-clock-rates = <24576000>;
701	assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
702	pinctrl-names = "default";
703	pinctrl-0 = <&pinctrl_sai2>;
704};
705
706&snvs_pwrkey {
707	status = "okay";
708};
709
710/* Verdin UART_3, used as the Linux console */
711&uart1 {
712	pinctrl-names = "default";
713	pinctrl-0 = <&pinctrl_uart1>;
714};
715
716/* Verdin UART_1 */
717&uart2 {
718	pinctrl-names = "default";
719	pinctrl-0 = <&pinctrl_uart2>;
720	uart-has-rtscts;
721};
722
723/* Verdin UART_2 */
724&uart3 {
725	pinctrl-names = "default";
726	pinctrl-0 = <&pinctrl_uart3>;
727	uart-has-rtscts;
728};
729
730/*
731 * Verdin UART_4
732 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
733 */
734&uart4 {
735	pinctrl-names = "default";
736	pinctrl-0 = <&pinctrl_uart4>;
737};
738
739/* Verdin USB_1 */
740&usbotg1 {
741	adp-disable;
742	dr_mode = "otg";
743	hnp-disable;
744	samsung,picophy-dc-vol-level-adjust = <7>;
745	samsung,picophy-pre-emp-curr-control = <3>;
746	srp-disable;
747	vbus-supply = <&reg_usb_otg1_vbus>;
748};
749
750/* Verdin USB_2 */
751&usbotg2 {
752	dr_mode = "host";
753	samsung,picophy-dc-vol-level-adjust = <7>;
754	samsung,picophy-pre-emp-curr-control = <3>;
755	vbus-supply = <&reg_usb_otg2_vbus>;
756};
757
758&usbphynop1 {
759	vcc-supply = <&reg_vdd_3v3>;
760};
761
762&usbphynop2 {
763	power-domains = <&pgc_otg2>;
764	vcc-supply = <&reg_vdd_3v3>;
765};
766
767/* On-module eMMC */
768&usdhc1 {
769	bus-width = <8>;
770	keep-power-in-suspend;
771	non-removable;
772	pinctrl-names = "default", "state_100mhz", "state_200mhz";
773	pinctrl-0 = <&pinctrl_usdhc1>;
774	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
775	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
776	status = "okay";
777};
778
779/* Verdin SD_1 */
780&usdhc2 {
781	bus-width = <4>;
782	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
783	disable-wp;
784	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
785	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
786	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
787	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
788	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
789	vmmc-supply = <&reg_usdhc2_vmmc>;
790};
791
792&wdog1 {
793	fsl,ext-reset-output;
794	pinctrl-names = "default";
795	pinctrl-0 = <&pinctrl_wdog>;
796	status = "okay";
797};
798
799&iomuxc {
800	pinctrl-names = "default";
801	pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
802		    <&pinctrl_gpio3>, <&pinctrl_gpio4>,
803		    <&pinctrl_gpio7>, <&pinctrl_gpio8>,
804		    <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
805		    <&pinctrl_pmic_tpm_ena>;
806
807	pinctrl_can1_int: can1intgrp {
808		fsl,pins =
809			<MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x146>;	/* CAN_1_SPI_INT#_1.8V */
810	};
811
812	pinctrl_can2_int: can2intgrp {
813		fsl,pins =
814			<MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x106>;	/* CAN_2_SPI_INT#_1.8V, unused */
815	};
816
817	pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
818		fsl,pins =
819			<MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1		0x106>;	/* SODIMM 256 */
820	};
821
822	pinctrl_ecspi2: ecspi2grp {
823		fsl,pins =
824			<MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x6>,	/* SODIMM 198 */
825			<MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x6>,	/* SODIMM 200 */
826			<MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x6>,	/* SODIMM 196 */
827			<MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x6>;	/* SODIMM 202 */
828	};
829
830	pinctrl_ecspi3: ecspi3grp {
831		fsl,pins =
832			<MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x146>,	/* CAN_2_SPI_CS#_1.8V */
833			<MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x6>,	/* CAN_SPI_SCK_1.8V */
834			<MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x6>,	/* CAN_SPI_MOSI_1.8V */
835			<MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO		0x6>,	/* CAN_SPI_MISO_1.8V */
836			<MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x6>;	/* CAN_1_SPI_CS_1.8V# */
837	};
838
839	pinctrl_fec1: fec1grp {
840		fsl,pins =
841			<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
842			<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3>,
843			<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91>,
844			<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91>,
845			<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91>,
846			<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91>,
847			<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91>,
848			<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
849			<MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f>,
850			<MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f>,
851			<MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f>,
852			<MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f>,
853			<MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f>,
854			<MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f>,
855			<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x146>;
856	};
857
858	pinctrl_fec1_sleep: fec1-sleepgrp {
859		fsl,pins =
860			<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
861			<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3>,
862			<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91>,
863			<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91>,
864			<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91>,
865			<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91>,
866			<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91>,
867			<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
868			<MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21		0x1f>,
869			<MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20		0x1f>,
870			<MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19		0x1f>,
871			<MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18		0x1f>,
872			<MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23		0x1f>,
873			<MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x1f>,
874			<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x106>;
875	};
876
877	pinctrl_flexspi0: flexspi0grp {
878		fsl,pins =
879			<MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x106>,	/* SODIMM 52 */
880			<MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x106>,	/* SODIMM 54 */
881			<MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B		0x106>,	/* SODIMM 64 */
882			<MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x106>,	/* SODIMM 56 */
883			<MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x106>,	/* SODIMM 58 */
884			<MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x106>,	/* SODIMM 60 */
885			<MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x106>,	/* SODIMM 62 */
886			<MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS		0x106>;	/* SODIMM 66 */
887	};
888
889	pinctrl_gpio1: gpio1grp {
890		fsl,pins =
891			<MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x106>;	/* SODIMM 206 */
892	};
893
894	pinctrl_gpio2: gpio2grp {
895		fsl,pins =
896			<MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5		0x106>;	/* SODIMM 208 */
897	};
898
899	pinctrl_gpio3: gpio3grp {
900		fsl,pins =
901			<MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26		0x106>;	/* SODIMM 210 */
902	};
903
904	pinctrl_gpio4: gpio4grp {
905		fsl,pins =
906			<MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27		0x106>;	/* SODIMM 212 */
907	};
908
909	pinctrl_gpio5: gpio5grp {
910		fsl,pins =
911			<MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x106>;	/* SODIMM 216 */
912	};
913
914	pinctrl_gpio6: gpio6grp {
915		fsl,pins =
916			<MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x106>;	/* SODIMM 218 */
917	};
918
919	pinctrl_gpio7: gpio7grp {
920		fsl,pins =
921			<MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x106>;	/* SODIMM 220 */
922	};
923
924	pinctrl_gpio8: gpio8grp {
925		fsl,pins =
926			<MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x106>;	/* SODIMM 222 */
927	};
928
929	/* Verdin GPIO_9_DSI (pulled-up as active-low) */
930	pinctrl_gpio_9_dsi: gpio9dsigrp {
931		fsl,pins =
932			<MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15		0x1c6>;	/* SODIMM 17 */
933	};
934
935	/* Verdin GPIO_10_DSI (pulled-up as active-low) */
936	pinctrl_gpio_10_dsi: gpio10dsigrp {
937		fsl,pins =
938			<MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x146>;	/* SODIMM 21 */
939	};
940
941	pinctrl_gpio_hog1: gpiohog1grp {
942		fsl,pins =
943			<MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20		0x106>,	/* SODIMM 88 */
944			<MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1		0x106>,	/* SODIMM 90 */
945			<MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2		0x106>,	/* SODIMM 92 */
946			<MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3		0x106>,	/* SODIMM 94 */
947			<MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4		0x106>,	/* SODIMM 96 */
948			<MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5		0x106>,	/* SODIMM 100 */
949			<MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0		0x106>,	/* SODIMM 102 */
950			<MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11		0x106>,	/* SODIMM 104 */
951			<MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12		0x106>,	/* SODIMM 106 */
952			<MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13		0x106>,	/* SODIMM 108 */
953			<MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x106>,	/* SODIMM 112 */
954			<MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x106>,	/* SODIMM 114 */
955			<MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16		0x106>,	/* SODIMM 116 */
956			<MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x106>,	/* SODIMM 118 */
957			<MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x106>;	/* SODIMM 120 */
958	};
959
960	pinctrl_gpio_hog2: gpiohog2grp {
961		fsl,pins =
962			<MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x106>;	/* SODIMM 91 */
963	};
964
965	pinctrl_gpio_hog3: gpiohog3grp {
966		fsl,pins =
967			<MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x146>,	/* SODIMM 157 */
968			<MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x146>;	/* SODIMM 187 */
969	};
970
971	pinctrl_gpio_keys: gpiokeysgrp {
972		fsl,pins =
973			<MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x146>;	/* SODIMM 252 */
974	};
975
976	/* On-module I2C */
977	pinctrl_i2c1: i2c1grp {
978		fsl,pins =
979			<MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x40000146>,	/* PMIC_I2C_SCL */
980			<MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x40000146>;	/* PMIC_I2C_SDA */
981	};
982
983	pinctrl_i2c1_gpio: i2c1gpiogrp {
984		fsl,pins =
985			<MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14		0x146>,	/* PMIC_I2C_SCL */
986			<MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15		0x146>;	/* PMIC_I2C_SDA */
987	};
988
989	/* Verdin I2C_4_CSI */
990	pinctrl_i2c2: i2c2grp {
991		fsl,pins =
992			<MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x40000146>,	/* SODIMM 55 */
993			<MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x40000146>;	/* SODIMM 53 */
994	};
995
996	pinctrl_i2c2_gpio: i2c2gpiogrp {
997		fsl,pins =
998			<MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x146>,	/* SODIMM 55 */
999			<MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x146>;	/* SODIMM 53 */
1000	};
1001
1002	/* Verdin I2C_2_DSI */
1003	pinctrl_i2c3: i2c3grp {
1004		fsl,pins =
1005			<MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000146>,	/* SODIMM 95 */
1006			<MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000146>;	/* SODIMM 93 */
1007	};
1008
1009	pinctrl_i2c3_gpio: i2c3gpiogrp {
1010		fsl,pins =
1011			<MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x146>,	/* SODIMM 95 */
1012			<MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x146>;	/* SODIMM 93 */
1013	};
1014
1015	/* Verdin I2C_1 */
1016	pinctrl_i2c4: i2c4grp {
1017		fsl,pins =
1018			<MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000146>,	/* SODIMM 14 */
1019			<MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000146>;	/* SODIMM 12 */
1020	};
1021
1022	pinctrl_i2c4_gpio: i2c4gpiogrp {
1023		fsl,pins =
1024			<MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20		0x146>,	/* SODIMM 14 */
1025			<MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21		0x146>;	/* SODIMM 12 */
1026	};
1027
1028	/* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1029	pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1030		fsl,pins =
1031			<MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x6>;	/* SODIMM 42 */
1032	};
1033
1034	/* Verdin I2S_2_D_OUT shared with SAI5 */
1035	pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1036		fsl,pins =
1037			<MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24		0x6>;	/* SODIMM 46 */
1038	};
1039
1040	pinctrl_pcie0: pcie0grp {
1041		fsl,pins =
1042			<MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19		0x6>,	/* SODIMM 244 */
1043			/* PMIC_EN_PCIe_CLK, unused */
1044			<MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x6>;
1045	};
1046
1047	pinctrl_pmic: pmicirqgrp {
1048		fsl,pins =
1049			<MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141>;	/* PMIC_INT# */
1050	};
1051
1052	/* Verdin PWM_3_DSI shared with GPIO1_IO1 */
1053	pinctrl_pwm_1: pwm1grp {
1054		fsl,pins =
1055			<MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT		0x6>;	/* SODIMM 19 */
1056	};
1057
1058	pinctrl_pwm_2: pwm2grp {
1059		fsl,pins =
1060			<MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT			0x6>;	/* SODIMM 15 */
1061	};
1062
1063	pinctrl_pwm_3: pwm3grp {
1064		fsl,pins =
1065			<MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT			0x6>;	/* SODIMM 16 */
1066	};
1067
1068	/* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
1069	pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
1070		fsl,pins =
1071			<MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x106>;	/* SODIMM 19 */
1072	};
1073
1074	pinctrl_reg_eth: regethgrp {
1075		fsl,pins =
1076			<MX8MM_IOMUXC_SD2_WP_GPIO2_IO20			0x146>;	/* PMIC_EN_ETH */
1077	};
1078
1079	pinctrl_reg_usb1_en: regusb1engrp {
1080		fsl,pins =
1081			<MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x106>;	/* SODIMM 155 */
1082	};
1083
1084	pinctrl_reg_usb2_en: regusb2engrp {
1085		fsl,pins =
1086			<MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x106>;	/* SODIMM 185 */
1087	};
1088
1089	pinctrl_sai2: sai2grp {
1090		fsl,pins =
1091			<MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK		0x6>,	/* SODIMM 38 */
1092			<MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0x6>,	/* SODIMM 30 */
1093			<MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0x6>,	/* SODIMM 32 */
1094			<MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0x6>,	/* SODIMM 36 */
1095			<MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0x6>;	/* SODIMM 34 */
1096	};
1097
1098	pinctrl_sai5: sai5grp {
1099		fsl,pins =
1100			<MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0		0x6>,	/* SODIMM 48 */
1101			<MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC		0x6>,	/* SODIMM 44 */
1102			<MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK		0x6>,	/* SODIMM 42 */
1103			<MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0		0x6>;	/* SODIMM 46 */
1104	};
1105
1106	/* control signal for optional ATTPM20P or SE050 */
1107	pinctrl_pmic_tpm_ena: pmictpmenagrp {
1108		fsl,pins =
1109			<MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x106>;	/* PMIC_TPM_ENA */
1110	};
1111
1112	pinctrl_tsp: tspgrp {
1113		fsl,pins =
1114			<MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6		0x6>,	/* SODIMM 148 */
1115			<MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x6>,	/* SODIMM 152 */
1116			<MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x6>,	/* SODIMM 154 */
1117			<MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x146>,	/* SODIMM 174 */
1118			<MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17		0x6>;	/* SODIMM 150 */
1119	};
1120
1121	pinctrl_uart1: uart1grp {
1122		fsl,pins =
1123			<MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX		0x146>,	/* SODIMM 147 */
1124			<MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX		0x146>;	/* SODIMM 149 */
1125	};
1126
1127	pinctrl_uart2: uart2grp {
1128		fsl,pins =
1129			<MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B		0x146>,	/* SODIMM 133 */
1130			<MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B		0x146>,	/* SODIMM 135 */
1131			<MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX		0x146>,	/* SODIMM 131 */
1132			<MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX		0x146>;	/* SODIMM 129 */
1133	};
1134
1135	pinctrl_uart3: uart3grp {
1136		fsl,pins =
1137			<MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x146>,	/* SODIMM 141 */
1138			<MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x146>,	/* SODIMM 139 */
1139			<MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x146>,	/* SODIMM 137 */
1140			<MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x146>;	/* SODIMM 143 */
1141	};
1142
1143	pinctrl_uart4: uart4grp {
1144		fsl,pins =
1145			<MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x146>,	/* SODIMM 151 */
1146			<MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x146>;	/* SODIMM 153 */
1147	};
1148
1149	pinctrl_usdhc1: usdhc1grp {
1150		fsl,pins =
1151			<MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190>,
1152			<MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0>,
1153			<MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0>,
1154			<MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0>,
1155			<MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0>,
1156			<MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0>,
1157			<MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d0>,
1158			<MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d0>,
1159			<MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d0>,
1160			<MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d0>,
1161			<MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d1>,
1162			<MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x190>;
1163	};
1164
1165	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1166		fsl,pins =
1167			<MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194>,
1168			<MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4>,
1169			<MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4>,
1170			<MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4>,
1171			<MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4>,
1172			<MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4>,
1173			<MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d4>,
1174			<MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d4>,
1175			<MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d4>,
1176			<MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d4>,
1177			<MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d1>,
1178			<MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x194>;
1179	};
1180
1181	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1182		fsl,pins =
1183			<MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196>,
1184			<MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6>,
1185			<MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6>,
1186			<MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6>,
1187			<MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6>,
1188			<MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6>,
1189			<MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d6>,
1190			<MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d6>,
1191			<MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d6>,
1192			<MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d6>,
1193			<MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d1>,
1194			<MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x196>;
1195	};
1196
1197	pinctrl_usdhc2_cd: usdhc2cdgrp {
1198		fsl,pins =
1199			<MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x6>;	/* SODIMM 84 */
1200	};
1201
1202	pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1203		fsl,pins =
1204			<MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x0>;	/* SODIMM 84 */
1205	};
1206
1207	pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1208		fsl,pins =
1209			<MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5		0x6>;	/* SODIMM 76 */
1210	};
1211
1212	/*
1213	 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
1214	 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
1215	 */
1216	pinctrl_usdhc2: usdhc2grp {
1217		fsl,pins =
1218			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,
1219			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x90>,	/* SODIMM 78 */
1220			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x90>,	/* SODIMM 74 */
1221			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x90>,	/* SODIMM 80 */
1222			<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x90>,	/* SODIMM 82 */
1223			<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x90>,	/* SODIMM 70 */
1224			<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x90>;	/* SODIMM 72 */
1225	};
1226
1227	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1228		fsl,pins =
1229			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,
1230			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x94>,
1231			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x94>,
1232			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x94>,
1233			<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x94>,
1234			<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x94>,
1235			<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x94>;
1236	};
1237
1238	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1239		fsl,pins =
1240			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,
1241			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x96>,
1242			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x96>,
1243			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x96>,
1244			<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x96>,
1245			<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x96>,
1246			<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x96>;
1247	};
1248
1249	/* Avoid backfeeding with removed card power */
1250	pinctrl_usdhc2_sleep: usdhc2slpgrp {
1251		fsl,pins =
1252			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x0>,
1253			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x0>,
1254			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x0>,
1255			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0>,
1256			<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x0>,
1257			<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x0>,
1258			<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x0>;
1259	};
1260
1261	/*
1262	 * On-module Wi-Fi/BT or type specific SDHC interface
1263	 * (e.g. on X52 extension slot of Verdin Development Board)
1264	 */
1265	pinctrl_usdhc3: usdhc3grp {
1266		fsl,pins =
1267			<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x150>,
1268			<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x150>,
1269			<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x150>,
1270			<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x150>,
1271			<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x150>,
1272			<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x150>;
1273	};
1274
1275	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1276		fsl,pins =
1277			<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x154>,
1278			<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x154>,
1279			<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x154>,
1280			<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x154>,
1281			<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x154>,
1282			<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x154>;
1283	};
1284
1285	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1286		fsl,pins =
1287			<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x156>,
1288			<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x156>,
1289			<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x156>,
1290			<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x156>,
1291			<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x156>,
1292			<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x156>;
1293	};
1294
1295	pinctrl_wdog: wdoggrp {
1296		fsl,pins =
1297			<MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166>;	/* PMIC_WDI */
1298	};
1299
1300	pinctrl_wifi_ctrl: wifictrlgrp {
1301		fsl,pins =
1302			<MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16		0x46>,	/* WIFI_WKUP_BT */
1303			<MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x146>,	/* WIFI_W_WKUP_HOST */
1304			<MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20		0x46>;	/* WIFI_WKUP_WLAN */
1305	};
1306
1307	pinctrl_wifi_i2s: bti2sgrp {
1308		fsl,pins =
1309			<MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK		0x6>,	/* WIFI_TX_BCLK */
1310			<MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0		0x6>,	/* WIFI_TX_DATA0 */
1311			<MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC		0x6>,	/* WIFI_TX_SYNC */
1312			<MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0		0x6>;	/* WIFI_RX_DATA0 */
1313	};
1314
1315	pinctrl_wifi_pwr_en: wifipwrengrp {
1316		fsl,pins =
1317			<MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x6>;	/* PMIC_EN_WIFI */
1318	};
1319};
1320