1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include <dt-bindings/phy/phy-imx8-pcie.h> 7#include <dt-bindings/pwm/pwm.h> 8#include "imx8mm.dtsi" 9 10/ { 11 chosen { 12 stdout-path = &uart1; 13 }; 14 15 aliases { 16 rtc0 = &rtc_i2c; 17 rtc1 = &snvs_rtc; 18 }; 19 20 backlight: backlight { 21 compatible = "pwm-backlight"; 22 brightness-levels = <0 45 63 88 119 158 203 255>; 23 default-brightness-level = <4>; 24 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 25 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 28 power-supply = <®_3p3v>; 29 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; 31 status = "disabled"; 32 }; 33 34 /* Fixed clock dedicated to SPI CAN controller */ 35 clk40m: oscillator { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <40000000>; 39 }; 40 41 gpio-keys { 42 compatible = "gpio-keys"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_gpio_keys>; 45 46 key-wakeup { 47 debounce-interval = <10>; 48 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 50 label = "Wake-Up"; 51 linux,code = <KEY_WAKEUP>; 52 wakeup-source; 53 }; 54 }; 55 56 hdmi_connector: hdmi-connector { 57 compatible = "hdmi-connector"; 58 ddc-i2c-bus = <&i2c2>; 59 label = "hdmi"; 60 type = "a"; 61 status = "disabled"; 62 }; 63 64 panel_lvds: panel-lvds { 65 compatible = "panel-lvds"; 66 backlight = <&backlight>; 67 data-mapping = "vesa-24"; 68 status = "disabled"; 69 }; 70 71 /* Carrier Board Supplies */ 72 reg_1p8v: regulator-1p8v { 73 compatible = "regulator-fixed"; 74 regulator-max-microvolt = <1800000>; 75 regulator-min-microvolt = <1800000>; 76 regulator-name = "+V1.8_SW"; 77 }; 78 79 reg_3p3v: regulator-3p3v { 80 compatible = "regulator-fixed"; 81 regulator-max-microvolt = <3300000>; 82 regulator-min-microvolt = <3300000>; 83 regulator-name = "+V3.3_SW"; 84 }; 85 86 reg_5p0v: regulator-5p0v { 87 compatible = "regulator-fixed"; 88 regulator-max-microvolt = <5000000>; 89 regulator-min-microvolt = <5000000>; 90 regulator-name = "+V5_SW"; 91 }; 92 93 /* Non PMIC On-module Supplies */ 94 reg_ethphy: regulator-ethphy { 95 compatible = "regulator-fixed"; 96 enable-active-high; 97 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 98 off-on-delay = <500000>; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_reg_eth>; 101 regulator-always-on; 102 regulator-boot-on; 103 regulator-max-microvolt = <3300000>; 104 regulator-min-microvolt = <3300000>; 105 regulator-name = "On-module +V3.3_ETH"; 106 startup-delay-us = <200000>; 107 }; 108 109 reg_usb_otg1_vbus: regulator-usb-otg1 { 110 compatible = "regulator-fixed"; 111 enable-active-high; 112 /* Verdin USB_1_EN (SODIMM 155) */ 113 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_reg_usb1_en>; 116 regulator-max-microvolt = <5000000>; 117 regulator-min-microvolt = <5000000>; 118 regulator-name = "USB_1_EN"; 119 }; 120 121 reg_usb_otg2_vbus: regulator-usb-otg2 { 122 compatible = "regulator-fixed"; 123 enable-active-high; 124 /* Verdin USB_2_EN (SODIMM 185) */ 125 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_reg_usb2_en>; 128 regulator-max-microvolt = <5000000>; 129 regulator-min-microvolt = <5000000>; 130 regulator-name = "USB_2_EN"; 131 }; 132 133 reg_usdhc2_vmmc: regulator-usdhc2 { 134 compatible = "regulator-fixed"; 135 enable-active-high; 136 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 137 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 138 off-on-delay = <100000>; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 141 regulator-max-microvolt = <3300000>; 142 regulator-min-microvolt = <3300000>; 143 regulator-name = "+V3.3_SD"; 144 startup-delay-us = <2000>; 145 }; 146 147 reserved-memory { 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges; 151 152 /* Use the kernel configuration settings instead */ 153 /delete-node/ linux,cma; 154 }; 155}; 156 157&A53_0 { 158 cpu-supply = <®_vdd_arm>; 159}; 160 161&A53_1 { 162 cpu-supply = <®_vdd_arm>; 163}; 164 165&A53_2 { 166 cpu-supply = <®_vdd_arm>; 167}; 168 169&A53_3 { 170 cpu-supply = <®_vdd_arm>; 171}; 172 173&cpu_alert0 { 174 temperature = <95000>; 175}; 176 177&cpu_crit0 { 178 temperature = <105000>; 179}; 180 181&ddrc { 182 operating-points-v2 = <&ddrc_opp_table>; 183 184 ddrc_opp_table: opp-table { 185 compatible = "operating-points-v2"; 186 187 opp-25000000 { 188 opp-hz = /bits/ 64 <25000000>; 189 }; 190 191 opp-100000000 { 192 opp-hz = /bits/ 64 <100000000>; 193 }; 194 195 opp-750000000 { 196 opp-hz = /bits/ 64 <750000000>; 197 }; 198 }; 199}; 200 201/* Verdin SPI_1 */ 202&ecspi2 { 203 #address-cells = <1>; 204 #size-cells = <0>; 205 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_ecspi2>; 208}; 209 210/* Verdin CAN_1 (On-module) */ 211&ecspi3 { 212 #address-cells = <1>; 213 #size-cells = <0>; 214 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_ecspi3>; 217 status = "okay"; 218 219 can1: can@0 { 220 compatible = "microchip,mcp251xfd"; 221 clocks = <&clk40m>; 222 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_can1_int>; 225 reg = <0>; 226 spi-max-frequency = <8500000>; 227 }; 228}; 229 230/* Verdin ETH_1 (On-module PHY) */ 231&fec1 { 232 fsl,magic-packet; 233 phy-handle = <ðphy0>; 234 phy-mode = "rgmii-id"; 235 phy-supply = <®_ethphy>; 236 pinctrl-names = "default", "sleep"; 237 pinctrl-0 = <&pinctrl_fec1>; 238 pinctrl-1 = <&pinctrl_fec1_sleep>; 239 240 mdio { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 244 ethphy0: ethernet-phy@7 { 245 compatible = "ethernet-phy-ieee802.3-c22"; 246 interrupt-parent = <&gpio1>; 247 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 248 micrel,led-mode = <0>; 249 reg = <7>; 250 }; 251 }; 252}; 253 254/* Verdin QSPI_1 */ 255&flexspi { 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_flexspi0>; 258}; 259 260&gpio1 { 261 gpio-line-names = "SODIMM_216", 262 "SODIMM_19", 263 "", 264 "", 265 "", 266 "", 267 "", 268 "", 269 "SODIMM_220", 270 "SODIMM_222", 271 "", 272 "SODIMM_218", 273 "SODIMM_155", 274 "SODIMM_157", 275 "SODIMM_185", 276 "SODIMM_187"; 277}; 278 279&gpio2 { 280 gpio-line-names = "", 281 "", 282 "", 283 "", 284 "", 285 "", 286 "", 287 "", 288 "", 289 "", 290 "", 291 "", 292 "SODIMM_84", 293 "SODIMM_78", 294 "SODIMM_74", 295 "SODIMM_80", 296 "SODIMM_82", 297 "SODIMM_70", 298 "SODIMM_72"; 299}; 300 301&gpio5 { 302 gpio-line-names = "SODIMM_131", 303 "", 304 "SODIMM_91", 305 "SODIMM_16", 306 "SODIMM_15", 307 "SODIMM_208", 308 "SODIMM_137", 309 "SODIMM_139", 310 "SODIMM_141", 311 "SODIMM_143", 312 "SODIMM_196", 313 "SODIMM_200", 314 "SODIMM_198", 315 "SODIMM_202", 316 "", 317 "", 318 "SODIMM_55", 319 "SODIMM_53", 320 "SODIMM_95", 321 "SODIMM_93", 322 "SODIMM_14", 323 "SODIMM_12", 324 "", 325 "", 326 "", 327 "", 328 "SODIMM_210", 329 "SODIMM_212", 330 "SODIMM_151", 331 "SODIMM_153"; 332 333 ctrl-sleep-moci-hog { 334 gpio-hog; 335 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 336 gpios = <1 GPIO_ACTIVE_HIGH>; 337 line-name = "CTRL_SLEEP_MOCI#"; 338 output-high; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 341 }; 342}; 343 344/* On-module I2C */ 345&i2c1 { 346 clock-frequency = <400000>; 347 pinctrl-names = "default", "gpio"; 348 pinctrl-0 = <&pinctrl_i2c1>; 349 pinctrl-1 = <&pinctrl_i2c1_gpio>; 350 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 351 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 352 status = "okay"; 353 354 pca9450: pmic@25 { 355 compatible = "nxp,pca9450a"; 356 interrupt-parent = <&gpio1>; 357 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 358 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&pinctrl_pmic>; 361 reg = <0x25>; 362 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 363 364 /* 365 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC 366 * behind this PMIC. 367 */ 368 369 regulators { 370 reg_vdd_soc: BUCK1 { 371 nxp,dvs-run-voltage = <850000>; 372 nxp,dvs-standby-voltage = <800000>; 373 regulator-always-on; 374 regulator-boot-on; 375 regulator-max-microvolt = <850000>; 376 regulator-min-microvolt = <800000>; 377 regulator-name = "On-module +VDD_SOC (BUCK1)"; 378 regulator-ramp-delay = <3125>; 379 }; 380 381 reg_vdd_arm: BUCK2 { 382 nxp,dvs-run-voltage = <950000>; 383 nxp,dvs-standby-voltage = <850000>; 384 regulator-always-on; 385 regulator-boot-on; 386 regulator-max-microvolt = <1050000>; 387 regulator-min-microvolt = <805000>; 388 regulator-name = "On-module +VDD_ARM (BUCK2)"; 389 regulator-ramp-delay = <3125>; 390 }; 391 392 reg_vdd_dram: BUCK3 { 393 regulator-always-on; 394 regulator-boot-on; 395 regulator-max-microvolt = <1000000>; 396 regulator-min-microvolt = <805000>; 397 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; 398 }; 399 400 reg_vdd_3v3: BUCK4 { 401 regulator-always-on; 402 regulator-boot-on; 403 regulator-max-microvolt = <3300000>; 404 regulator-min-microvolt = <3300000>; 405 regulator-name = "On-module +V3.3 (BUCK4)"; 406 }; 407 408 reg_vdd_1v8: BUCK5 { 409 regulator-always-on; 410 regulator-boot-on; 411 regulator-max-microvolt = <1800000>; 412 regulator-min-microvolt = <1800000>; 413 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 414 }; 415 416 reg_nvcc_dram: BUCK6 { 417 regulator-always-on; 418 regulator-boot-on; 419 regulator-max-microvolt = <1100000>; 420 regulator-min-microvolt = <1100000>; 421 regulator-name = "On-module +VDD_DDR (BUCK6)"; 422 }; 423 424 reg_nvcc_snvs: LDO1 { 425 regulator-always-on; 426 regulator-boot-on; 427 regulator-max-microvolt = <1800000>; 428 regulator-min-microvolt = <1800000>; 429 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 430 }; 431 432 reg_vdd_snvs: LDO2 { 433 regulator-always-on; 434 regulator-boot-on; 435 regulator-max-microvolt = <800000>; 436 regulator-min-microvolt = <800000>; 437 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 438 }; 439 440 reg_vdda: LDO3 { 441 regulator-always-on; 442 regulator-boot-on; 443 regulator-max-microvolt = <1800000>; 444 regulator-min-microvolt = <1800000>; 445 regulator-name = "On-module +V1.8A (LDO3)"; 446 }; 447 448 reg_vdd_phy: LDO4 { 449 regulator-always-on; 450 regulator-boot-on; 451 regulator-max-microvolt = <900000>; 452 regulator-min-microvolt = <900000>; 453 regulator-name = "On-module +V0.9_MIPI (LDO4)"; 454 }; 455 456 reg_nvcc_sd: LDO5 { 457 regulator-max-microvolt = <3300000>; 458 regulator-min-microvolt = <1800000>; 459 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 460 }; 461 }; 462 }; 463 464 rtc_i2c: rtc@32 { 465 compatible = "epson,rx8130"; 466 reg = <0x32>; 467 }; 468 469 adc@49 { 470 compatible = "ti,ads1015"; 471 reg = <0x49>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 475 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 476 channel@0 { 477 reg = <0>; 478 ti,datarate = <4>; 479 ti,gain = <2>; 480 }; 481 482 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 483 channel@1 { 484 reg = <1>; 485 ti,datarate = <4>; 486 ti,gain = <2>; 487 }; 488 489 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 490 channel@2 { 491 reg = <2>; 492 ti,datarate = <4>; 493 ti,gain = <2>; 494 }; 495 496 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 497 channel@3 { 498 reg = <3>; 499 ti,datarate = <4>; 500 ti,gain = <2>; 501 }; 502 503 /* Verdin I2C_1 ADC_4 */ 504 channel@4 { 505 reg = <4>; 506 ti,datarate = <4>; 507 ti,gain = <2>; 508 }; 509 510 /* Verdin I2C_1 ADC_3 */ 511 channel@5 { 512 reg = <5>; 513 ti,datarate = <4>; 514 ti,gain = <2>; 515 }; 516 517 /* Verdin I2C_1 ADC_2 */ 518 channel@6 { 519 reg = <6>; 520 ti,datarate = <4>; 521 ti,gain = <2>; 522 }; 523 524 /* Verdin I2C_1 ADC_1 */ 525 channel@7 { 526 reg = <7>; 527 ti,datarate = <4>; 528 ti,gain = <2>; 529 }; 530 }; 531 532 eeprom@50 { 533 compatible = "st,24c02"; 534 pagesize = <16>; 535 reg = <0x50>; 536 }; 537}; 538 539/* Verdin I2C_2_DSI */ 540&i2c2 { 541 clock-frequency = <10000>; 542 pinctrl-names = "default", "gpio"; 543 pinctrl-0 = <&pinctrl_i2c2>; 544 pinctrl-1 = <&pinctrl_i2c2_gpio>; 545 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 546 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 547 status = "disabled"; 548}; 549 550/* Verdin I2C_3_HDMI N/A */ 551 552/* Verdin I2C_4_CSI */ 553&i2c3 { 554 clock-frequency = <400000>; 555 pinctrl-names = "default", "gpio"; 556 pinctrl-0 = <&pinctrl_i2c3>; 557 pinctrl-1 = <&pinctrl_i2c3_gpio>; 558 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 559 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 560}; 561 562/* Verdin I2C_1 */ 563&i2c4 { 564 clock-frequency = <400000>; 565 pinctrl-names = "default", "gpio"; 566 pinctrl-0 = <&pinctrl_i2c4>; 567 pinctrl-1 = <&pinctrl_i2c4_gpio>; 568 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 569 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 570 571 gpio_expander_21: gpio-expander@21 { 572 compatible = "nxp,pcal6416"; 573 #gpio-cells = <2>; 574 gpio-controller; 575 reg = <0x21>; 576 vcc-supply = <®_3p3v>; 577 status = "disabled"; 578 }; 579 580 lvds_ti_sn65dsi84: bridge@2c { 581 compatible = "ti,sn65dsi84"; 582 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 583 /* Verdin GPIO_10_DSI (SODIMM 21) */ 584 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 587 reg = <0x2c>; 588 status = "disabled"; 589 }; 590 591 /* Current measurement into module VCC */ 592 hwmon: hwmon@40 { 593 compatible = "ti,ina219"; 594 reg = <0x40>; 595 shunt-resistor = <10000>; 596 status = "disabled"; 597 }; 598 599 hdmi_lontium_lt8912: hdmi@48 { 600 compatible = "lontium,lt8912b"; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; 603 reg = <0x48>; 604 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 605 /* Verdin GPIO_10_DSI (SODIMM 21) */ 606 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; 607 status = "disabled"; 608 }; 609 610 atmel_mxt_ts: touch@4a { 611 compatible = "atmel,maxtouch"; 612 /* 613 * Verdin GPIO_9_DSI 614 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) 615 */ 616 interrupt-parent = <&gpio3>; 617 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 618 pinctrl-names = "default"; 619 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 620 reg = <0x4a>; 621 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 622 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 623 status = "disabled"; 624 }; 625 626 /* Temperature sensor on carrier board */ 627 hwmon_temp: sensor@4f { 628 compatible = "ti,tmp75c"; 629 reg = <0x4f>; 630 status = "disabled"; 631 }; 632 633 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 634 eeprom_display_adapter: eeprom@50 { 635 compatible = "st,24c02"; 636 pagesize = <16>; 637 reg = <0x50>; 638 status = "disabled"; 639 }; 640 641 /* EEPROM on carrier board */ 642 eeprom_carrier_board: eeprom@57 { 643 compatible = "st,24c02"; 644 pagesize = <16>; 645 reg = <0x57>; 646 status = "disabled"; 647 }; 648}; 649 650/* Verdin PCIE_1 */ 651&pcie0 { 652 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 653 <&clk IMX8MM_CLK_PCIE1_CTRL>; 654 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 655 <&clk IMX8MM_SYS_PLL2_250M>; 656 assigned-clock-rates = <10000000>, <250000000>; 657 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 658 <&clk IMX8MM_CLK_PCIE1_AUX>, 659 <&clk IMX8MM_CLK_PCIE1_PHY>; 660 clock-names = "pcie", "pcie_aux", "pcie_bus"; 661 pinctrl-names = "default"; 662 pinctrl-0 = <&pinctrl_pcie0>; 663 /* PCIE_1_RESET# (SODIMM 244) */ 664 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 665}; 666 667&pcie_phy { 668 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 669 clock-names = "ref"; 670 fsl,clkreq-unsupported; 671 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 672 fsl,tx-deemph-gen1 = <0x2d>; 673 fsl,tx-deemph-gen2 = <0xf>; 674}; 675 676/* Verdin PWM_3_DSI */ 677&pwm1 { 678 pinctrl-names = "default"; 679 pinctrl-0 = <&pinctrl_pwm_1>; 680 #pwm-cells = <3>; 681}; 682 683/* Verdin PWM_1 */ 684&pwm2 { 685 pinctrl-names = "default"; 686 pinctrl-0 = <&pinctrl_pwm_2>; 687 #pwm-cells = <3>; 688}; 689 690/* Verdin PWM_2 */ 691&pwm3 { 692 pinctrl-names = "default"; 693 pinctrl-0 = <&pinctrl_pwm_3>; 694 #pwm-cells = <3>; 695}; 696 697/* Verdin I2S_1 */ 698&sai2 { 699 #sound-dai-cells = <0>; 700 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 701 assigned-clock-rates = <24576000>; 702 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 703 pinctrl-names = "default"; 704 pinctrl-0 = <&pinctrl_sai2>; 705}; 706 707&snvs_pwrkey { 708 status = "okay"; 709}; 710 711/* Verdin UART_3, used as the Linux console */ 712&uart1 { 713 pinctrl-names = "default"; 714 pinctrl-0 = <&pinctrl_uart1>; 715}; 716 717/* Verdin UART_1 */ 718&uart2 { 719 pinctrl-names = "default"; 720 pinctrl-0 = <&pinctrl_uart2>; 721 uart-has-rtscts; 722}; 723 724/* Verdin UART_2 */ 725&uart3 { 726 pinctrl-names = "default"; 727 pinctrl-0 = <&pinctrl_uart3>; 728 uart-has-rtscts; 729}; 730 731/* 732 * Verdin UART_4 733 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS 734 */ 735&uart4 { 736 pinctrl-names = "default"; 737 pinctrl-0 = <&pinctrl_uart4>; 738}; 739 740/* Verdin USB_1 */ 741&usbotg1 { 742 adp-disable; 743 dr_mode = "otg"; 744 hnp-disable; 745 over-current-active-low; 746 samsung,picophy-dc-vol-level-adjust = <7>; 747 samsung,picophy-pre-emp-curr-control = <3>; 748 srp-disable; 749 vbus-supply = <®_usb_otg1_vbus>; 750}; 751 752/* Verdin USB_2 */ 753&usbotg2 { 754 dr_mode = "host"; 755 over-current-active-low; 756 samsung,picophy-dc-vol-level-adjust = <7>; 757 samsung,picophy-pre-emp-curr-control = <3>; 758 vbus-supply = <®_usb_otg2_vbus>; 759}; 760 761&usbphynop1 { 762 vcc-supply = <®_vdd_3v3>; 763}; 764 765&usbphynop2 { 766 power-domains = <&pgc_otg2>; 767 vcc-supply = <®_vdd_3v3>; 768}; 769 770/* On-module eMMC */ 771&usdhc1 { 772 bus-width = <8>; 773 keep-power-in-suspend; 774 non-removable; 775 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 776 pinctrl-0 = <&pinctrl_usdhc1>; 777 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 778 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 779 status = "okay"; 780}; 781 782/* Verdin SD_1 */ 783&usdhc2 { 784 bus-width = <4>; 785 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 786 disable-wp; 787 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 788 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 789 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 790 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 791 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 792 vmmc-supply = <®_usdhc2_vmmc>; 793}; 794 795&wdog1 { 796 fsl,ext-reset-output; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&pinctrl_wdog>; 799 status = "okay"; 800}; 801 802&iomuxc { 803 pinctrl-names = "default"; 804 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 805 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 806 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 807 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, 808 <&pinctrl_pmic_tpm_ena>; 809 810 pinctrl_can1_int: can1intgrp { 811 fsl,pins = 812 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */ 813 }; 814 815 pinctrl_can2_int: can2intgrp { 816 fsl,pins = 817 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */ 818 }; 819 820 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 821 fsl,pins = 822 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */ 823 }; 824 825 pinctrl_ecspi2: ecspi2grp { 826 fsl,pins = 827 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ 828 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */ 829 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */ 830 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ 831 }; 832 833 pinctrl_ecspi3: ecspi3grp { 834 fsl,pins = 835 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */ 836 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ 837 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ 838 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ 839 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */ 840 }; 841 842 pinctrl_fec1: fec1grp { 843 fsl,pins = 844 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 845 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 846 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 847 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 848 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 849 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 850 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 851 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 852 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, 853 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, 854 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, 855 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, 856 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, 857 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, 858 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; 859 }; 860 861 pinctrl_fec1_sleep: fec1-sleepgrp { 862 fsl,pins = 863 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 864 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 865 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 866 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 867 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 868 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 869 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 870 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 871 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, 872 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, 873 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, 874 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, 875 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, 876 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, 877 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; 878 }; 879 880 pinctrl_flexspi0: flexspi0grp { 881 fsl,pins = 882 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ 883 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ 884 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ 885 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ 886 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ 887 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ 888 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */ 889 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */ 890 }; 891 892 pinctrl_gpio1: gpio1grp { 893 fsl,pins = 894 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */ 895 }; 896 897 pinctrl_gpio2: gpio2grp { 898 fsl,pins = 899 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */ 900 }; 901 902 pinctrl_gpio3: gpio3grp { 903 fsl,pins = 904 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */ 905 }; 906 907 pinctrl_gpio4: gpio4grp { 908 fsl,pins = 909 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */ 910 }; 911 912 pinctrl_gpio5: gpio5grp { 913 fsl,pins = 914 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */ 915 }; 916 917 pinctrl_gpio6: gpio6grp { 918 fsl,pins = 919 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */ 920 }; 921 922 pinctrl_gpio7: gpio7grp { 923 fsl,pins = 924 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */ 925 }; 926 927 pinctrl_gpio8: gpio8grp { 928 fsl,pins = 929 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */ 930 }; 931 932 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 933 pinctrl_gpio_9_dsi: gpio9dsigrp { 934 fsl,pins = 935 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */ 936 }; 937 938 /* Verdin GPIO_10_DSI (pulled-up as active-low) */ 939 pinctrl_gpio_10_dsi: gpio10dsigrp { 940 fsl,pins = 941 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */ 942 }; 943 944 pinctrl_gpio_hog1: gpiohog1grp { 945 fsl,pins = 946 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */ 947 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */ 948 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */ 949 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */ 950 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */ 951 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */ 952 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */ 953 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */ 954 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */ 955 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */ 956 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */ 957 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */ 958 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */ 959 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */ 960 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */ 961 }; 962 963 pinctrl_gpio_hog2: gpiohog2grp { 964 fsl,pins = 965 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */ 966 }; 967 968 pinctrl_gpio_hog3: gpiohog3grp { 969 fsl,pins = 970 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */ 971 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */ 972 }; 973 974 pinctrl_gpio_keys: gpiokeysgrp { 975 fsl,pins = 976 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */ 977 }; 978 979 /* On-module I2C */ 980 pinctrl_i2c1: i2c1grp { 981 fsl,pins = 982 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */ 983 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */ 984 }; 985 986 pinctrl_i2c1_gpio: i2c1gpiogrp { 987 fsl,pins = 988 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */ 989 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */ 990 }; 991 992 /* Verdin I2C_4_CSI */ 993 pinctrl_i2c2: i2c2grp { 994 fsl,pins = 995 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */ 996 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */ 997 }; 998 999 pinctrl_i2c2_gpio: i2c2gpiogrp { 1000 fsl,pins = 1001 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */ 1002 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */ 1003 }; 1004 1005 /* Verdin I2C_2_DSI */ 1006 pinctrl_i2c3: i2c3grp { 1007 fsl,pins = 1008 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */ 1009 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */ 1010 }; 1011 1012 pinctrl_i2c3_gpio: i2c3gpiogrp { 1013 fsl,pins = 1014 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */ 1015 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */ 1016 }; 1017 1018 /* Verdin I2C_1 */ 1019 pinctrl_i2c4: i2c4grp { 1020 fsl,pins = 1021 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */ 1022 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */ 1023 }; 1024 1025 pinctrl_i2c4_gpio: i2c4gpiogrp { 1026 fsl,pins = 1027 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */ 1028 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */ 1029 }; 1030 1031 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1032 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1033 fsl,pins = 1034 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */ 1035 }; 1036 1037 /* Verdin I2S_2_D_OUT shared with SAI5 */ 1038 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1039 fsl,pins = 1040 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */ 1041 }; 1042 1043 pinctrl_pcie0: pcie0grp { 1044 fsl,pins = 1045 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ 1046 /* PMIC_EN_PCIe_CLK, unused */ 1047 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; 1048 }; 1049 1050 pinctrl_pmic: pmicirqgrp { 1051 fsl,pins = 1052 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */ 1053 }; 1054 1055 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ 1056 pinctrl_pwm_1: pwm1grp { 1057 fsl,pins = 1058 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ 1059 }; 1060 1061 pinctrl_pwm_2: pwm2grp { 1062 fsl,pins = 1063 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ 1064 }; 1065 1066 pinctrl_pwm_3: pwm3grp { 1067 fsl,pins = 1068 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ 1069 }; 1070 1071 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ 1072 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { 1073 fsl,pins = 1074 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */ 1075 }; 1076 1077 pinctrl_reg_eth: regethgrp { 1078 fsl,pins = 1079 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */ 1080 }; 1081 1082 pinctrl_reg_usb1_en: regusb1engrp { 1083 fsl,pins = 1084 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */ 1085 }; 1086 1087 pinctrl_reg_usb2_en: regusb2engrp { 1088 fsl,pins = 1089 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */ 1090 }; 1091 1092 pinctrl_sai2: sai2grp { 1093 fsl,pins = 1094 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ 1095 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */ 1096 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */ 1097 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ 1098 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ 1099 }; 1100 1101 pinctrl_sai5: sai5grp { 1102 fsl,pins = 1103 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */ 1104 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */ 1105 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */ 1106 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */ 1107 }; 1108 1109 /* control signal for optional ATTPM20P or SE050 */ 1110 pinctrl_pmic_tpm_ena: pmictpmenagrp { 1111 fsl,pins = 1112 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ 1113 }; 1114 1115 pinctrl_tsp: tspgrp { 1116 fsl,pins = 1117 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */ 1118 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */ 1119 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */ 1120 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */ 1121 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */ 1122 }; 1123 1124 pinctrl_uart1: uart1grp { 1125 fsl,pins = 1126 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */ 1127 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */ 1128 }; 1129 1130 pinctrl_uart2: uart2grp { 1131 fsl,pins = 1132 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ 1133 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */ 1134 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */ 1135 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */ 1136 }; 1137 1138 pinctrl_uart3: uart3grp { 1139 fsl,pins = 1140 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ 1141 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */ 1142 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */ 1143 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ 1144 }; 1145 1146 pinctrl_uart4: uart4grp { 1147 fsl,pins = 1148 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */ 1149 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */ 1150 }; 1151 1152 pinctrl_usdhc1: usdhc1grp { 1153 fsl,pins = 1154 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, 1155 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, 1156 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, 1157 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, 1158 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, 1159 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, 1160 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, 1161 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, 1162 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, 1163 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, 1164 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1165 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; 1166 }; 1167 1168 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1169 fsl,pins = 1170 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, 1171 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, 1172 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, 1173 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, 1174 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, 1175 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, 1176 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, 1177 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, 1178 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, 1179 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, 1180 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1181 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; 1182 }; 1183 1184 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1185 fsl,pins = 1186 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, 1187 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, 1188 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, 1189 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, 1190 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, 1191 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, 1192 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, 1193 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, 1194 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, 1195 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, 1196 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1197 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; 1198 }; 1199 1200 pinctrl_usdhc2_cd: usdhc2cdgrp { 1201 fsl,pins = 1202 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */ 1203 }; 1204 1205 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1206 fsl,pins = 1207 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */ 1208 }; 1209 1210 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1211 fsl,pins = 1212 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ 1213 }; 1214 1215 /* 1216 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the 1217 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. 1218 */ 1219 pinctrl_usdhc2: usdhc2grp { 1220 fsl,pins = 1221 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1222 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ 1223 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ 1224 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ 1225 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ 1226 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ 1227 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */ 1228 }; 1229 1230 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1231 fsl,pins = 1232 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1233 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, 1234 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, 1235 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, 1236 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, 1237 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, 1238 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>; 1239 }; 1240 1241 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1242 fsl,pins = 1243 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1244 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, 1245 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, 1246 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, 1247 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, 1248 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, 1249 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>; 1250 }; 1251 1252 /* Avoid backfeeding with removed card power */ 1253 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1254 fsl,pins = 1255 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>, 1256 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, 1257 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, 1258 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>, 1259 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>, 1260 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>, 1261 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>; 1262 }; 1263 1264 /* 1265 * On-module Wi-Fi/BT or type specific SDHC interface 1266 * (e.g. on X52 extension slot of Verdin Development Board) 1267 */ 1268 pinctrl_usdhc3: usdhc3grp { 1269 fsl,pins = 1270 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, 1271 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, 1272 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, 1273 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>, 1274 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>, 1275 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>; 1276 }; 1277 1278 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1279 fsl,pins = 1280 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, 1281 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, 1282 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, 1283 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>, 1284 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>, 1285 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>; 1286 }; 1287 1288 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1289 fsl,pins = 1290 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, 1291 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, 1292 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, 1293 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>, 1294 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>, 1295 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>; 1296 }; 1297 1298 pinctrl_wdog: wdoggrp { 1299 fsl,pins = 1300 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */ 1301 }; 1302 1303 pinctrl_wifi_ctrl: wifictrlgrp { 1304 fsl,pins = 1305 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */ 1306 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */ 1307 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */ 1308 }; 1309 1310 pinctrl_wifi_i2s: bti2sgrp { 1311 fsl,pins = 1312 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */ 1313 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */ 1314 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */ 1315 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */ 1316 }; 1317 1318 pinctrl_wifi_pwr_en: wifipwrengrp { 1319 fsl,pins = 1320 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */ 1321 }; 1322}; 1323