1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include <dt-bindings/phy/phy-imx8-pcie.h> 7#include <dt-bindings/pwm/pwm.h> 8#include "imx8mm.dtsi" 9 10/ { 11 chosen { 12 stdout-path = &uart1; 13 }; 14 15 aliases { 16 rtc0 = &rtc_i2c; 17 rtc1 = &snvs_rtc; 18 }; 19 20 backlight: backlight { 21 compatible = "pwm-backlight"; 22 brightness-levels = <0 45 63 88 119 158 203 255>; 23 default-brightness-level = <4>; 24 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 25 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 28 power-supply = <®_3p3v>; 29 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; 31 status = "disabled"; 32 }; 33 34 /* Fixed clock dedicated to SPI CAN controller */ 35 clk40m: oscillator { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <40000000>; 39 }; 40 41 gpio-keys { 42 compatible = "gpio-keys"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_gpio_keys>; 45 46 key-wakeup { 47 debounce-interval = <10>; 48 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 50 label = "Wake-Up"; 51 linux,code = <KEY_WAKEUP>; 52 wakeup-source; 53 }; 54 }; 55 56 hdmi_connector: hdmi-connector { 57 compatible = "hdmi-connector"; 58 ddc-i2c-bus = <&i2c2>; 59 /* Verdin PWM_3_DSI (SODIMM 19) */ 60 hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 61 label = "hdmi"; 62 pinctrl-names = "default"; 63 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>; 64 type = "a"; 65 status = "disabled"; 66 }; 67 68 panel_lvds: panel-lvds { 69 compatible = "panel-lvds"; 70 backlight = <&backlight>; 71 data-mapping = "vesa-24"; 72 status = "disabled"; 73 }; 74 75 /* Carrier Board Supplies */ 76 reg_1p8v: regulator-1p8v { 77 compatible = "regulator-fixed"; 78 regulator-max-microvolt = <1800000>; 79 regulator-min-microvolt = <1800000>; 80 regulator-name = "+V1.8_SW"; 81 }; 82 83 reg_3p3v: regulator-3p3v { 84 compatible = "regulator-fixed"; 85 regulator-max-microvolt = <3300000>; 86 regulator-min-microvolt = <3300000>; 87 regulator-name = "+V3.3_SW"; 88 }; 89 90 reg_5p0v: regulator-5p0v { 91 compatible = "regulator-fixed"; 92 regulator-max-microvolt = <5000000>; 93 regulator-min-microvolt = <5000000>; 94 regulator-name = "+V5_SW"; 95 }; 96 97 /* Non PMIC On-module Supplies */ 98 reg_ethphy: regulator-ethphy { 99 compatible = "regulator-fixed"; 100 enable-active-high; 101 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 102 off-on-delay = <500000>; 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_reg_eth>; 105 regulator-boot-on; 106 regulator-max-microvolt = <3300000>; 107 regulator-min-microvolt = <3300000>; 108 regulator-name = "On-module +V3.3_ETH"; 109 startup-delay-us = <200000>; 110 }; 111 112 reg_usb_otg1_vbus: regulator-usb-otg1 { 113 compatible = "regulator-fixed"; 114 enable-active-high; 115 /* Verdin USB_1_EN (SODIMM 155) */ 116 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 117 pinctrl-names = "default"; 118 pinctrl-0 = <&pinctrl_reg_usb1_en>; 119 regulator-max-microvolt = <5000000>; 120 regulator-min-microvolt = <5000000>; 121 regulator-name = "USB_1_EN"; 122 }; 123 124 reg_usb_otg2_vbus: regulator-usb-otg2 { 125 compatible = "regulator-fixed"; 126 enable-active-high; 127 /* Verdin USB_2_EN (SODIMM 185) */ 128 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_reg_usb2_en>; 131 regulator-max-microvolt = <5000000>; 132 regulator-min-microvolt = <5000000>; 133 regulator-name = "USB_2_EN"; 134 }; 135 136 reg_usdhc2_vmmc: regulator-usdhc2 { 137 compatible = "regulator-fixed"; 138 enable-active-high; 139 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 140 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 141 off-on-delay = <100000>; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 144 regulator-max-microvolt = <3300000>; 145 regulator-min-microvolt = <3300000>; 146 regulator-name = "+V3.3_SD"; 147 startup-delay-us = <2000>; 148 }; 149 150 reserved-memory { 151 #address-cells = <2>; 152 #size-cells = <2>; 153 ranges; 154 155 /* Use the kernel configuration settings instead */ 156 /delete-node/ linux,cma; 157 }; 158}; 159 160&A53_0 { 161 cpu-supply = <®_vdd_arm>; 162}; 163 164&A53_1 { 165 cpu-supply = <®_vdd_arm>; 166}; 167 168&A53_2 { 169 cpu-supply = <®_vdd_arm>; 170}; 171 172&A53_3 { 173 cpu-supply = <®_vdd_arm>; 174}; 175 176&cpu_alert0 { 177 temperature = <95000>; 178}; 179 180&cpu_crit0 { 181 temperature = <105000>; 182}; 183 184&ddrc { 185 operating-points-v2 = <&ddrc_opp_table>; 186 187 ddrc_opp_table: opp-table { 188 compatible = "operating-points-v2"; 189 190 opp-25000000 { 191 opp-hz = /bits/ 64 <25000000>; 192 }; 193 194 opp-100000000 { 195 opp-hz = /bits/ 64 <100000000>; 196 }; 197 198 opp-750000000 { 199 opp-hz = /bits/ 64 <750000000>; 200 }; 201 }; 202}; 203 204/* Verdin SPI_1 */ 205&ecspi2 { 206 #address-cells = <1>; 207 #size-cells = <0>; 208 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_ecspi2>; 211}; 212 213/* Verdin CAN_1 (On-module) */ 214&ecspi3 { 215 #address-cells = <1>; 216 #size-cells = <0>; 217 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_ecspi3>; 220 status = "okay"; 221 222 can1: can@0 { 223 compatible = "microchip,mcp251xfd"; 224 clocks = <&clk40m>; 225 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&pinctrl_can1_int>; 228 reg = <0>; 229 spi-max-frequency = <8500000>; 230 }; 231}; 232 233/* Verdin ETH_1 (On-module PHY) */ 234&fec1 { 235 fsl,magic-packet; 236 phy-handle = <ðphy0>; 237 phy-mode = "rgmii-id"; 238 phy-supply = <®_ethphy>; 239 pinctrl-names = "default", "sleep"; 240 pinctrl-0 = <&pinctrl_fec1>; 241 pinctrl-1 = <&pinctrl_fec1_sleep>; 242 243 mdio { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 247 ethphy0: ethernet-phy@7 { 248 compatible = "ethernet-phy-ieee802.3-c22"; 249 interrupt-parent = <&gpio1>; 250 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 251 micrel,led-mode = <0>; 252 reg = <7>; 253 }; 254 }; 255}; 256 257/* Verdin QSPI_1 */ 258&flexspi { 259 pinctrl-names = "default"; 260 pinctrl-0 = <&pinctrl_flexspi0>; 261}; 262 263&gpio1 { 264 gpio-line-names = "SODIMM_216", 265 "SODIMM_19", 266 "", 267 "", 268 "", 269 "", 270 "", 271 "", 272 "SODIMM_220", 273 "SODIMM_222", 274 "", 275 "SODIMM_218", 276 "SODIMM_155", 277 "SODIMM_157", 278 "SODIMM_185", 279 "SODIMM_187"; 280}; 281 282&gpio2 { 283 gpio-line-names = "", 284 "", 285 "", 286 "", 287 "", 288 "", 289 "", 290 "", 291 "", 292 "", 293 "", 294 "", 295 "SODIMM_84", 296 "SODIMM_78", 297 "SODIMM_74", 298 "SODIMM_80", 299 "SODIMM_82", 300 "SODIMM_70", 301 "SODIMM_72"; 302}; 303 304&gpio5 { 305 gpio-line-names = "SODIMM_131", 306 "", 307 "SODIMM_91", 308 "SODIMM_16", 309 "SODIMM_15", 310 "SODIMM_208", 311 "SODIMM_137", 312 "SODIMM_139", 313 "SODIMM_141", 314 "SODIMM_143", 315 "SODIMM_196", 316 "SODIMM_200", 317 "SODIMM_198", 318 "SODIMM_202", 319 "", 320 "", 321 "SODIMM_55", 322 "SODIMM_53", 323 "SODIMM_95", 324 "SODIMM_93", 325 "SODIMM_14", 326 "SODIMM_12", 327 "", 328 "", 329 "", 330 "", 331 "SODIMM_210", 332 "SODIMM_212", 333 "SODIMM_151", 334 "SODIMM_153"; 335 336 ctrl-sleep-moci-hog { 337 gpio-hog; 338 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 339 gpios = <1 GPIO_ACTIVE_HIGH>; 340 line-name = "CTRL_SLEEP_MOCI#"; 341 output-high; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 344 }; 345}; 346 347/* On-module I2C */ 348&i2c1 { 349 clock-frequency = <400000>; 350 pinctrl-names = "default", "gpio"; 351 pinctrl-0 = <&pinctrl_i2c1>; 352 pinctrl-1 = <&pinctrl_i2c1_gpio>; 353 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 354 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 355 status = "okay"; 356 357 pca9450: pmic@25 { 358 compatible = "nxp,pca9450a"; 359 interrupt-parent = <&gpio1>; 360 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 361 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 362 pinctrl-names = "default"; 363 pinctrl-0 = <&pinctrl_pmic>; 364 reg = <0x25>; 365 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 366 367 /* 368 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC 369 * behind this PMIC. 370 */ 371 372 regulators { 373 reg_vdd_soc: BUCK1 { 374 nxp,dvs-run-voltage = <850000>; 375 nxp,dvs-standby-voltage = <800000>; 376 regulator-always-on; 377 regulator-boot-on; 378 regulator-max-microvolt = <850000>; 379 regulator-min-microvolt = <800000>; 380 regulator-name = "On-module +VDD_SOC (BUCK1)"; 381 regulator-ramp-delay = <3125>; 382 }; 383 384 reg_vdd_arm: BUCK2 { 385 nxp,dvs-run-voltage = <950000>; 386 nxp,dvs-standby-voltage = <850000>; 387 regulator-always-on; 388 regulator-boot-on; 389 regulator-max-microvolt = <1050000>; 390 regulator-min-microvolt = <805000>; 391 regulator-name = "On-module +VDD_ARM (BUCK2)"; 392 regulator-ramp-delay = <3125>; 393 }; 394 395 reg_vdd_dram: BUCK3 { 396 regulator-always-on; 397 regulator-boot-on; 398 regulator-max-microvolt = <1000000>; 399 regulator-min-microvolt = <805000>; 400 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; 401 }; 402 403 reg_vdd_3v3: BUCK4 { 404 regulator-always-on; 405 regulator-boot-on; 406 regulator-max-microvolt = <3300000>; 407 regulator-min-microvolt = <3300000>; 408 regulator-name = "On-module +V3.3 (BUCK4)"; 409 }; 410 411 reg_vdd_1v8: BUCK5 { 412 regulator-always-on; 413 regulator-boot-on; 414 regulator-max-microvolt = <1800000>; 415 regulator-min-microvolt = <1800000>; 416 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 417 }; 418 419 reg_nvcc_dram: BUCK6 { 420 regulator-always-on; 421 regulator-boot-on; 422 regulator-max-microvolt = <1100000>; 423 regulator-min-microvolt = <1100000>; 424 regulator-name = "On-module +VDD_DDR (BUCK6)"; 425 }; 426 427 reg_nvcc_snvs: LDO1 { 428 regulator-always-on; 429 regulator-boot-on; 430 regulator-max-microvolt = <1800000>; 431 regulator-min-microvolt = <1800000>; 432 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 433 }; 434 435 reg_vdd_snvs: LDO2 { 436 regulator-always-on; 437 regulator-boot-on; 438 regulator-max-microvolt = <800000>; 439 regulator-min-microvolt = <800000>; 440 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 441 }; 442 443 reg_vdda: LDO3 { 444 regulator-always-on; 445 regulator-boot-on; 446 regulator-max-microvolt = <1800000>; 447 regulator-min-microvolt = <1800000>; 448 regulator-name = "On-module +V1.8A (LDO3)"; 449 }; 450 451 reg_vdd_phy: LDO4 { 452 regulator-always-on; 453 regulator-boot-on; 454 regulator-max-microvolt = <900000>; 455 regulator-min-microvolt = <900000>; 456 regulator-name = "On-module +V0.9_MIPI (LDO4)"; 457 }; 458 459 reg_nvcc_sd: LDO5 { 460 regulator-max-microvolt = <3300000>; 461 regulator-min-microvolt = <1800000>; 462 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 463 }; 464 }; 465 }; 466 467 rtc_i2c: rtc@32 { 468 compatible = "epson,rx8130"; 469 reg = <0x32>; 470 }; 471 472 adc@49 { 473 compatible = "ti,ads1015"; 474 reg = <0x49>; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 478 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 479 channel@0 { 480 reg = <0>; 481 ti,datarate = <4>; 482 ti,gain = <2>; 483 }; 484 485 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 486 channel@1 { 487 reg = <1>; 488 ti,datarate = <4>; 489 ti,gain = <2>; 490 }; 491 492 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 493 channel@2 { 494 reg = <2>; 495 ti,datarate = <4>; 496 ti,gain = <2>; 497 }; 498 499 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 500 channel@3 { 501 reg = <3>; 502 ti,datarate = <4>; 503 ti,gain = <2>; 504 }; 505 506 /* Verdin I2C_1 ADC_4 */ 507 channel@4 { 508 reg = <4>; 509 ti,datarate = <4>; 510 ti,gain = <2>; 511 }; 512 513 /* Verdin I2C_1 ADC_3 */ 514 channel@5 { 515 reg = <5>; 516 ti,datarate = <4>; 517 ti,gain = <2>; 518 }; 519 520 /* Verdin I2C_1 ADC_2 */ 521 channel@6 { 522 reg = <6>; 523 ti,datarate = <4>; 524 ti,gain = <2>; 525 }; 526 527 /* Verdin I2C_1 ADC_1 */ 528 channel@7 { 529 reg = <7>; 530 ti,datarate = <4>; 531 ti,gain = <2>; 532 }; 533 }; 534 535 eeprom@50 { 536 compatible = "st,24c02"; 537 pagesize = <16>; 538 reg = <0x50>; 539 }; 540}; 541 542/* Verdin I2C_2_DSI */ 543&i2c2 { 544 clock-frequency = <10000>; 545 pinctrl-names = "default", "gpio"; 546 pinctrl-0 = <&pinctrl_i2c2>; 547 pinctrl-1 = <&pinctrl_i2c2_gpio>; 548 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 549 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 550 status = "disabled"; 551}; 552 553/* Verdin I2C_3_HDMI N/A */ 554 555/* Verdin I2C_4_CSI */ 556&i2c3 { 557 clock-frequency = <400000>; 558 pinctrl-names = "default", "gpio"; 559 pinctrl-0 = <&pinctrl_i2c3>; 560 pinctrl-1 = <&pinctrl_i2c3_gpio>; 561 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 562 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 563}; 564 565/* Verdin I2C_1 */ 566&i2c4 { 567 clock-frequency = <400000>; 568 pinctrl-names = "default", "gpio"; 569 pinctrl-0 = <&pinctrl_i2c4>; 570 pinctrl-1 = <&pinctrl_i2c4_gpio>; 571 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 572 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 573 574 gpio_expander_21: gpio-expander@21 { 575 compatible = "nxp,pcal6416"; 576 #gpio-cells = <2>; 577 gpio-controller; 578 reg = <0x21>; 579 vcc-supply = <®_3p3v>; 580 status = "disabled"; 581 }; 582 583 lvds_ti_sn65dsi84: bridge@2c { 584 compatible = "ti,sn65dsi84"; 585 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 586 /* Verdin GPIO_10_DSI (SODIMM 21) */ 587 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 590 reg = <0x2c>; 591 status = "disabled"; 592 }; 593 594 /* Current measurement into module VCC */ 595 hwmon: hwmon@40 { 596 compatible = "ti,ina219"; 597 reg = <0x40>; 598 shunt-resistor = <10000>; 599 status = "disabled"; 600 }; 601 602 hdmi_lontium_lt8912: hdmi@48 { 603 compatible = "lontium,lt8912b"; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 606 reg = <0x48>; 607 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 608 /* Verdin GPIO_10_DSI (SODIMM 21) */ 609 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; 610 status = "disabled"; 611 }; 612 613 atmel_mxt_ts: touch@4a { 614 compatible = "atmel,maxtouch"; 615 /* 616 * Verdin GPIO_9_DSI 617 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) 618 */ 619 interrupt-parent = <&gpio3>; 620 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 621 pinctrl-names = "default"; 622 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 623 reg = <0x4a>; 624 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 625 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 626 status = "disabled"; 627 }; 628 629 /* Temperature sensor on carrier board */ 630 hwmon_temp: sensor@4f { 631 compatible = "ti,tmp75c"; 632 reg = <0x4f>; 633 status = "disabled"; 634 }; 635 636 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 637 eeprom_display_adapter: eeprom@50 { 638 compatible = "st,24c02"; 639 pagesize = <16>; 640 reg = <0x50>; 641 status = "disabled"; 642 }; 643 644 /* EEPROM on carrier board */ 645 eeprom_carrier_board: eeprom@57 { 646 compatible = "st,24c02"; 647 pagesize = <16>; 648 reg = <0x57>; 649 status = "disabled"; 650 }; 651}; 652 653/* Verdin PCIE_1 */ 654&pcie0 { 655 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 656 <&clk IMX8MM_CLK_PCIE1_CTRL>; 657 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 658 <&clk IMX8MM_SYS_PLL2_250M>; 659 assigned-clock-rates = <10000000>, <250000000>; 660 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 661 <&clk IMX8MM_CLK_PCIE1_AUX>, 662 <&clk IMX8MM_CLK_PCIE1_PHY>; 663 clock-names = "pcie", "pcie_aux", "pcie_bus"; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&pinctrl_pcie0>; 666 /* PCIE_1_RESET# (SODIMM 244) */ 667 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 668}; 669 670&pcie_phy { 671 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 672 clock-names = "ref"; 673 fsl,clkreq-unsupported; 674 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 675 fsl,tx-deemph-gen1 = <0x2d>; 676 fsl,tx-deemph-gen2 = <0xf>; 677}; 678 679/* Verdin PWM_3_DSI */ 680&pwm1 { 681 pinctrl-names = "default"; 682 pinctrl-0 = <&pinctrl_pwm_1>; 683 #pwm-cells = <3>; 684}; 685 686/* Verdin PWM_1 */ 687&pwm2 { 688 pinctrl-names = "default"; 689 pinctrl-0 = <&pinctrl_pwm_2>; 690 #pwm-cells = <3>; 691}; 692 693/* Verdin PWM_2 */ 694&pwm3 { 695 pinctrl-names = "default"; 696 pinctrl-0 = <&pinctrl_pwm_3>; 697 #pwm-cells = <3>; 698}; 699 700/* Verdin I2S_1 */ 701&sai2 { 702 #sound-dai-cells = <0>; 703 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 704 assigned-clock-rates = <24576000>; 705 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&pinctrl_sai2>; 708}; 709 710&snvs_pwrkey { 711 status = "okay"; 712}; 713 714/* Verdin UART_3, used as the Linux console */ 715&uart1 { 716 pinctrl-names = "default"; 717 pinctrl-0 = <&pinctrl_uart1>; 718}; 719 720/* Verdin UART_1 */ 721&uart2 { 722 pinctrl-names = "default"; 723 pinctrl-0 = <&pinctrl_uart2>; 724 uart-has-rtscts; 725}; 726 727/* Verdin UART_2 */ 728&uart3 { 729 pinctrl-names = "default"; 730 pinctrl-0 = <&pinctrl_uart3>; 731 uart-has-rtscts; 732}; 733 734/* 735 * Verdin UART_4 736 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS 737 */ 738&uart4 { 739 pinctrl-names = "default"; 740 pinctrl-0 = <&pinctrl_uart4>; 741}; 742 743/* Verdin USB_1 */ 744&usbotg1 { 745 adp-disable; 746 dr_mode = "otg"; 747 hnp-disable; 748 samsung,picophy-dc-vol-level-adjust = <7>; 749 samsung,picophy-pre-emp-curr-control = <3>; 750 srp-disable; 751 vbus-supply = <®_usb_otg1_vbus>; 752}; 753 754/* Verdin USB_2 */ 755&usbotg2 { 756 dr_mode = "host"; 757 samsung,picophy-dc-vol-level-adjust = <7>; 758 samsung,picophy-pre-emp-curr-control = <3>; 759 vbus-supply = <®_usb_otg2_vbus>; 760}; 761 762&usbphynop1 { 763 vcc-supply = <®_vdd_3v3>; 764}; 765 766&usbphynop2 { 767 power-domains = <&pgc_otg2>; 768 vcc-supply = <®_vdd_3v3>; 769}; 770 771/* On-module eMMC */ 772&usdhc1 { 773 bus-width = <8>; 774 keep-power-in-suspend; 775 non-removable; 776 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 777 pinctrl-0 = <&pinctrl_usdhc1>; 778 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 779 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 780 status = "okay"; 781}; 782 783/* Verdin SD_1 */ 784&usdhc2 { 785 bus-width = <4>; 786 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 787 disable-wp; 788 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 789 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 790 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 791 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 792 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 793 vmmc-supply = <®_usdhc2_vmmc>; 794}; 795 796&wdog1 { 797 fsl,ext-reset-output; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&pinctrl_wdog>; 800 status = "okay"; 801}; 802 803&iomuxc { 804 pinctrl-names = "default"; 805 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 806 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 807 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 808 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, 809 <&pinctrl_pmic_tpm_ena>; 810 811 pinctrl_can1_int: can1intgrp { 812 fsl,pins = 813 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */ 814 }; 815 816 pinctrl_can2_int: can2intgrp { 817 fsl,pins = 818 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */ 819 }; 820 821 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 822 fsl,pins = 823 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */ 824 }; 825 826 pinctrl_ecspi2: ecspi2grp { 827 fsl,pins = 828 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ 829 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */ 830 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */ 831 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ 832 }; 833 834 pinctrl_ecspi3: ecspi3grp { 835 fsl,pins = 836 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */ 837 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ 838 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ 839 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ 840 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */ 841 }; 842 843 pinctrl_fec1: fec1grp { 844 fsl,pins = 845 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 846 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 847 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 848 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 849 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 850 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 851 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 852 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 853 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, 854 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, 855 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, 856 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, 857 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, 858 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, 859 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; 860 }; 861 862 pinctrl_fec1_sleep: fec1-sleepgrp { 863 fsl,pins = 864 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 865 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 866 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 867 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 868 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 869 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 870 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 871 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 872 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, 873 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, 874 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, 875 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, 876 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, 877 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, 878 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; 879 }; 880 881 pinctrl_flexspi0: flexspi0grp { 882 fsl,pins = 883 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ 884 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ 885 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ 886 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ 887 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ 888 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ 889 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */ 890 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */ 891 }; 892 893 pinctrl_gpio1: gpio1grp { 894 fsl,pins = 895 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */ 896 }; 897 898 pinctrl_gpio2: gpio2grp { 899 fsl,pins = 900 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */ 901 }; 902 903 pinctrl_gpio3: gpio3grp { 904 fsl,pins = 905 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */ 906 }; 907 908 pinctrl_gpio4: gpio4grp { 909 fsl,pins = 910 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */ 911 }; 912 913 pinctrl_gpio5: gpio5grp { 914 fsl,pins = 915 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */ 916 }; 917 918 pinctrl_gpio6: gpio6grp { 919 fsl,pins = 920 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */ 921 }; 922 923 pinctrl_gpio7: gpio7grp { 924 fsl,pins = 925 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */ 926 }; 927 928 pinctrl_gpio8: gpio8grp { 929 fsl,pins = 930 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */ 931 }; 932 933 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 934 pinctrl_gpio_9_dsi: gpio9dsigrp { 935 fsl,pins = 936 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */ 937 }; 938 939 /* Verdin GPIO_10_DSI (pulled-up as active-low) */ 940 pinctrl_gpio_10_dsi: gpio10dsigrp { 941 fsl,pins = 942 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */ 943 }; 944 945 pinctrl_gpio_hog1: gpiohog1grp { 946 fsl,pins = 947 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */ 948 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */ 949 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */ 950 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */ 951 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */ 952 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */ 953 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */ 954 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */ 955 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */ 956 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */ 957 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */ 958 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */ 959 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */ 960 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */ 961 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */ 962 }; 963 964 pinctrl_gpio_hog2: gpiohog2grp { 965 fsl,pins = 966 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */ 967 }; 968 969 pinctrl_gpio_hog3: gpiohog3grp { 970 fsl,pins = 971 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */ 972 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */ 973 }; 974 975 pinctrl_gpio_keys: gpiokeysgrp { 976 fsl,pins = 977 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */ 978 }; 979 980 /* On-module I2C */ 981 pinctrl_i2c1: i2c1grp { 982 fsl,pins = 983 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */ 984 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */ 985 }; 986 987 pinctrl_i2c1_gpio: i2c1gpiogrp { 988 fsl,pins = 989 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */ 990 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */ 991 }; 992 993 /* Verdin I2C_4_CSI */ 994 pinctrl_i2c2: i2c2grp { 995 fsl,pins = 996 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */ 997 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */ 998 }; 999 1000 pinctrl_i2c2_gpio: i2c2gpiogrp { 1001 fsl,pins = 1002 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */ 1003 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */ 1004 }; 1005 1006 /* Verdin I2C_2_DSI */ 1007 pinctrl_i2c3: i2c3grp { 1008 fsl,pins = 1009 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */ 1010 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */ 1011 }; 1012 1013 pinctrl_i2c3_gpio: i2c3gpiogrp { 1014 fsl,pins = 1015 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */ 1016 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */ 1017 }; 1018 1019 /* Verdin I2C_1 */ 1020 pinctrl_i2c4: i2c4grp { 1021 fsl,pins = 1022 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */ 1023 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */ 1024 }; 1025 1026 pinctrl_i2c4_gpio: i2c4gpiogrp { 1027 fsl,pins = 1028 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */ 1029 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */ 1030 }; 1031 1032 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1033 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1034 fsl,pins = 1035 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */ 1036 }; 1037 1038 /* Verdin I2S_2_D_OUT shared with SAI5 */ 1039 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1040 fsl,pins = 1041 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */ 1042 }; 1043 1044 pinctrl_pcie0: pcie0grp { 1045 fsl,pins = 1046 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ 1047 /* PMIC_EN_PCIe_CLK, unused */ 1048 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; 1049 }; 1050 1051 pinctrl_pmic: pmicirqgrp { 1052 fsl,pins = 1053 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */ 1054 }; 1055 1056 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ 1057 pinctrl_pwm_1: pwm1grp { 1058 fsl,pins = 1059 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ 1060 }; 1061 1062 pinctrl_pwm_2: pwm2grp { 1063 fsl,pins = 1064 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ 1065 }; 1066 1067 pinctrl_pwm_3: pwm3grp { 1068 fsl,pins = 1069 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ 1070 }; 1071 1072 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ 1073 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { 1074 fsl,pins = 1075 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */ 1076 }; 1077 1078 pinctrl_reg_eth: regethgrp { 1079 fsl,pins = 1080 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */ 1081 }; 1082 1083 pinctrl_reg_usb1_en: regusb1engrp { 1084 fsl,pins = 1085 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */ 1086 }; 1087 1088 pinctrl_reg_usb2_en: regusb2engrp { 1089 fsl,pins = 1090 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */ 1091 }; 1092 1093 pinctrl_sai2: sai2grp { 1094 fsl,pins = 1095 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ 1096 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */ 1097 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */ 1098 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ 1099 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ 1100 }; 1101 1102 pinctrl_sai5: sai5grp { 1103 fsl,pins = 1104 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */ 1105 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */ 1106 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */ 1107 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */ 1108 }; 1109 1110 /* control signal for optional ATTPM20P or SE050 */ 1111 pinctrl_pmic_tpm_ena: pmictpmenagrp { 1112 fsl,pins = 1113 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ 1114 }; 1115 1116 pinctrl_tsp: tspgrp { 1117 fsl,pins = 1118 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */ 1119 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */ 1120 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */ 1121 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */ 1122 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */ 1123 }; 1124 1125 pinctrl_uart1: uart1grp { 1126 fsl,pins = 1127 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */ 1128 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */ 1129 }; 1130 1131 pinctrl_uart2: uart2grp { 1132 fsl,pins = 1133 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ 1134 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */ 1135 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */ 1136 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */ 1137 }; 1138 1139 pinctrl_uart3: uart3grp { 1140 fsl,pins = 1141 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ 1142 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */ 1143 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */ 1144 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ 1145 }; 1146 1147 pinctrl_uart4: uart4grp { 1148 fsl,pins = 1149 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */ 1150 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */ 1151 }; 1152 1153 pinctrl_usdhc1: usdhc1grp { 1154 fsl,pins = 1155 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, 1156 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, 1157 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, 1158 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, 1159 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, 1160 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, 1161 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, 1162 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, 1163 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, 1164 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, 1165 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1166 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; 1167 }; 1168 1169 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1170 fsl,pins = 1171 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, 1172 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, 1173 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, 1174 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, 1175 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, 1176 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, 1177 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, 1178 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, 1179 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, 1180 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, 1181 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1182 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; 1183 }; 1184 1185 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1186 fsl,pins = 1187 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, 1188 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, 1189 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, 1190 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, 1191 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, 1192 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, 1193 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, 1194 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, 1195 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, 1196 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, 1197 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1198 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; 1199 }; 1200 1201 pinctrl_usdhc2_cd: usdhc2cdgrp { 1202 fsl,pins = 1203 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */ 1204 }; 1205 1206 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1207 fsl,pins = 1208 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */ 1209 }; 1210 1211 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1212 fsl,pins = 1213 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ 1214 }; 1215 1216 /* 1217 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the 1218 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. 1219 */ 1220 pinctrl_usdhc2: usdhc2grp { 1221 fsl,pins = 1222 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1223 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ 1224 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ 1225 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ 1226 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ 1227 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ 1228 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */ 1229 }; 1230 1231 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1232 fsl,pins = 1233 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1234 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, 1235 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, 1236 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, 1237 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, 1238 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, 1239 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>; 1240 }; 1241 1242 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1243 fsl,pins = 1244 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1245 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, 1246 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, 1247 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, 1248 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, 1249 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, 1250 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>; 1251 }; 1252 1253 /* Avoid backfeeding with removed card power */ 1254 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1255 fsl,pins = 1256 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>, 1257 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, 1258 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, 1259 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>, 1260 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>, 1261 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>, 1262 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>; 1263 }; 1264 1265 /* 1266 * On-module Wi-Fi/BT or type specific SDHC interface 1267 * (e.g. on X52 extension slot of Verdin Development Board) 1268 */ 1269 pinctrl_usdhc3: usdhc3grp { 1270 fsl,pins = 1271 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, 1272 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, 1273 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, 1274 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>, 1275 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>, 1276 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>; 1277 }; 1278 1279 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1280 fsl,pins = 1281 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, 1282 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, 1283 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, 1284 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>, 1285 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>, 1286 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>; 1287 }; 1288 1289 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1290 fsl,pins = 1291 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, 1292 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, 1293 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, 1294 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>, 1295 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>, 1296 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>; 1297 }; 1298 1299 pinctrl_wdog: wdoggrp { 1300 fsl,pins = 1301 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */ 1302 }; 1303 1304 pinctrl_wifi_ctrl: wifictrlgrp { 1305 fsl,pins = 1306 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */ 1307 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */ 1308 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */ 1309 }; 1310 1311 pinctrl_wifi_i2s: bti2sgrp { 1312 fsl,pins = 1313 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */ 1314 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */ 1315 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */ 1316 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */ 1317 }; 1318 1319 pinctrl_wifi_pwr_en: wifipwrengrp { 1320 fsl,pins = 1321 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */ 1322 }; 1323}; 1324