1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include "dt-bindings/phy/phy-imx8-pcie.h" 7#include "dt-bindings/pwm/pwm.h" 8#include "imx8mm.dtsi" 9 10/ { 11 chosen { 12 stdout-path = &uart1; 13 }; 14 15 aliases { 16 rtc0 = &rtc_i2c; 17 rtc1 = &snvs_rtc; 18 }; 19 20 backlight: backlight { 21 compatible = "pwm-backlight"; 22 brightness-levels = <0 45 63 88 119 158 203 255>; 23 default-brightness-level = <4>; 24 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 25 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 28 power-supply = <®_3p3v>; 29 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; 31 status = "disabled"; 32 }; 33 34 /* Fixed clock dedicated to SPI CAN controller */ 35 clk20m: oscillator { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <20000000>; 39 }; 40 41 gpio-keys { 42 compatible = "gpio-keys"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_gpio_keys>; 45 46 wakeup { 47 debounce-interval = <10>; 48 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 50 label = "Wake-Up"; 51 linux,code = <KEY_WAKEUP>; 52 wakeup-source; 53 }; 54 }; 55 56 /* Carrier Board Supplies */ 57 reg_1p8v: regulator-1p8v { 58 compatible = "regulator-fixed"; 59 regulator-max-microvolt = <1800000>; 60 regulator-min-microvolt = <1800000>; 61 regulator-name = "+V1.8_SW"; 62 }; 63 64 reg_3p3v: regulator-3p3v { 65 compatible = "regulator-fixed"; 66 regulator-max-microvolt = <3300000>; 67 regulator-min-microvolt = <3300000>; 68 regulator-name = "+V3.3_SW"; 69 }; 70 71 reg_5p0v: regulator-5p0v { 72 compatible = "regulator-fixed"; 73 regulator-max-microvolt = <5000000>; 74 regulator-min-microvolt = <5000000>; 75 regulator-name = "+V5_SW"; 76 }; 77 78 /* Non PMIC On-module Supplies */ 79 reg_ethphy: regulator-ethphy { 80 compatible = "regulator-fixed"; 81 enable-active-high; 82 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 83 off-on-delay = <500000>; 84 pinctrl-names = "default"; 85 pinctrl-0 = <&pinctrl_reg_eth>; 86 regulator-boot-on; 87 regulator-max-microvolt = <3300000>; 88 regulator-min-microvolt = <3300000>; 89 regulator-name = "+V3.3_ETH"; 90 startup-delay-us = <200000>; 91 }; 92 93 reg_usb_otg1_vbus: regulator-usb-otg1 { 94 compatible = "regulator-fixed"; 95 enable-active-high; 96 /* Verdin USB_1_EN (SODIMM 155) */ 97 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 98 pinctrl-names = "default"; 99 pinctrl-0 = <&pinctrl_reg_usb1_en>; 100 regulator-max-microvolt = <5000000>; 101 regulator-min-microvolt = <5000000>; 102 regulator-name = "usb_otg1_vbus"; 103 }; 104 105 reg_usb_otg2_vbus: regulator-usb-otg2 { 106 compatible = "regulator-fixed"; 107 enable-active-high; 108 /* Verdin USB_2_EN (SODIMM 185) */ 109 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 110 pinctrl-names = "default"; 111 pinctrl-0 = <&pinctrl_reg_usb2_en>; 112 regulator-max-microvolt = <5000000>; 113 regulator-min-microvolt = <5000000>; 114 regulator-name = "usb_otg2_vbus"; 115 }; 116 117 reg_usdhc2_vmmc: regulator-usdhc2 { 118 compatible = "regulator-fixed"; 119 enable-active-high; 120 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 121 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 122 off-on-delay = <100000>; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 125 regulator-max-microvolt = <3300000>; 126 regulator-min-microvolt = <3300000>; 127 regulator-name = "+V3.3_SD"; 128 startup-delay-us = <2000>; 129 }; 130 131 reserved-memory { 132 #address-cells = <2>; 133 #size-cells = <2>; 134 ranges; 135 136 /* Use the kernel configuration settings instead */ 137 /delete-node/ linux,cma; 138 }; 139}; 140 141&A53_0 { 142 cpu-supply = <®_vdd_arm>; 143}; 144 145&A53_1 { 146 cpu-supply = <®_vdd_arm>; 147}; 148 149&A53_2 { 150 cpu-supply = <®_vdd_arm>; 151}; 152 153&A53_3 { 154 cpu-supply = <®_vdd_arm>; 155}; 156 157&ddrc { 158 operating-points-v2 = <&ddrc_opp_table>; 159 160 ddrc_opp_table: opp-table { 161 compatible = "operating-points-v2"; 162 163 opp-25M { 164 opp-hz = /bits/ 64 <25000000>; 165 }; 166 167 opp-100M { 168 opp-hz = /bits/ 64 <100000000>; 169 }; 170 171 opp-750M { 172 opp-hz = /bits/ 64 <750000000>; 173 }; 174 }; 175}; 176 177/* Verdin SPI_1 */ 178&ecspi2 { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_ecspi2>; 184}; 185 186/* Verdin CAN_1 (On-module) */ 187&ecspi3 { 188 #address-cells = <1>; 189 #size-cells = <0>; 190 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_ecspi3>; 193 status = "okay"; 194 195 can1: can@0 { 196 compatible = "microchip,mcp251xfd"; 197 clocks = <&clk20m>; 198 interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_can1_int>; 201 reg = <0>; 202 spi-max-frequency = <8500000>; 203 }; 204}; 205 206/* Verdin ETH_1 (On-module PHY) */ 207&fec1 { 208 fsl,magic-packet; 209 phy-handle = <ðphy0>; 210 phy-mode = "rgmii-id"; 211 phy-supply = <®_ethphy>; 212 pinctrl-names = "default", "sleep"; 213 pinctrl-0 = <&pinctrl_fec1>; 214 pinctrl-1 = <&pinctrl_fec1_sleep>; 215 216 mdio { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 220 ethphy0: ethernet-phy@7 { 221 compatible = "ethernet-phy-ieee802.3-c22"; 222 interrupt-parent = <&gpio1>; 223 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 224 micrel,led-mode = <0>; 225 reg = <7>; 226 }; 227 }; 228}; 229 230/* Verdin QSPI_1 */ 231&flexspi { 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pinctrl_flexspi0>; 234}; 235 236&gpio1 { 237 gpio-line-names = "SODIMM_216", 238 "SODIMM_19", 239 "", 240 "", 241 "", 242 "", 243 "", 244 "", 245 "SODIMM_220", 246 "SODIMM_222", 247 "", 248 "SODIMM_218", 249 "SODIMM_155", 250 "SODIMM_157", 251 "SODIMM_185", 252 "SODIMM_187"; 253}; 254 255&gpio2 { 256 gpio-line-names = "", 257 "", 258 "", 259 "", 260 "", 261 "", 262 "", 263 "", 264 "", 265 "", 266 "", 267 "", 268 "SODIMM_84", 269 "SODIMM_78", 270 "SODIMM_74", 271 "SODIMM_80", 272 "SODIMM_82", 273 "SODIMM_70", 274 "SODIMM_72"; 275}; 276 277&gpio5 { 278 gpio-line-names = "SODIMM_131", 279 "", 280 "SODIMM_91", 281 "SODIMM_16", 282 "SODIMM_15", 283 "SODIMM_208", 284 "SODIMM_137", 285 "SODIMM_139", 286 "SODIMM_141", 287 "SODIMM_143", 288 "SODIMM_196", 289 "SODIMM_200", 290 "SODIMM_198", 291 "SODIMM_202", 292 "", 293 "", 294 "SODIMM_55", 295 "SODIMM_53", 296 "SODIMM_95", 297 "SODIMM_93", 298 "SODIMM_14", 299 "SODIMM_12", 300 "", 301 "", 302 "", 303 "", 304 "SODIMM_210", 305 "SODIMM_212", 306 "SODIMM_151", 307 "SODIMM_153"; 308 309 ctrl_sleep_moci-hog { 310 gpio-hog; 311 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 312 gpios = <1 GPIO_ACTIVE_HIGH>; 313 line-name = "CTRL_SLEEP_MOCI#"; 314 output-high; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 317 }; 318}; 319 320/* On-module I2C */ 321&i2c1 { 322 clock-frequency = <400000>; 323 pinctrl-names = "default", "gpio"; 324 pinctrl-0 = <&pinctrl_i2c1>; 325 pinctrl-1 = <&pinctrl_i2c1_gpio>; 326 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 327 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 328 status = "okay"; 329 330 pca9450: pmic@25 { 331 compatible = "nxp,pca9450a"; 332 interrupt-parent = <&gpio1>; 333 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 334 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 335 pinctrl-names = "default"; 336 pinctrl-0 = <&pinctrl_pmic>; 337 reg = <0x25>; 338 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 339 340 regulators { 341 reg_vdd_soc: BUCK1 { 342 nxp,dvs-run-voltage = <850000>; 343 nxp,dvs-standby-voltage = <800000>; 344 regulator-always-on; 345 regulator-boot-on; 346 regulator-max-microvolt = <850000>; 347 regulator-min-microvolt = <800000>; 348 regulator-name = "+VDD_SOC"; 349 regulator-ramp-delay = <3125>; 350 }; 351 352 reg_vdd_arm: BUCK2 { 353 nxp,dvs-run-voltage = <950000>; 354 nxp,dvs-standby-voltage = <850000>; 355 regulator-always-on; 356 regulator-boot-on; 357 regulator-max-microvolt = <950000>; 358 regulator-min-microvolt = <850000>; 359 regulator-name = "+VDD_ARM"; 360 regulator-ramp-delay = <3125>; 361 }; 362 363 reg_vdd_dram: BUCK3 { 364 regulator-always-on; 365 regulator-boot-on; 366 regulator-max-microvolt = <950000>; 367 regulator-min-microvolt = <850000>; 368 regulator-name = "+VDD_GPU_VPU_DDR"; 369 }; 370 371 reg_vdd_3v3: BUCK4 { 372 regulator-always-on; 373 regulator-boot-on; 374 regulator-max-microvolt = <3300000>; 375 regulator-min-microvolt = <3300000>; 376 regulator-name = "+V3.3"; 377 }; 378 379 reg_vdd_1v8: BUCK5 { 380 regulator-always-on; 381 regulator-boot-on; 382 regulator-max-microvolt = <1800000>; 383 regulator-min-microvolt = <1800000>; 384 regulator-name = "PWR_1V8_MOCI"; 385 }; 386 387 reg_nvcc_dram: BUCK6 { 388 regulator-always-on; 389 regulator-boot-on; 390 regulator-max-microvolt = <1100000>; 391 regulator-min-microvolt = <1100000>; 392 regulator-name = "+VDD_DDR"; 393 }; 394 395 reg_nvcc_snvs: LDO1 { 396 regulator-always-on; 397 regulator-boot-on; 398 regulator-max-microvolt = <1800000>; 399 regulator-min-microvolt = <1800000>; 400 regulator-name = "+V1.8_SNVS"; 401 }; 402 403 reg_vdd_snvs: LDO2 { 404 regulator-always-on; 405 regulator-boot-on; 406 regulator-max-microvolt = <900000>; 407 regulator-min-microvolt = <800000>; 408 regulator-name = "+V0.8_SNVS"; 409 }; 410 411 reg_vdda: LDO3 { 412 regulator-always-on; 413 regulator-boot-on; 414 regulator-max-microvolt = <1800000>; 415 regulator-min-microvolt = <1800000>; 416 regulator-name = "+V1.8A"; 417 }; 418 419 reg_vdd_phy: LDO4 { 420 regulator-always-on; 421 regulator-boot-on; 422 regulator-max-microvolt = <900000>; 423 regulator-min-microvolt = <900000>; 424 regulator-name = "+V0.9_MIPI"; 425 }; 426 427 reg_nvcc_sd: LDO5 { 428 regulator-max-microvolt = <3300000>; 429 regulator-min-microvolt = <1800000>; 430 regulator-name = "+V3.3_1.8_SD"; 431 }; 432 }; 433 }; 434 435 rtc_i2c: rtc@32 { 436 compatible = "epson,rx8130"; 437 reg = <0x32>; 438 }; 439 440 adc@49 { 441 compatible = "ti,ads1015"; 442 reg = <0x49>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 446 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 447 channel@0 { 448 reg = <0>; 449 ti,datarate = <4>; 450 ti,gain = <2>; 451 }; 452 453 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 454 channel@1 { 455 reg = <1>; 456 ti,datarate = <4>; 457 ti,gain = <2>; 458 }; 459 460 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 461 channel@2 { 462 reg = <2>; 463 ti,datarate = <4>; 464 ti,gain = <2>; 465 }; 466 467 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 468 channel@3 { 469 reg = <3>; 470 ti,datarate = <4>; 471 ti,gain = <2>; 472 }; 473 474 /* Verdin I2C_1 ADC_4 */ 475 channel@4 { 476 reg = <4>; 477 ti,datarate = <4>; 478 ti,gain = <2>; 479 }; 480 481 /* Verdin I2C_1 ADC_3 */ 482 channel@5 { 483 reg = <5>; 484 ti,datarate = <4>; 485 ti,gain = <2>; 486 }; 487 488 /* Verdin I2C_1 ADC_2 */ 489 channel@6 { 490 reg = <6>; 491 ti,datarate = <4>; 492 ti,gain = <2>; 493 }; 494 495 /* Verdin I2C_1 ADC_1 */ 496 channel@7 { 497 reg = <7>; 498 ti,datarate = <4>; 499 ti,gain = <2>; 500 }; 501 }; 502 503 eeprom@50 { 504 compatible = "st,24c02"; 505 pagesize = <16>; 506 reg = <0x50>; 507 }; 508}; 509 510/* Verdin I2C_2_DSI */ 511&i2c2 { 512 clock-frequency = <10000>; 513 pinctrl-names = "default", "gpio"; 514 pinctrl-0 = <&pinctrl_i2c2>; 515 pinctrl-1 = <&pinctrl_i2c2_gpio>; 516 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 517 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 518 status = "disabled"; 519}; 520 521/* Verdin I2C_3_HDMI N/A */ 522 523/* Verdin I2C_4_CSI */ 524&i2c3 { 525 clock-frequency = <400000>; 526 pinctrl-names = "default", "gpio"; 527 pinctrl-0 = <&pinctrl_i2c3>; 528 pinctrl-1 = <&pinctrl_i2c3_gpio>; 529 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 530 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 531}; 532 533/* Verdin I2C_1 */ 534&i2c4 { 535 clock-frequency = <400000>; 536 pinctrl-names = "default", "gpio"; 537 pinctrl-0 = <&pinctrl_i2c4>; 538 pinctrl-1 = <&pinctrl_i2c4_gpio>; 539 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 540 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 541 542 gpio_expander_21: gpio-expander@21 { 543 compatible = "nxp,pcal6416"; 544 #gpio-cells = <2>; 545 gpio-controller; 546 reg = <0x21>; 547 vcc-supply = <®_3p3v>; 548 status = "disabled"; 549 }; 550 551 lvds_ti_sn65dsi83: bridge@2c { 552 compatible = "ti,sn65dsi83"; 553 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 554 /* Verdin GPIO_10_DSI (SODIMM 21) */ 555 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 558 reg = <0x2c>; 559 status = "disabled"; 560 }; 561 562 /* Current measurement into module VCC */ 563 hwmon: hwmon@40 { 564 compatible = "ti,ina219"; 565 reg = <0x40>; 566 shunt-resistor = <10000>; 567 status = "disabled"; 568 }; 569 570 hdmi_lontium_lt8912: hdmi@48 { 571 compatible = "lontium,lt8912b"; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; 574 reg = <0x48>; 575 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 576 /* Verdin GPIO_10_DSI (SODIMM 21) */ 577 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; 578 status = "disabled"; 579 }; 580 581 atmel_mxt_ts: touch@4a { 582 compatible = "atmel,maxtouch"; 583 /* Verdin GPIO_9_DSI */ 584 /* (TOUCH_INT#, SODIMM 17, also routed to SN65dsi83 IRQ albeit currently unused) */ 585 interrupt-parent = <&gpio3>; 586 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 587 pinctrl-names = "default"; 588 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 589 reg = <0x4a>; 590 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 591 reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; 592 status = "disabled"; 593 }; 594 595 /* Temperature sensor on carrier board */ 596 hwmon_temp: sensor@4f { 597 compatible = "ti,tmp75c"; 598 reg = <0x4f>; 599 status = "disabled"; 600 }; 601 602 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 603 eeprom_display_adapter: eeprom@50 { 604 compatible = "st,24c02"; 605 pagesize = <16>; 606 reg = <0x50>; 607 status = "disabled"; 608 }; 609 610 /* EEPROM on carrier board */ 611 eeprom_carrier_board: eeprom@57 { 612 compatible = "st,24c02"; 613 pagesize = <16>; 614 reg = <0x57>; 615 status = "disabled"; 616 }; 617}; 618 619/* Verdin PCIE_1 */ 620&pcie0 { 621 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 622 <&clk IMX8MM_CLK_PCIE1_CTRL>; 623 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 624 <&clk IMX8MM_SYS_PLL2_250M>; 625 assigned-clock-rates = <10000000>, <250000000>; 626 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, 627 <&clk IMX8MM_CLK_PCIE1_PHY>; 628 clock-names = "pcie", "pcie_aux", "pcie_bus"; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&pinctrl_pcie0>; 631 /* PCIE_1_RESET# (SODIMM 244) */ 632 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 633}; 634 635&pcie_phy { 636 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 637 fsl,clkreq-unsupported; 638 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 639 fsl,tx-deemph-gen1 = <0x2d>; 640 fsl,tx-deemph-gen2 = <0xf>; 641}; 642 643/* Verdin PWM_3_DSI */ 644&pwm1 { 645 pinctrl-names = "default"; 646 pinctrl-0 = <&pinctrl_pwm_1>; 647 #pwm-cells = <3>; 648}; 649 650/* Verdin PWM_1 */ 651&pwm2 { 652 pinctrl-names = "default"; 653 pinctrl-0 = <&pinctrl_pwm_2>; 654 #pwm-cells = <3>; 655}; 656 657/* Verdin PWM_2 */ 658&pwm3 { 659 pinctrl-names = "default"; 660 pinctrl-0 = <&pinctrl_pwm_3>; 661 #pwm-cells = <3>; 662}; 663 664/* VERDIN I2S_1 */ 665&sai2 { 666 #sound-dai-cells = <0>; 667 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 668 assigned-clock-rates = <24576000>; 669 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&pinctrl_sai2>; 672}; 673 674&snvs_pwrkey { 675 status = "okay"; 676}; 677 678/* Verdin UART_3, used as the Linux console */ 679&uart1 { 680 pinctrl-names = "default"; 681 pinctrl-0 = <&pinctrl_uart1>; 682}; 683 684/* Verdin UART_1 */ 685&uart2 { 686 pinctrl-names = "default"; 687 pinctrl-0 = <&pinctrl_uart2>; 688 uart-has-rtscts; 689}; 690 691/* Verdin UART_2 */ 692&uart3 { 693 pinctrl-names = "default"; 694 pinctrl-0 = <&pinctrl_uart3>; 695 uart-has-rtscts; 696}; 697 698/* Verdin UART_4 */ 699/* 700 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS 701 */ 702&uart4 { 703 pinctrl-names = "default"; 704 pinctrl-0 = <&pinctrl_uart4>; 705}; 706 707/* Verdin USB_1 */ 708&usbotg1 { 709 adp-disable; 710 dr_mode = "otg"; 711 hnp-disable; 712 over-current-active-low; 713 samsung,picophy-dc-vol-level-adjust = <7>; 714 samsung,picophy-pre-emp-curr-control = <3>; 715 srp-disable; 716 vbus-supply = <®_usb_otg1_vbus>; 717}; 718 719/* Verdin USB_2 */ 720&usbotg2 { 721 dr_mode = "host"; 722 over-current-active-low; 723 samsung,picophy-dc-vol-level-adjust = <7>; 724 samsung,picophy-pre-emp-curr-control = <3>; 725 vbus-supply = <®_usb_otg2_vbus>; 726}; 727 728&usbphynop1 { 729 vcc-supply = <®_vdd_3v3>; 730}; 731 732&usbphynop2 { 733 vcc-supply = <®_vdd_3v3>; 734}; 735 736/* On-module eMMC */ 737&usdhc1 { 738 bus-width = <8>; 739 keep-power-in-suspend; 740 non-removable; 741 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 742 pinctrl-0 = <&pinctrl_usdhc1>; 743 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 744 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 745 status = "okay"; 746}; 747 748/* Verdin SD_1 */ 749&usdhc2 { 750 bus-width = <4>; 751 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 752 disable-wp; 753 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 754 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 755 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 756 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 757 vmmc-supply = <®_usdhc2_vmmc>; 758}; 759 760&wdog1 { 761 fsl,ext-reset-output; 762 pinctrl-names = "default"; 763 pinctrl-0 = <&pinctrl_wdog>; 764 status = "okay"; 765}; 766 767&iomuxc { 768 pinctrl-names = "default"; 769 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 770 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 771 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 772 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, 773 <&pinctrl_pmic_tpm_ena>; 774 775 pinctrl_can1_int: can1intgrp { 776 fsl,pins = 777 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4>; /* CAN_1_SPI_INT#_1.8V */ 778 }; 779 780 pinctrl_can2_int: can2intgrp { 781 fsl,pins = 782 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4>; /* CAN_2_SPI_INT#_1.8V */ 783 }; 784 785 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 786 fsl,pins = 787 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1c4>; /* SODIMM 256 */ 788 }; 789 790 pinctrl_ecspi2: ecspi2grp { 791 fsl,pins = 792 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4>, /* SODIMM 196 */ 793 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4>, /* SODIMM 200 */ 794 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4>, /* SODIMM 198 */ 795 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4>; /* SODIMM 202 */ 796 }; 797 798 pinctrl_ecspi3: ecspi3grp { 799 fsl,pins = 800 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4>, /* CAN_SPI_SCK_1.8V */ 801 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4>, /* CAN_SPI_MOSI_1.8V */ 802 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4>, /* CAN_SPI_MISO_1.8V */ 803 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4>, /* CAN_1_SPI_CS_1.8V# */ 804 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4>; /* CAN_2_SPI_CS#_1.8V */ 805 }; 806 807 pinctrl_fec1: fec1grp { 808 fsl,pins = 809 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 810 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 811 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, 812 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, 813 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, 814 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, 815 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 816 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 817 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 818 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 819 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, 820 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 821 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 822 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, 823 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4>; 824 }; 825 826 pinctrl_fec1_sleep: fec1-sleepgrp { 827 fsl,pins = 828 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 829 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 830 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, 831 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, 832 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, 833 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, 834 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 835 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 836 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 837 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 838 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, 839 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 840 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 841 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, 842 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x184>; 843 }; 844 845 pinctrl_flexspi0: flexspi0grp { 846 fsl,pins = 847 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2>, /* SODIMM 52 */ 848 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>, /* SODIMM 54 */ 849 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82>, /* SODIMM 64 */ 850 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82>, /* SODIMM 66 */ 851 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>, /* SODIMM 56 */ 852 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>, /* SODIMM 58 */ 853 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>, /* SODIMM 60 */ 854 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>; /* SODIMM 62 */ 855 }; 856 857 pinctrl_gpio1: gpio1grp { 858 fsl,pins = 859 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184>; /* SODIMM 206 */ 860 }; 861 862 pinctrl_gpio2: gpio2grp { 863 fsl,pins = 864 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1c4>; /* SODIMM 208 */ 865 }; 866 867 pinctrl_gpio3: gpio3grp { 868 fsl,pins = 869 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184>; /* SODIMM 210 */ 870 }; 871 872 pinctrl_gpio4: gpio4grp { 873 fsl,pins = 874 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184>; /* SODIMM 212 */ 875 }; 876 877 pinctrl_gpio5: gpio5grp { 878 fsl,pins = 879 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184>; /* SODIMM 216 */ 880 }; 881 882 pinctrl_gpio6: gpio6grp { 883 fsl,pins = 884 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184>; /* SODIMM 218 */ 885 }; 886 887 pinctrl_gpio7: gpio7grp { 888 fsl,pins = 889 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184>; /* SODIMM 220 */ 890 }; 891 892 pinctrl_gpio8: gpio8grp { 893 fsl,pins = 894 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184>; /* SODIMM 222 */ 895 }; 896 897 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 898 pinctrl_gpio_9_dsi: gpio9dsigrp { 899 fsl,pins = 900 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c4>; /* SODIMM 17 */ 901 }; 902 903 /* Verdin GPIO_10_DSI */ 904 pinctrl_gpio_10_dsi: gpio10dsigrp { 905 fsl,pins = 906 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4>; /* SODIMM 21 */ 907 }; 908 909 pinctrl_gpio_hog1: gpiohog1grp { 910 fsl,pins = 911 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4>, /* SODIMM 88 */ 912 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4>, /* SODIMM 90 */ 913 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4>, /* SODIMM 92 */ 914 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4>, /* SODIMM 94 */ 915 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4>, /* SODIMM 96 */ 916 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4>, /* SODIMM 100 */ 917 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4>, /* SODIMM 102 */ 918 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4>, /* SODIMM 104 */ 919 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4>, /* SODIMM 106 */ 920 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4>, /* SODIMM 108 */ 921 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4>, /* SODIMM 112 */ 922 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4>, /* SODIMM 114 */ 923 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4>, /* SODIMM 116 */ 924 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4>, /* SODIMM 118 */ 925 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4>; /* SODIMM 120 */ 926 }; 927 928 pinctrl_gpio_hog2: gpiohog2grp { 929 fsl,pins = 930 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1c4>; /* SODIMM 91 */ 931 }; 932 933 pinctrl_gpio_hog3: gpiohog3grp { 934 fsl,pins = 935 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x1c4>, /* SODIMM 157 */ 936 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4>; /* SODIMM 187 */ 937 }; 938 939 pinctrl_gpio_keys: gpiokeysgrp { 940 fsl,pins = 941 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1c4>; /* SODIMM 252 */ 942 }; 943 944 /* On-module I2C */ 945 pinctrl_i2c1: i2c1grp { 946 fsl,pins = 947 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */ 948 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */ 949 }; 950 951 pinctrl_i2c1_gpio: i2c1gpiogrp { 952 fsl,pins = 953 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */ 954 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */ 955 }; 956 957 /* Verdin I2C_4_CSI */ 958 pinctrl_i2c2: i2c2grp { 959 fsl,pins = 960 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6>, /* SODIMM 55 */ 961 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6>; /* SODIMM 53 */ 962 }; 963 964 pinctrl_i2c2_gpio: i2c2gpiogrp { 965 fsl,pins = 966 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c6>, /* SODIMM 55 */ 967 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c6>; /* SODIMM 53 */ 968 }; 969 970 /* Verdin I2C_2_DSI */ 971 pinctrl_i2c3: i2c3grp { 972 fsl,pins = 973 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6>, /* SODIMM 95 */ 974 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6>; /* SODIMM 93 */ 975 }; 976 977 pinctrl_i2c3_gpio: i2c3gpiogrp { 978 fsl,pins = 979 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c6>, /* SODIMM 95 */ 980 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c6>; /* SODIMM 93 */ 981 }; 982 983 /* Verdin I2C_1 */ 984 pinctrl_i2c4: i2c4grp { 985 fsl,pins = 986 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6>, /* SODIMM 14 */ 987 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6>; /* SODIMM 12 */ 988 }; 989 990 pinctrl_i2c4_gpio: i2c4gpiogrp { 991 fsl,pins = 992 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c6>, /* SODIMM 14 */ 993 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c6>; /* SODIMM 12 */ 994 }; 995 996 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 997 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 998 fsl,pins = 999 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x184>; /* SODIMM 42 */ 1000 }; 1001 1002 /* Verdin I2S_2_D_OUT shared with SAI5 */ 1003 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1004 fsl,pins = 1005 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x184>; /* SODIMM 46 */ 1006 }; 1007 1008 pinctrl_pcie0: pcie0grp { 1009 fsl,pins = 1010 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ 1011 /* PMIC_EN_PCIe_CLK, unused */ 1012 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; 1013 }; 1014 1015 pinctrl_pmic: pmicirqgrp { 1016 fsl,pins = 1017 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41>; /* PMIC_INT# */ 1018 }; 1019 1020 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ 1021 pinctrl_pwm_1: pwm1grp { 1022 fsl,pins = 1023 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ 1024 }; 1025 1026 pinctrl_pwm_2: pwm2grp { 1027 fsl,pins = 1028 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ 1029 }; 1030 1031 pinctrl_pwm_3: pwm3grp { 1032 fsl,pins = 1033 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ 1034 }; 1035 1036 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ 1037 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { 1038 fsl,pins = 1039 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x184>; /* SODIMM 19 */ 1040 }; 1041 1042 pinctrl_reg_eth: regethgrp { 1043 fsl,pins = 1044 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184>; /* PMIC_EN_ETH */ 1045 }; 1046 1047 pinctrl_reg_usb1_en: regusb1engrp { 1048 fsl,pins = 1049 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184>; /* SODIMM 155 */ 1050 }; 1051 1052 pinctrl_reg_usb2_en: regusb2engrp { 1053 fsl,pins = 1054 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184>; /* SODIMM 185 */ 1055 }; 1056 1057 pinctrl_sai2: sai2grp { 1058 fsl,pins = 1059 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6>, /* SODIMM 32 */ 1060 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6>, /* SODIMM 30 */ 1061 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6>, /* SODIMM 38 */ 1062 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6>, /* SODIMM 36 */ 1063 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6>; /* SODIMM 34 */ 1064 }; 1065 1066 pinctrl_sai5: sai5grp { 1067 fsl,pins = 1068 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6>, /* SODIMM 48 */ 1069 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6>, /* SODIMM 44 */ 1070 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6>, /* SODIMM 42 */ 1071 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6>; /* SODIMM 46 */ 1072 }; 1073 1074 /* control signal for optional ATTPM20P or SE050 */ 1075 pinctrl_pmic_tpm_ena: pmictpmenagrp { 1076 fsl,pins = 1077 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1c4>; /* PMIC_TPM_ENA */ 1078 }; 1079 1080 pinctrl_tsp: tspgrp { 1081 fsl,pins = 1082 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140>, /* SODIMM 148 */ 1083 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140>, /* SODIMM 152 */ 1084 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x140>, /* SODIMM 154 */ 1085 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140>, /* SODIMM 174 */ 1086 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140>; /* SODIMM 150 */ 1087 }; 1088 1089 pinctrl_uart1: uart1grp { 1090 fsl,pins = 1091 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4>, /* SODIMM 149 */ 1092 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4>; /* SODIMM 147 */ 1093 }; 1094 1095 pinctrl_uart2: uart2grp { 1096 fsl,pins = 1097 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1c4>, /* SODIMM 129 */ 1098 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1c4>, /* SODIMM 131 */ 1099 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4>, /* SODIMM 133 */ 1100 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4>; /* SODIMM 135 */ 1101 }; 1102 1103 pinctrl_uart3: uart3grp { 1104 fsl,pins = 1105 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4>, /* SODIMM 137 */ 1106 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4>, /* SODIMM 139 */ 1107 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4>, /* SODIMM 141 */ 1108 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4>; /* SODIMM 143 */ 1109 }; 1110 1111 pinctrl_uart4: uart4grp { 1112 fsl,pins = 1113 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4>, /* SODIMM 151 */ 1114 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4>; /* SODIMM 153 */ 1115 }; 1116 1117 pinctrl_usdhc1: usdhc1grp { 1118 fsl,pins = 1119 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, 1120 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, 1121 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, 1122 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, 1123 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, 1124 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, 1125 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, 1126 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, 1127 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, 1128 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, 1129 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1130 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; 1131 }; 1132 1133 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1134 fsl,pins = 1135 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, 1136 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, 1137 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, 1138 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, 1139 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, 1140 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, 1141 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, 1142 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, 1143 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, 1144 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, 1145 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1146 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; 1147 }; 1148 1149 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1150 fsl,pins = 1151 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, 1152 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, 1153 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, 1154 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, 1155 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, 1156 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, 1157 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, 1158 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, 1159 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, 1160 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, 1161 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1162 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; 1163 }; 1164 1165 pinctrl_usdhc2_cd: usdhc2cdgrp { 1166 fsl,pins = 1167 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4>; /* SODIMM 84 */ 1168 }; 1169 1170 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1171 fsl,pins = 1172 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184>; /* SODIMM 76 */ 1173 }; 1174 1175 pinctrl_usdhc2: usdhc2grp { 1176 fsl,pins = 1177 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190>, /* SODIMM 78 */ 1178 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0>, /* SODIMM 74 */ 1179 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0>, /* SODIMM 80 */ 1180 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0>, /* SODIMM 82 */ 1181 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0>, /* SODIMM 70 */ 1182 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0>, /* SODIMM 72 */ 1183 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0>; 1184 }; 1185 1186 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1187 fsl,pins = 1188 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194>, 1189 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>, 1190 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, 1191 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, 1192 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, 1193 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, 1194 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0>; 1195 }; 1196 1197 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1198 fsl,pins = 1199 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196>, 1200 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6>, 1201 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6>, 1202 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6>, 1203 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6>, 1204 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6>, 1205 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0>; 1206 }; 1207 1208 /* On-module Wi-Fi/BT or type specific SDHC interface */ 1209 /* (e.g. on X52 extension slot of Verdin Development Board) */ 1210 pinctrl_usdhc3: usdhc3grp { 1211 fsl,pins = 1212 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190>, 1213 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0>, 1214 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0>, 1215 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0>, 1216 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0>, 1217 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0>; 1218 }; 1219 1220 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1221 fsl,pins = 1222 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194>, 1223 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4>, 1224 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 1225 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 1226 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 1227 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>; 1228 }; 1229 1230 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1231 fsl,pins = 1232 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196>, 1233 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6>, 1234 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6>, 1235 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6>, 1236 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6>, 1237 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6>; 1238 }; 1239 1240 pinctrl_wdog: wdoggrp { 1241 fsl,pins = 1242 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */ 1243 }; 1244 1245 pinctrl_wifi_ctrl: wifictrlgrp { 1246 fsl,pins = 1247 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4>, /* WIFI_WKUP_BT */ 1248 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4>, /* WIFI_W_WKUP_HOST */ 1249 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4>; /* WIFI_WKUP_WLAN */ 1250 }; 1251 1252 pinctrl_wifi_i2s: bti2sgrp { 1253 fsl,pins = 1254 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0xd6>, /* WIFI_TX_BCLK */ 1255 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6>, /* WIFI_TX_DATA0 */ 1256 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0xd6>, /* WIFI_TX_SYNC */ 1257 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6>; /* WIFI_RX_DATA0 */ 1258 }; 1259 1260 pinctrl_wifi_pwr_en: wifipwrengrp { 1261 fsl,pins = 1262 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184>; /* PMIC_EN_WIFI */ 1263 }; 1264}; 1265