16a57f224SMarcel Ziswiler// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 26a57f224SMarcel Ziswiler/* 36a57f224SMarcel Ziswiler * Copyright 2022 Toradex 46a57f224SMarcel Ziswiler */ 56a57f224SMarcel Ziswiler 66a57f224SMarcel Ziswiler#include "dt-bindings/phy/phy-imx8-pcie.h" 76a57f224SMarcel Ziswiler#include "dt-bindings/pwm/pwm.h" 86a57f224SMarcel Ziswiler#include "imx8mm.dtsi" 96a57f224SMarcel Ziswiler 106a57f224SMarcel Ziswiler/ { 116a57f224SMarcel Ziswiler chosen { 126a57f224SMarcel Ziswiler stdout-path = &uart1; 136a57f224SMarcel Ziswiler }; 146a57f224SMarcel Ziswiler 156a57f224SMarcel Ziswiler aliases { 166a57f224SMarcel Ziswiler rtc0 = &rtc_i2c; 176a57f224SMarcel Ziswiler rtc1 = &snvs_rtc; 186a57f224SMarcel Ziswiler }; 196a57f224SMarcel Ziswiler 206a57f224SMarcel Ziswiler backlight: backlight { 216a57f224SMarcel Ziswiler compatible = "pwm-backlight"; 226a57f224SMarcel Ziswiler brightness-levels = <0 45 63 88 119 158 203 255>; 236a57f224SMarcel Ziswiler default-brightness-level = <4>; 246a57f224SMarcel Ziswiler /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 256a57f224SMarcel Ziswiler enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 266a57f224SMarcel Ziswiler pinctrl-names = "default"; 276a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 286a57f224SMarcel Ziswiler power-supply = <®_3p3v>; 296a57f224SMarcel Ziswiler /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 306a57f224SMarcel Ziswiler pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; 316a57f224SMarcel Ziswiler status = "disabled"; 326a57f224SMarcel Ziswiler }; 336a57f224SMarcel Ziswiler 346a57f224SMarcel Ziswiler /* Fixed clock dedicated to SPI CAN controller */ 356a57f224SMarcel Ziswiler clk20m: oscillator { 366a57f224SMarcel Ziswiler compatible = "fixed-clock"; 376a57f224SMarcel Ziswiler #clock-cells = <0>; 386a57f224SMarcel Ziswiler clock-frequency = <20000000>; 396a57f224SMarcel Ziswiler }; 406a57f224SMarcel Ziswiler 416a57f224SMarcel Ziswiler gpio-keys { 426a57f224SMarcel Ziswiler compatible = "gpio-keys"; 436a57f224SMarcel Ziswiler pinctrl-names = "default"; 446a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_gpio_keys>; 456a57f224SMarcel Ziswiler 46b803d15eSKrzysztof Kozlowski key-wakeup { 476a57f224SMarcel Ziswiler debounce-interval = <10>; 486a57f224SMarcel Ziswiler /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 496a57f224SMarcel Ziswiler gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 506a57f224SMarcel Ziswiler label = "Wake-Up"; 516a57f224SMarcel Ziswiler linux,code = <KEY_WAKEUP>; 526a57f224SMarcel Ziswiler wakeup-source; 536a57f224SMarcel Ziswiler }; 546a57f224SMarcel Ziswiler }; 556a57f224SMarcel Ziswiler 56*ac2ac9ffSMarcel Ziswiler panel_lvds: panel-lvds { 57*ac2ac9ffSMarcel Ziswiler compatible = "panel-lvds"; 58*ac2ac9ffSMarcel Ziswiler backlight = <&backlight>; 59*ac2ac9ffSMarcel Ziswiler data-mapping = "vesa-24"; 60*ac2ac9ffSMarcel Ziswiler status = "disabled"; 61*ac2ac9ffSMarcel Ziswiler }; 62*ac2ac9ffSMarcel Ziswiler 636a57f224SMarcel Ziswiler /* Carrier Board Supplies */ 646a57f224SMarcel Ziswiler reg_1p8v: regulator-1p8v { 656a57f224SMarcel Ziswiler compatible = "regulator-fixed"; 666a57f224SMarcel Ziswiler regulator-max-microvolt = <1800000>; 676a57f224SMarcel Ziswiler regulator-min-microvolt = <1800000>; 686a57f224SMarcel Ziswiler regulator-name = "+V1.8_SW"; 696a57f224SMarcel Ziswiler }; 706a57f224SMarcel Ziswiler 716a57f224SMarcel Ziswiler reg_3p3v: regulator-3p3v { 726a57f224SMarcel Ziswiler compatible = "regulator-fixed"; 736a57f224SMarcel Ziswiler regulator-max-microvolt = <3300000>; 746a57f224SMarcel Ziswiler regulator-min-microvolt = <3300000>; 756a57f224SMarcel Ziswiler regulator-name = "+V3.3_SW"; 766a57f224SMarcel Ziswiler }; 776a57f224SMarcel Ziswiler 786a57f224SMarcel Ziswiler reg_5p0v: regulator-5p0v { 796a57f224SMarcel Ziswiler compatible = "regulator-fixed"; 806a57f224SMarcel Ziswiler regulator-max-microvolt = <5000000>; 816a57f224SMarcel Ziswiler regulator-min-microvolt = <5000000>; 826a57f224SMarcel Ziswiler regulator-name = "+V5_SW"; 836a57f224SMarcel Ziswiler }; 846a57f224SMarcel Ziswiler 856a57f224SMarcel Ziswiler /* Non PMIC On-module Supplies */ 866a57f224SMarcel Ziswiler reg_ethphy: regulator-ethphy { 876a57f224SMarcel Ziswiler compatible = "regulator-fixed"; 886a57f224SMarcel Ziswiler enable-active-high; 896a57f224SMarcel Ziswiler gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 906a57f224SMarcel Ziswiler off-on-delay = <500000>; 916a57f224SMarcel Ziswiler pinctrl-names = "default"; 926a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_reg_eth>; 936a57f224SMarcel Ziswiler regulator-boot-on; 946a57f224SMarcel Ziswiler regulator-max-microvolt = <3300000>; 956a57f224SMarcel Ziswiler regulator-min-microvolt = <3300000>; 9697a07703SMarcel Ziswiler regulator-name = "On-module +V3.3_ETH"; 976a57f224SMarcel Ziswiler startup-delay-us = <200000>; 986a57f224SMarcel Ziswiler }; 996a57f224SMarcel Ziswiler 1006a57f224SMarcel Ziswiler reg_usb_otg1_vbus: regulator-usb-otg1 { 1016a57f224SMarcel Ziswiler compatible = "regulator-fixed"; 1026a57f224SMarcel Ziswiler enable-active-high; 1036a57f224SMarcel Ziswiler /* Verdin USB_1_EN (SODIMM 155) */ 1046a57f224SMarcel Ziswiler gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 1056a57f224SMarcel Ziswiler pinctrl-names = "default"; 1066a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_reg_usb1_en>; 1076a57f224SMarcel Ziswiler regulator-max-microvolt = <5000000>; 1086a57f224SMarcel Ziswiler regulator-min-microvolt = <5000000>; 10997a07703SMarcel Ziswiler regulator-name = "USB_1_EN"; 1106a57f224SMarcel Ziswiler }; 1116a57f224SMarcel Ziswiler 1126a57f224SMarcel Ziswiler reg_usb_otg2_vbus: regulator-usb-otg2 { 1136a57f224SMarcel Ziswiler compatible = "regulator-fixed"; 1146a57f224SMarcel Ziswiler enable-active-high; 1156a57f224SMarcel Ziswiler /* Verdin USB_2_EN (SODIMM 185) */ 1166a57f224SMarcel Ziswiler gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 1176a57f224SMarcel Ziswiler pinctrl-names = "default"; 1186a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_reg_usb2_en>; 1196a57f224SMarcel Ziswiler regulator-max-microvolt = <5000000>; 1206a57f224SMarcel Ziswiler regulator-min-microvolt = <5000000>; 12197a07703SMarcel Ziswiler regulator-name = "USB_2_EN"; 1226a57f224SMarcel Ziswiler }; 1236a57f224SMarcel Ziswiler 1246a57f224SMarcel Ziswiler reg_usdhc2_vmmc: regulator-usdhc2 { 1256a57f224SMarcel Ziswiler compatible = "regulator-fixed"; 1266a57f224SMarcel Ziswiler enable-active-high; 1276a57f224SMarcel Ziswiler /* Verdin SD_1_PWR_EN (SODIMM 76) */ 1286a57f224SMarcel Ziswiler gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 1296a57f224SMarcel Ziswiler off-on-delay = <100000>; 1306a57f224SMarcel Ziswiler pinctrl-names = "default"; 1316a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 1326a57f224SMarcel Ziswiler regulator-max-microvolt = <3300000>; 1336a57f224SMarcel Ziswiler regulator-min-microvolt = <3300000>; 1346a57f224SMarcel Ziswiler regulator-name = "+V3.3_SD"; 1356a57f224SMarcel Ziswiler startup-delay-us = <2000>; 1366a57f224SMarcel Ziswiler }; 1376a57f224SMarcel Ziswiler 1386a57f224SMarcel Ziswiler reserved-memory { 1396a57f224SMarcel Ziswiler #address-cells = <2>; 1406a57f224SMarcel Ziswiler #size-cells = <2>; 1416a57f224SMarcel Ziswiler ranges; 1426a57f224SMarcel Ziswiler 1436a57f224SMarcel Ziswiler /* Use the kernel configuration settings instead */ 1446a57f224SMarcel Ziswiler /delete-node/ linux,cma; 1456a57f224SMarcel Ziswiler }; 1466a57f224SMarcel Ziswiler}; 1476a57f224SMarcel Ziswiler 1486a57f224SMarcel Ziswiler&A53_0 { 1496a57f224SMarcel Ziswiler cpu-supply = <®_vdd_arm>; 1506a57f224SMarcel Ziswiler}; 1516a57f224SMarcel Ziswiler 1526a57f224SMarcel Ziswiler&A53_1 { 1536a57f224SMarcel Ziswiler cpu-supply = <®_vdd_arm>; 1546a57f224SMarcel Ziswiler}; 1556a57f224SMarcel Ziswiler 1566a57f224SMarcel Ziswiler&A53_2 { 1576a57f224SMarcel Ziswiler cpu-supply = <®_vdd_arm>; 1586a57f224SMarcel Ziswiler}; 1596a57f224SMarcel Ziswiler 1606a57f224SMarcel Ziswiler&A53_3 { 1616a57f224SMarcel Ziswiler cpu-supply = <®_vdd_arm>; 1626a57f224SMarcel Ziswiler}; 1636a57f224SMarcel Ziswiler 164a242ef5fSPhilippe Schenker&cpu_alert0 { 165a242ef5fSPhilippe Schenker temperature = <95000>; 166a242ef5fSPhilippe Schenker}; 167a242ef5fSPhilippe Schenker 168a242ef5fSPhilippe Schenker&cpu_crit0 { 169a242ef5fSPhilippe Schenker temperature = <105000>; 170a242ef5fSPhilippe Schenker}; 171a242ef5fSPhilippe Schenker 1726a57f224SMarcel Ziswiler&ddrc { 1736a57f224SMarcel Ziswiler operating-points-v2 = <&ddrc_opp_table>; 1746a57f224SMarcel Ziswiler 1756a57f224SMarcel Ziswiler ddrc_opp_table: opp-table { 1766a57f224SMarcel Ziswiler compatible = "operating-points-v2"; 1776a57f224SMarcel Ziswiler 1786a57f224SMarcel Ziswiler opp-25M { 1796a57f224SMarcel Ziswiler opp-hz = /bits/ 64 <25000000>; 1806a57f224SMarcel Ziswiler }; 1816a57f224SMarcel Ziswiler 1826a57f224SMarcel Ziswiler opp-100M { 1836a57f224SMarcel Ziswiler opp-hz = /bits/ 64 <100000000>; 1846a57f224SMarcel Ziswiler }; 1856a57f224SMarcel Ziswiler 1866a57f224SMarcel Ziswiler opp-750M { 1876a57f224SMarcel Ziswiler opp-hz = /bits/ 64 <750000000>; 1886a57f224SMarcel Ziswiler }; 1896a57f224SMarcel Ziswiler }; 1906a57f224SMarcel Ziswiler}; 1916a57f224SMarcel Ziswiler 1926a57f224SMarcel Ziswiler/* Verdin SPI_1 */ 1936a57f224SMarcel Ziswiler&ecspi2 { 1946a57f224SMarcel Ziswiler #address-cells = <1>; 1956a57f224SMarcel Ziswiler #size-cells = <0>; 1966a57f224SMarcel Ziswiler cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 1976a57f224SMarcel Ziswiler pinctrl-names = "default"; 1986a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_ecspi2>; 1996a57f224SMarcel Ziswiler}; 2006a57f224SMarcel Ziswiler 2016a57f224SMarcel Ziswiler/* Verdin CAN_1 (On-module) */ 2026a57f224SMarcel Ziswiler&ecspi3 { 2036a57f224SMarcel Ziswiler #address-cells = <1>; 2046a57f224SMarcel Ziswiler #size-cells = <0>; 2056a57f224SMarcel Ziswiler cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 2066a57f224SMarcel Ziswiler pinctrl-names = "default"; 2076a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_ecspi3>; 2086a57f224SMarcel Ziswiler status = "okay"; 2096a57f224SMarcel Ziswiler 2106a57f224SMarcel Ziswiler can1: can@0 { 2116a57f224SMarcel Ziswiler compatible = "microchip,mcp251xfd"; 2126a57f224SMarcel Ziswiler clocks = <&clk20m>; 2136a57f224SMarcel Ziswiler interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>; 2146a57f224SMarcel Ziswiler pinctrl-names = "default"; 2156a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_can1_int>; 2166a57f224SMarcel Ziswiler reg = <0>; 2176a57f224SMarcel Ziswiler spi-max-frequency = <8500000>; 2186a57f224SMarcel Ziswiler }; 2196a57f224SMarcel Ziswiler}; 2206a57f224SMarcel Ziswiler 2216a57f224SMarcel Ziswiler/* Verdin ETH_1 (On-module PHY) */ 2226a57f224SMarcel Ziswiler&fec1 { 2236a57f224SMarcel Ziswiler fsl,magic-packet; 2246a57f224SMarcel Ziswiler phy-handle = <ðphy0>; 2256a57f224SMarcel Ziswiler phy-mode = "rgmii-id"; 2266a57f224SMarcel Ziswiler phy-supply = <®_ethphy>; 2276a57f224SMarcel Ziswiler pinctrl-names = "default", "sleep"; 2286a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_fec1>; 2296a57f224SMarcel Ziswiler pinctrl-1 = <&pinctrl_fec1_sleep>; 2306a57f224SMarcel Ziswiler 2316a57f224SMarcel Ziswiler mdio { 2326a57f224SMarcel Ziswiler #address-cells = <1>; 2336a57f224SMarcel Ziswiler #size-cells = <0>; 2346a57f224SMarcel Ziswiler 2356a57f224SMarcel Ziswiler ethphy0: ethernet-phy@7 { 2366a57f224SMarcel Ziswiler compatible = "ethernet-phy-ieee802.3-c22"; 2376a57f224SMarcel Ziswiler interrupt-parent = <&gpio1>; 2386a57f224SMarcel Ziswiler interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 2396a57f224SMarcel Ziswiler micrel,led-mode = <0>; 2406a57f224SMarcel Ziswiler reg = <7>; 2416a57f224SMarcel Ziswiler }; 2426a57f224SMarcel Ziswiler }; 2436a57f224SMarcel Ziswiler}; 2446a57f224SMarcel Ziswiler 2456a57f224SMarcel Ziswiler/* Verdin QSPI_1 */ 2466a57f224SMarcel Ziswiler&flexspi { 2476a57f224SMarcel Ziswiler pinctrl-names = "default"; 2486a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_flexspi0>; 2496a57f224SMarcel Ziswiler}; 2506a57f224SMarcel Ziswiler 2516a57f224SMarcel Ziswiler&gpio1 { 2526a57f224SMarcel Ziswiler gpio-line-names = "SODIMM_216", 2536a57f224SMarcel Ziswiler "SODIMM_19", 2546a57f224SMarcel Ziswiler "", 2556a57f224SMarcel Ziswiler "", 2566a57f224SMarcel Ziswiler "", 2576a57f224SMarcel Ziswiler "", 2586a57f224SMarcel Ziswiler "", 2596a57f224SMarcel Ziswiler "", 2606a57f224SMarcel Ziswiler "SODIMM_220", 2616a57f224SMarcel Ziswiler "SODIMM_222", 2626a57f224SMarcel Ziswiler "", 2636a57f224SMarcel Ziswiler "SODIMM_218", 2646a57f224SMarcel Ziswiler "SODIMM_155", 2656a57f224SMarcel Ziswiler "SODIMM_157", 2666a57f224SMarcel Ziswiler "SODIMM_185", 2676a57f224SMarcel Ziswiler "SODIMM_187"; 2686a57f224SMarcel Ziswiler}; 2696a57f224SMarcel Ziswiler 2706a57f224SMarcel Ziswiler&gpio2 { 2716a57f224SMarcel Ziswiler gpio-line-names = "", 2726a57f224SMarcel Ziswiler "", 2736a57f224SMarcel Ziswiler "", 2746a57f224SMarcel Ziswiler "", 2756a57f224SMarcel Ziswiler "", 2766a57f224SMarcel Ziswiler "", 2776a57f224SMarcel Ziswiler "", 2786a57f224SMarcel Ziswiler "", 2796a57f224SMarcel Ziswiler "", 2806a57f224SMarcel Ziswiler "", 2816a57f224SMarcel Ziswiler "", 2826a57f224SMarcel Ziswiler "", 2836a57f224SMarcel Ziswiler "SODIMM_84", 2846a57f224SMarcel Ziswiler "SODIMM_78", 2856a57f224SMarcel Ziswiler "SODIMM_74", 2866a57f224SMarcel Ziswiler "SODIMM_80", 2876a57f224SMarcel Ziswiler "SODIMM_82", 2886a57f224SMarcel Ziswiler "SODIMM_70", 2896a57f224SMarcel Ziswiler "SODIMM_72"; 2906a57f224SMarcel Ziswiler}; 2916a57f224SMarcel Ziswiler 2926a57f224SMarcel Ziswiler&gpio5 { 2936a57f224SMarcel Ziswiler gpio-line-names = "SODIMM_131", 2946a57f224SMarcel Ziswiler "", 2956a57f224SMarcel Ziswiler "SODIMM_91", 2966a57f224SMarcel Ziswiler "SODIMM_16", 2976a57f224SMarcel Ziswiler "SODIMM_15", 2986a57f224SMarcel Ziswiler "SODIMM_208", 2996a57f224SMarcel Ziswiler "SODIMM_137", 3006a57f224SMarcel Ziswiler "SODIMM_139", 3016a57f224SMarcel Ziswiler "SODIMM_141", 3026a57f224SMarcel Ziswiler "SODIMM_143", 3036a57f224SMarcel Ziswiler "SODIMM_196", 3046a57f224SMarcel Ziswiler "SODIMM_200", 3056a57f224SMarcel Ziswiler "SODIMM_198", 3066a57f224SMarcel Ziswiler "SODIMM_202", 3076a57f224SMarcel Ziswiler "", 3086a57f224SMarcel Ziswiler "", 3096a57f224SMarcel Ziswiler "SODIMM_55", 3106a57f224SMarcel Ziswiler "SODIMM_53", 3116a57f224SMarcel Ziswiler "SODIMM_95", 3126a57f224SMarcel Ziswiler "SODIMM_93", 3136a57f224SMarcel Ziswiler "SODIMM_14", 3146a57f224SMarcel Ziswiler "SODIMM_12", 3156a57f224SMarcel Ziswiler "", 3166a57f224SMarcel Ziswiler "", 3176a57f224SMarcel Ziswiler "", 3186a57f224SMarcel Ziswiler "", 3196a57f224SMarcel Ziswiler "SODIMM_210", 3206a57f224SMarcel Ziswiler "SODIMM_212", 3216a57f224SMarcel Ziswiler "SODIMM_151", 3226a57f224SMarcel Ziswiler "SODIMM_153"; 3236a57f224SMarcel Ziswiler 3249847725eSMarcel Ziswiler ctrl-sleep-moci-hog { 3256a57f224SMarcel Ziswiler gpio-hog; 3266a57f224SMarcel Ziswiler /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 3276a57f224SMarcel Ziswiler gpios = <1 GPIO_ACTIVE_HIGH>; 3286a57f224SMarcel Ziswiler line-name = "CTRL_SLEEP_MOCI#"; 3296a57f224SMarcel Ziswiler output-high; 3306a57f224SMarcel Ziswiler pinctrl-names = "default"; 3316a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 3326a57f224SMarcel Ziswiler }; 3336a57f224SMarcel Ziswiler}; 3346a57f224SMarcel Ziswiler 3356a57f224SMarcel Ziswiler/* On-module I2C */ 3366a57f224SMarcel Ziswiler&i2c1 { 3376a57f224SMarcel Ziswiler clock-frequency = <400000>; 3386a57f224SMarcel Ziswiler pinctrl-names = "default", "gpio"; 3396a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_i2c1>; 3406a57f224SMarcel Ziswiler pinctrl-1 = <&pinctrl_i2c1_gpio>; 3416a57f224SMarcel Ziswiler scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 3426a57f224SMarcel Ziswiler sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 3436a57f224SMarcel Ziswiler status = "okay"; 3446a57f224SMarcel Ziswiler 3456a57f224SMarcel Ziswiler pca9450: pmic@25 { 3466a57f224SMarcel Ziswiler compatible = "nxp,pca9450a"; 3476a57f224SMarcel Ziswiler interrupt-parent = <&gpio1>; 3486a57f224SMarcel Ziswiler /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 3496a57f224SMarcel Ziswiler interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 3506a57f224SMarcel Ziswiler pinctrl-names = "default"; 3516a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_pmic>; 3526a57f224SMarcel Ziswiler reg = <0x25>; 3536a57f224SMarcel Ziswiler sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 3546a57f224SMarcel Ziswiler 35579c1c850SMarcel Ziswiler /* 35679c1c850SMarcel Ziswiler * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC 35779c1c850SMarcel Ziswiler * behind this PMIC. 35879c1c850SMarcel Ziswiler */ 35979c1c850SMarcel Ziswiler 3606a57f224SMarcel Ziswiler regulators { 3616a57f224SMarcel Ziswiler reg_vdd_soc: BUCK1 { 3626a57f224SMarcel Ziswiler nxp,dvs-run-voltage = <850000>; 3636a57f224SMarcel Ziswiler nxp,dvs-standby-voltage = <800000>; 3646a57f224SMarcel Ziswiler regulator-always-on; 3656a57f224SMarcel Ziswiler regulator-boot-on; 3666a57f224SMarcel Ziswiler regulator-max-microvolt = <850000>; 3676a57f224SMarcel Ziswiler regulator-min-microvolt = <800000>; 36897a07703SMarcel Ziswiler regulator-name = "On-module +VDD_SOC (BUCK1)"; 3696a57f224SMarcel Ziswiler regulator-ramp-delay = <3125>; 3706a57f224SMarcel Ziswiler }; 3716a57f224SMarcel Ziswiler 3726a57f224SMarcel Ziswiler reg_vdd_arm: BUCK2 { 3736a57f224SMarcel Ziswiler nxp,dvs-run-voltage = <950000>; 3746a57f224SMarcel Ziswiler nxp,dvs-standby-voltage = <850000>; 3756a57f224SMarcel Ziswiler regulator-always-on; 3766a57f224SMarcel Ziswiler regulator-boot-on; 3776a57f224SMarcel Ziswiler regulator-max-microvolt = <950000>; 3786a57f224SMarcel Ziswiler regulator-min-microvolt = <850000>; 37997a07703SMarcel Ziswiler regulator-name = "On-module +VDD_ARM (BUCK2)"; 3806a57f224SMarcel Ziswiler regulator-ramp-delay = <3125>; 3816a57f224SMarcel Ziswiler }; 3826a57f224SMarcel Ziswiler 3836a57f224SMarcel Ziswiler reg_vdd_dram: BUCK3 { 3846a57f224SMarcel Ziswiler regulator-always-on; 3856a57f224SMarcel Ziswiler regulator-boot-on; 3866a57f224SMarcel Ziswiler regulator-max-microvolt = <950000>; 3876a57f224SMarcel Ziswiler regulator-min-microvolt = <850000>; 38897a07703SMarcel Ziswiler regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; 3896a57f224SMarcel Ziswiler }; 3906a57f224SMarcel Ziswiler 3916a57f224SMarcel Ziswiler reg_vdd_3v3: BUCK4 { 3926a57f224SMarcel Ziswiler regulator-always-on; 3936a57f224SMarcel Ziswiler regulator-boot-on; 3946a57f224SMarcel Ziswiler regulator-max-microvolt = <3300000>; 3956a57f224SMarcel Ziswiler regulator-min-microvolt = <3300000>; 39697a07703SMarcel Ziswiler regulator-name = "On-module +V3.3 (BUCK4)"; 3976a57f224SMarcel Ziswiler }; 3986a57f224SMarcel Ziswiler 3996a57f224SMarcel Ziswiler reg_vdd_1v8: BUCK5 { 4006a57f224SMarcel Ziswiler regulator-always-on; 4016a57f224SMarcel Ziswiler regulator-boot-on; 4026a57f224SMarcel Ziswiler regulator-max-microvolt = <1800000>; 4036a57f224SMarcel Ziswiler regulator-min-microvolt = <1800000>; 40497a07703SMarcel Ziswiler regulator-name = "PWR_1V8_MOCI (BUCK5)"; 4056a57f224SMarcel Ziswiler }; 4066a57f224SMarcel Ziswiler 4076a57f224SMarcel Ziswiler reg_nvcc_dram: BUCK6 { 4086a57f224SMarcel Ziswiler regulator-always-on; 4096a57f224SMarcel Ziswiler regulator-boot-on; 4106a57f224SMarcel Ziswiler regulator-max-microvolt = <1100000>; 4116a57f224SMarcel Ziswiler regulator-min-microvolt = <1100000>; 41297a07703SMarcel Ziswiler regulator-name = "On-module +VDD_DDR (BUCK6)"; 4136a57f224SMarcel Ziswiler }; 4146a57f224SMarcel Ziswiler 4156a57f224SMarcel Ziswiler reg_nvcc_snvs: LDO1 { 4166a57f224SMarcel Ziswiler regulator-always-on; 4176a57f224SMarcel Ziswiler regulator-boot-on; 4186a57f224SMarcel Ziswiler regulator-max-microvolt = <1800000>; 4196a57f224SMarcel Ziswiler regulator-min-microvolt = <1800000>; 42097a07703SMarcel Ziswiler regulator-name = "On-module +V1.8_SNVS (LDO1)"; 4216a57f224SMarcel Ziswiler }; 4226a57f224SMarcel Ziswiler 4236a57f224SMarcel Ziswiler reg_vdd_snvs: LDO2 { 4246a57f224SMarcel Ziswiler regulator-always-on; 4256a57f224SMarcel Ziswiler regulator-boot-on; 4266a57f224SMarcel Ziswiler regulator-max-microvolt = <900000>; 4276a57f224SMarcel Ziswiler regulator-min-microvolt = <800000>; 42897a07703SMarcel Ziswiler regulator-name = "On-module +V0.8_SNVS (LDO2)"; 4296a57f224SMarcel Ziswiler }; 4306a57f224SMarcel Ziswiler 4316a57f224SMarcel Ziswiler reg_vdda: LDO3 { 4326a57f224SMarcel Ziswiler regulator-always-on; 4336a57f224SMarcel Ziswiler regulator-boot-on; 4346a57f224SMarcel Ziswiler regulator-max-microvolt = <1800000>; 4356a57f224SMarcel Ziswiler regulator-min-microvolt = <1800000>; 43697a07703SMarcel Ziswiler regulator-name = "On-module +V1.8A (LDO3)"; 4376a57f224SMarcel Ziswiler }; 4386a57f224SMarcel Ziswiler 4396a57f224SMarcel Ziswiler reg_vdd_phy: LDO4 { 4406a57f224SMarcel Ziswiler regulator-always-on; 4416a57f224SMarcel Ziswiler regulator-boot-on; 4426a57f224SMarcel Ziswiler regulator-max-microvolt = <900000>; 4436a57f224SMarcel Ziswiler regulator-min-microvolt = <900000>; 44497a07703SMarcel Ziswiler regulator-name = "On-module +V0.9_MIPI (LDO4)"; 4456a57f224SMarcel Ziswiler }; 4466a57f224SMarcel Ziswiler 4476a57f224SMarcel Ziswiler reg_nvcc_sd: LDO5 { 4486a57f224SMarcel Ziswiler regulator-max-microvolt = <3300000>; 4496a57f224SMarcel Ziswiler regulator-min-microvolt = <1800000>; 45097a07703SMarcel Ziswiler regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 4516a57f224SMarcel Ziswiler }; 4526a57f224SMarcel Ziswiler }; 4536a57f224SMarcel Ziswiler }; 4546a57f224SMarcel Ziswiler 4556a57f224SMarcel Ziswiler rtc_i2c: rtc@32 { 4566a57f224SMarcel Ziswiler compatible = "epson,rx8130"; 4576a57f224SMarcel Ziswiler reg = <0x32>; 4586a57f224SMarcel Ziswiler }; 4596a57f224SMarcel Ziswiler 4606a57f224SMarcel Ziswiler adc@49 { 4616a57f224SMarcel Ziswiler compatible = "ti,ads1015"; 4626a57f224SMarcel Ziswiler reg = <0x49>; 4636a57f224SMarcel Ziswiler #address-cells = <1>; 4646a57f224SMarcel Ziswiler #size-cells = <0>; 4656a57f224SMarcel Ziswiler 4666a57f224SMarcel Ziswiler /* Verdin I2C_1 (ADC_4 - ADC_3) */ 4676a57f224SMarcel Ziswiler channel@0 { 4686a57f224SMarcel Ziswiler reg = <0>; 4696a57f224SMarcel Ziswiler ti,datarate = <4>; 4706a57f224SMarcel Ziswiler ti,gain = <2>; 4716a57f224SMarcel Ziswiler }; 4726a57f224SMarcel Ziswiler 4736a57f224SMarcel Ziswiler /* Verdin I2C_1 (ADC_4 - ADC_1) */ 4746a57f224SMarcel Ziswiler channel@1 { 4756a57f224SMarcel Ziswiler reg = <1>; 4766a57f224SMarcel Ziswiler ti,datarate = <4>; 4776a57f224SMarcel Ziswiler ti,gain = <2>; 4786a57f224SMarcel Ziswiler }; 4796a57f224SMarcel Ziswiler 4806a57f224SMarcel Ziswiler /* Verdin I2C_1 (ADC_3 - ADC_1) */ 4816a57f224SMarcel Ziswiler channel@2 { 4826a57f224SMarcel Ziswiler reg = <2>; 4836a57f224SMarcel Ziswiler ti,datarate = <4>; 4846a57f224SMarcel Ziswiler ti,gain = <2>; 4856a57f224SMarcel Ziswiler }; 4866a57f224SMarcel Ziswiler 4876a57f224SMarcel Ziswiler /* Verdin I2C_1 (ADC_2 - ADC_1) */ 4886a57f224SMarcel Ziswiler channel@3 { 4896a57f224SMarcel Ziswiler reg = <3>; 4906a57f224SMarcel Ziswiler ti,datarate = <4>; 4916a57f224SMarcel Ziswiler ti,gain = <2>; 4926a57f224SMarcel Ziswiler }; 4936a57f224SMarcel Ziswiler 4946a57f224SMarcel Ziswiler /* Verdin I2C_1 ADC_4 */ 4956a57f224SMarcel Ziswiler channel@4 { 4966a57f224SMarcel Ziswiler reg = <4>; 4976a57f224SMarcel Ziswiler ti,datarate = <4>; 4986a57f224SMarcel Ziswiler ti,gain = <2>; 4996a57f224SMarcel Ziswiler }; 5006a57f224SMarcel Ziswiler 5016a57f224SMarcel Ziswiler /* Verdin I2C_1 ADC_3 */ 5026a57f224SMarcel Ziswiler channel@5 { 5036a57f224SMarcel Ziswiler reg = <5>; 5046a57f224SMarcel Ziswiler ti,datarate = <4>; 5056a57f224SMarcel Ziswiler ti,gain = <2>; 5066a57f224SMarcel Ziswiler }; 5076a57f224SMarcel Ziswiler 5086a57f224SMarcel Ziswiler /* Verdin I2C_1 ADC_2 */ 5096a57f224SMarcel Ziswiler channel@6 { 5106a57f224SMarcel Ziswiler reg = <6>; 5116a57f224SMarcel Ziswiler ti,datarate = <4>; 5126a57f224SMarcel Ziswiler ti,gain = <2>; 5136a57f224SMarcel Ziswiler }; 5146a57f224SMarcel Ziswiler 5156a57f224SMarcel Ziswiler /* Verdin I2C_1 ADC_1 */ 5166a57f224SMarcel Ziswiler channel@7 { 5176a57f224SMarcel Ziswiler reg = <7>; 5186a57f224SMarcel Ziswiler ti,datarate = <4>; 5196a57f224SMarcel Ziswiler ti,gain = <2>; 5206a57f224SMarcel Ziswiler }; 5216a57f224SMarcel Ziswiler }; 5226a57f224SMarcel Ziswiler 5236a57f224SMarcel Ziswiler eeprom@50 { 5246a57f224SMarcel Ziswiler compatible = "st,24c02"; 5256a57f224SMarcel Ziswiler pagesize = <16>; 5266a57f224SMarcel Ziswiler reg = <0x50>; 5276a57f224SMarcel Ziswiler }; 5286a57f224SMarcel Ziswiler}; 5296a57f224SMarcel Ziswiler 5306a57f224SMarcel Ziswiler/* Verdin I2C_2_DSI */ 5316a57f224SMarcel Ziswiler&i2c2 { 5326a57f224SMarcel Ziswiler clock-frequency = <10000>; 5336a57f224SMarcel Ziswiler pinctrl-names = "default", "gpio"; 5346a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_i2c2>; 5356a57f224SMarcel Ziswiler pinctrl-1 = <&pinctrl_i2c2_gpio>; 5366a57f224SMarcel Ziswiler scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 5376a57f224SMarcel Ziswiler sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 5386a57f224SMarcel Ziswiler status = "disabled"; 5396a57f224SMarcel Ziswiler}; 5406a57f224SMarcel Ziswiler 5416a57f224SMarcel Ziswiler/* Verdin I2C_3_HDMI N/A */ 5426a57f224SMarcel Ziswiler 5436a57f224SMarcel Ziswiler/* Verdin I2C_4_CSI */ 5446a57f224SMarcel Ziswiler&i2c3 { 5456a57f224SMarcel Ziswiler clock-frequency = <400000>; 5466a57f224SMarcel Ziswiler pinctrl-names = "default", "gpio"; 5476a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_i2c3>; 5486a57f224SMarcel Ziswiler pinctrl-1 = <&pinctrl_i2c3_gpio>; 5496a57f224SMarcel Ziswiler scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 5506a57f224SMarcel Ziswiler sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 5516a57f224SMarcel Ziswiler}; 5526a57f224SMarcel Ziswiler 5536a57f224SMarcel Ziswiler/* Verdin I2C_1 */ 5546a57f224SMarcel Ziswiler&i2c4 { 5556a57f224SMarcel Ziswiler clock-frequency = <400000>; 5566a57f224SMarcel Ziswiler pinctrl-names = "default", "gpio"; 5576a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_i2c4>; 5586a57f224SMarcel Ziswiler pinctrl-1 = <&pinctrl_i2c4_gpio>; 5596a57f224SMarcel Ziswiler scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 5606a57f224SMarcel Ziswiler sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 5616a57f224SMarcel Ziswiler 5626a57f224SMarcel Ziswiler gpio_expander_21: gpio-expander@21 { 5636a57f224SMarcel Ziswiler compatible = "nxp,pcal6416"; 5646a57f224SMarcel Ziswiler #gpio-cells = <2>; 5656a57f224SMarcel Ziswiler gpio-controller; 5666a57f224SMarcel Ziswiler reg = <0x21>; 5676a57f224SMarcel Ziswiler vcc-supply = <®_3p3v>; 5686a57f224SMarcel Ziswiler status = "disabled"; 5696a57f224SMarcel Ziswiler }; 5706a57f224SMarcel Ziswiler 5718728c63cSMarcel Ziswiler lvds_ti_sn65dsi84: bridge@2c { 5728728c63cSMarcel Ziswiler compatible = "ti,sn65dsi84"; 5736a57f224SMarcel Ziswiler /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 5746a57f224SMarcel Ziswiler /* Verdin GPIO_10_DSI (SODIMM 21) */ 5756a57f224SMarcel Ziswiler enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 5766a57f224SMarcel Ziswiler pinctrl-names = "default"; 5776a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_gpio_10_dsi>; 5786a57f224SMarcel Ziswiler reg = <0x2c>; 5796a57f224SMarcel Ziswiler status = "disabled"; 5806a57f224SMarcel Ziswiler }; 5816a57f224SMarcel Ziswiler 5826a57f224SMarcel Ziswiler /* Current measurement into module VCC */ 5836a57f224SMarcel Ziswiler hwmon: hwmon@40 { 5846a57f224SMarcel Ziswiler compatible = "ti,ina219"; 5856a57f224SMarcel Ziswiler reg = <0x40>; 5866a57f224SMarcel Ziswiler shunt-resistor = <10000>; 5876a57f224SMarcel Ziswiler status = "disabled"; 5886a57f224SMarcel Ziswiler }; 5896a57f224SMarcel Ziswiler 5906a57f224SMarcel Ziswiler hdmi_lontium_lt8912: hdmi@48 { 5916a57f224SMarcel Ziswiler compatible = "lontium,lt8912b"; 5926a57f224SMarcel Ziswiler pinctrl-names = "default"; 5936a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; 5946a57f224SMarcel Ziswiler reg = <0x48>; 5956a57f224SMarcel Ziswiler /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 5966a57f224SMarcel Ziswiler /* Verdin GPIO_10_DSI (SODIMM 21) */ 5976a57f224SMarcel Ziswiler reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; 5986a57f224SMarcel Ziswiler status = "disabled"; 5996a57f224SMarcel Ziswiler }; 6006a57f224SMarcel Ziswiler 6016a57f224SMarcel Ziswiler atmel_mxt_ts: touch@4a { 6026a57f224SMarcel Ziswiler compatible = "atmel,maxtouch"; 60398e4f193SMarcel Ziswiler /* 60498e4f193SMarcel Ziswiler * Verdin GPIO_9_DSI 60598e4f193SMarcel Ziswiler * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) 60698e4f193SMarcel Ziswiler */ 6076a57f224SMarcel Ziswiler interrupt-parent = <&gpio3>; 6086a57f224SMarcel Ziswiler interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 6096a57f224SMarcel Ziswiler pinctrl-names = "default"; 6106a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 6116a57f224SMarcel Ziswiler reg = <0x4a>; 6126a57f224SMarcel Ziswiler /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 6136a57f224SMarcel Ziswiler reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; 6146a57f224SMarcel Ziswiler status = "disabled"; 6156a57f224SMarcel Ziswiler }; 6166a57f224SMarcel Ziswiler 6176a57f224SMarcel Ziswiler /* Temperature sensor on carrier board */ 6186a57f224SMarcel Ziswiler hwmon_temp: sensor@4f { 6196a57f224SMarcel Ziswiler compatible = "ti,tmp75c"; 6206a57f224SMarcel Ziswiler reg = <0x4f>; 6216a57f224SMarcel Ziswiler status = "disabled"; 6226a57f224SMarcel Ziswiler }; 6236a57f224SMarcel Ziswiler 6246a57f224SMarcel Ziswiler /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 6256a57f224SMarcel Ziswiler eeprom_display_adapter: eeprom@50 { 6266a57f224SMarcel Ziswiler compatible = "st,24c02"; 6276a57f224SMarcel Ziswiler pagesize = <16>; 6286a57f224SMarcel Ziswiler reg = <0x50>; 6296a57f224SMarcel Ziswiler status = "disabled"; 6306a57f224SMarcel Ziswiler }; 6316a57f224SMarcel Ziswiler 6326a57f224SMarcel Ziswiler /* EEPROM on carrier board */ 6336a57f224SMarcel Ziswiler eeprom_carrier_board: eeprom@57 { 6346a57f224SMarcel Ziswiler compatible = "st,24c02"; 6356a57f224SMarcel Ziswiler pagesize = <16>; 6366a57f224SMarcel Ziswiler reg = <0x57>; 6376a57f224SMarcel Ziswiler status = "disabled"; 6386a57f224SMarcel Ziswiler }; 6396a57f224SMarcel Ziswiler}; 6406a57f224SMarcel Ziswiler 6416a57f224SMarcel Ziswiler/* Verdin PCIE_1 */ 6426a57f224SMarcel Ziswiler&pcie0 { 6436a57f224SMarcel Ziswiler assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 6446a57f224SMarcel Ziswiler <&clk IMX8MM_CLK_PCIE1_CTRL>; 6456a57f224SMarcel Ziswiler assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 6466a57f224SMarcel Ziswiler <&clk IMX8MM_SYS_PLL2_250M>; 6476a57f224SMarcel Ziswiler assigned-clock-rates = <10000000>, <250000000>; 6486a57f224SMarcel Ziswiler clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, 6496a57f224SMarcel Ziswiler <&clk IMX8MM_CLK_PCIE1_PHY>; 6506a57f224SMarcel Ziswiler clock-names = "pcie", "pcie_aux", "pcie_bus"; 6516a57f224SMarcel Ziswiler pinctrl-names = "default"; 6526a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_pcie0>; 6536a57f224SMarcel Ziswiler /* PCIE_1_RESET# (SODIMM 244) */ 6546a57f224SMarcel Ziswiler reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 6556a57f224SMarcel Ziswiler}; 6566a57f224SMarcel Ziswiler 6576a57f224SMarcel Ziswiler&pcie_phy { 6586a57f224SMarcel Ziswiler clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 6596a57f224SMarcel Ziswiler fsl,clkreq-unsupported; 6606a57f224SMarcel Ziswiler fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 6616a57f224SMarcel Ziswiler fsl,tx-deemph-gen1 = <0x2d>; 6626a57f224SMarcel Ziswiler fsl,tx-deemph-gen2 = <0xf>; 6636a57f224SMarcel Ziswiler}; 6646a57f224SMarcel Ziswiler 6656a57f224SMarcel Ziswiler/* Verdin PWM_3_DSI */ 6666a57f224SMarcel Ziswiler&pwm1 { 6676a57f224SMarcel Ziswiler pinctrl-names = "default"; 6686a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_pwm_1>; 6696a57f224SMarcel Ziswiler #pwm-cells = <3>; 6706a57f224SMarcel Ziswiler}; 6716a57f224SMarcel Ziswiler 6726a57f224SMarcel Ziswiler/* Verdin PWM_1 */ 6736a57f224SMarcel Ziswiler&pwm2 { 6746a57f224SMarcel Ziswiler pinctrl-names = "default"; 6756a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_pwm_2>; 6766a57f224SMarcel Ziswiler #pwm-cells = <3>; 6776a57f224SMarcel Ziswiler}; 6786a57f224SMarcel Ziswiler 6796a57f224SMarcel Ziswiler/* Verdin PWM_2 */ 6806a57f224SMarcel Ziswiler&pwm3 { 6816a57f224SMarcel Ziswiler pinctrl-names = "default"; 6826a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_pwm_3>; 6836a57f224SMarcel Ziswiler #pwm-cells = <3>; 6846a57f224SMarcel Ziswiler}; 6856a57f224SMarcel Ziswiler 686473b34b8SMarcel Ziswiler/* Verdin I2S_1 */ 6876a57f224SMarcel Ziswiler&sai2 { 6886a57f224SMarcel Ziswiler #sound-dai-cells = <0>; 6896a57f224SMarcel Ziswiler assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 6906a57f224SMarcel Ziswiler assigned-clock-rates = <24576000>; 6916a57f224SMarcel Ziswiler assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 6926a57f224SMarcel Ziswiler pinctrl-names = "default"; 6936a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_sai2>; 6946a57f224SMarcel Ziswiler}; 6956a57f224SMarcel Ziswiler 6966a57f224SMarcel Ziswiler&snvs_pwrkey { 6976a57f224SMarcel Ziswiler status = "okay"; 6986a57f224SMarcel Ziswiler}; 6996a57f224SMarcel Ziswiler 7006a57f224SMarcel Ziswiler/* Verdin UART_3, used as the Linux console */ 7016a57f224SMarcel Ziswiler&uart1 { 7026a57f224SMarcel Ziswiler pinctrl-names = "default"; 7036a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_uart1>; 7046a57f224SMarcel Ziswiler}; 7056a57f224SMarcel Ziswiler 7066a57f224SMarcel Ziswiler/* Verdin UART_1 */ 7076a57f224SMarcel Ziswiler&uart2 { 7086a57f224SMarcel Ziswiler pinctrl-names = "default"; 7096a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_uart2>; 7106a57f224SMarcel Ziswiler uart-has-rtscts; 7116a57f224SMarcel Ziswiler}; 7126a57f224SMarcel Ziswiler 7136a57f224SMarcel Ziswiler/* Verdin UART_2 */ 7146a57f224SMarcel Ziswiler&uart3 { 7156a57f224SMarcel Ziswiler pinctrl-names = "default"; 7166a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_uart3>; 7176a57f224SMarcel Ziswiler uart-has-rtscts; 7186a57f224SMarcel Ziswiler}; 7196a57f224SMarcel Ziswiler 7206a57f224SMarcel Ziswiler/* 72198e4f193SMarcel Ziswiler * Verdin UART_4 7226a57f224SMarcel Ziswiler * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS 7236a57f224SMarcel Ziswiler */ 7246a57f224SMarcel Ziswiler&uart4 { 7256a57f224SMarcel Ziswiler pinctrl-names = "default"; 7266a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_uart4>; 7276a57f224SMarcel Ziswiler}; 7286a57f224SMarcel Ziswiler 7296a57f224SMarcel Ziswiler/* Verdin USB_1 */ 7306a57f224SMarcel Ziswiler&usbotg1 { 7316a57f224SMarcel Ziswiler adp-disable; 7326a57f224SMarcel Ziswiler dr_mode = "otg"; 7336a57f224SMarcel Ziswiler hnp-disable; 7346a57f224SMarcel Ziswiler over-current-active-low; 7356a57f224SMarcel Ziswiler samsung,picophy-dc-vol-level-adjust = <7>; 7366a57f224SMarcel Ziswiler samsung,picophy-pre-emp-curr-control = <3>; 7376a57f224SMarcel Ziswiler srp-disable; 7386a57f224SMarcel Ziswiler vbus-supply = <®_usb_otg1_vbus>; 7396a57f224SMarcel Ziswiler}; 7406a57f224SMarcel Ziswiler 7416a57f224SMarcel Ziswiler/* Verdin USB_2 */ 7426a57f224SMarcel Ziswiler&usbotg2 { 7436a57f224SMarcel Ziswiler dr_mode = "host"; 7446a57f224SMarcel Ziswiler over-current-active-low; 7456a57f224SMarcel Ziswiler samsung,picophy-dc-vol-level-adjust = <7>; 7466a57f224SMarcel Ziswiler samsung,picophy-pre-emp-curr-control = <3>; 7476a57f224SMarcel Ziswiler vbus-supply = <®_usb_otg2_vbus>; 7486a57f224SMarcel Ziswiler}; 7496a57f224SMarcel Ziswiler 7506a57f224SMarcel Ziswiler&usbphynop1 { 7516a57f224SMarcel Ziswiler vcc-supply = <®_vdd_3v3>; 7526a57f224SMarcel Ziswiler}; 7536a57f224SMarcel Ziswiler 7546a57f224SMarcel Ziswiler&usbphynop2 { 7556a57f224SMarcel Ziswiler vcc-supply = <®_vdd_3v3>; 7566a57f224SMarcel Ziswiler}; 7576a57f224SMarcel Ziswiler 7586a57f224SMarcel Ziswiler/* On-module eMMC */ 7596a57f224SMarcel Ziswiler&usdhc1 { 7606a57f224SMarcel Ziswiler bus-width = <8>; 7616a57f224SMarcel Ziswiler keep-power-in-suspend; 7626a57f224SMarcel Ziswiler non-removable; 7636a57f224SMarcel Ziswiler pinctrl-names = "default", "state_100mhz", "state_200mhz"; 7646a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_usdhc1>; 7656a57f224SMarcel Ziswiler pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 7666a57f224SMarcel Ziswiler pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 7676a57f224SMarcel Ziswiler status = "okay"; 7686a57f224SMarcel Ziswiler}; 7696a57f224SMarcel Ziswiler 7706a57f224SMarcel Ziswiler/* Verdin SD_1 */ 7716a57f224SMarcel Ziswiler&usdhc2 { 7726a57f224SMarcel Ziswiler bus-width = <4>; 7736a57f224SMarcel Ziswiler cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 7746a57f224SMarcel Ziswiler disable-wp; 7754f6b5de9SMarcel Ziswiler pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 7766a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 7776a57f224SMarcel Ziswiler pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 7786a57f224SMarcel Ziswiler pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 7794f6b5de9SMarcel Ziswiler pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 7806a57f224SMarcel Ziswiler vmmc-supply = <®_usdhc2_vmmc>; 7816a57f224SMarcel Ziswiler}; 7826a57f224SMarcel Ziswiler 7836a57f224SMarcel Ziswiler&wdog1 { 7846a57f224SMarcel Ziswiler fsl,ext-reset-output; 7856a57f224SMarcel Ziswiler pinctrl-names = "default"; 7866a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_wdog>; 7876a57f224SMarcel Ziswiler status = "okay"; 7886a57f224SMarcel Ziswiler}; 7896a57f224SMarcel Ziswiler 7906a57f224SMarcel Ziswiler&iomuxc { 7916a57f224SMarcel Ziswiler pinctrl-names = "default"; 7926a57f224SMarcel Ziswiler pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 7936a57f224SMarcel Ziswiler <&pinctrl_gpio3>, <&pinctrl_gpio4>, 7946a57f224SMarcel Ziswiler <&pinctrl_gpio7>, <&pinctrl_gpio8>, 7956a57f224SMarcel Ziswiler <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, 7966a57f224SMarcel Ziswiler <&pinctrl_pmic_tpm_ena>; 7976a57f224SMarcel Ziswiler 7986a57f224SMarcel Ziswiler pinctrl_can1_int: can1intgrp { 7996a57f224SMarcel Ziswiler fsl,pins = 80060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */ 8016a57f224SMarcel Ziswiler }; 8026a57f224SMarcel Ziswiler 8036a57f224SMarcel Ziswiler pinctrl_can2_int: can2intgrp { 8046a57f224SMarcel Ziswiler fsl,pins = 80560f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */ 8066a57f224SMarcel Ziswiler }; 8076a57f224SMarcel Ziswiler 8086a57f224SMarcel Ziswiler pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 8096a57f224SMarcel Ziswiler fsl,pins = 81060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */ 8116a57f224SMarcel Ziswiler }; 8126a57f224SMarcel Ziswiler 8136a57f224SMarcel Ziswiler pinctrl_ecspi2: ecspi2grp { 8146a57f224SMarcel Ziswiler fsl,pins = 81560f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ 816593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */ 817593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */ 81860f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ 8196a57f224SMarcel Ziswiler }; 8206a57f224SMarcel Ziswiler 8216a57f224SMarcel Ziswiler pinctrl_ecspi3: ecspi3grp { 8226a57f224SMarcel Ziswiler fsl,pins = 823593c535bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */ 82460f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ 82560f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ 82660f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ 827593c535bSMarcel Ziswiler <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */ 8286a57f224SMarcel Ziswiler }; 8296a57f224SMarcel Ziswiler 8306a57f224SMarcel Ziswiler pinctrl_fec1: fec1grp { 8316a57f224SMarcel Ziswiler fsl,pins = 8326a57f224SMarcel Ziswiler <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 8336a57f224SMarcel Ziswiler <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 8346a57f224SMarcel Ziswiler <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 835593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 836593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 837593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 8386a57f224SMarcel Ziswiler <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 8396a57f224SMarcel Ziswiler <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 840593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, 841593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, 842593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, 843593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, 844593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, 8456a57f224SMarcel Ziswiler <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, 84660f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; 8476a57f224SMarcel Ziswiler }; 8486a57f224SMarcel Ziswiler 8496a57f224SMarcel Ziswiler pinctrl_fec1_sleep: fec1-sleepgrp { 8506a57f224SMarcel Ziswiler fsl,pins = 8516a57f224SMarcel Ziswiler <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 8526a57f224SMarcel Ziswiler <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 8536a57f224SMarcel Ziswiler <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 854593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 855593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 856593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 8576a57f224SMarcel Ziswiler <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 8586a57f224SMarcel Ziswiler <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 859593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, 860593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, 861593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, 862593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, 863593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, 8646a57f224SMarcel Ziswiler <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, 86560f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; 8666a57f224SMarcel Ziswiler }; 8676a57f224SMarcel Ziswiler 8686a57f224SMarcel Ziswiler pinctrl_flexspi0: flexspi0grp { 8696a57f224SMarcel Ziswiler fsl,pins = 87060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ 87160f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ 87260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ 87360f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ 87460f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ 87560f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ 876593c535bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */ 877593c535bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */ 8786a57f224SMarcel Ziswiler }; 8796a57f224SMarcel Ziswiler 8806a57f224SMarcel Ziswiler pinctrl_gpio1: gpio1grp { 8816a57f224SMarcel Ziswiler fsl,pins = 88260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */ 8836a57f224SMarcel Ziswiler }; 8846a57f224SMarcel Ziswiler 8856a57f224SMarcel Ziswiler pinctrl_gpio2: gpio2grp { 8866a57f224SMarcel Ziswiler fsl,pins = 88760f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */ 8886a57f224SMarcel Ziswiler }; 8896a57f224SMarcel Ziswiler 8906a57f224SMarcel Ziswiler pinctrl_gpio3: gpio3grp { 8916a57f224SMarcel Ziswiler fsl,pins = 89260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */ 8936a57f224SMarcel Ziswiler }; 8946a57f224SMarcel Ziswiler 8956a57f224SMarcel Ziswiler pinctrl_gpio4: gpio4grp { 8966a57f224SMarcel Ziswiler fsl,pins = 89760f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */ 8986a57f224SMarcel Ziswiler }; 8996a57f224SMarcel Ziswiler 9006a57f224SMarcel Ziswiler pinctrl_gpio5: gpio5grp { 9016a57f224SMarcel Ziswiler fsl,pins = 90260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */ 9036a57f224SMarcel Ziswiler }; 9046a57f224SMarcel Ziswiler 9056a57f224SMarcel Ziswiler pinctrl_gpio6: gpio6grp { 9066a57f224SMarcel Ziswiler fsl,pins = 90760f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */ 9086a57f224SMarcel Ziswiler }; 9096a57f224SMarcel Ziswiler 9106a57f224SMarcel Ziswiler pinctrl_gpio7: gpio7grp { 9116a57f224SMarcel Ziswiler fsl,pins = 91260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */ 9136a57f224SMarcel Ziswiler }; 9146a57f224SMarcel Ziswiler 9156a57f224SMarcel Ziswiler pinctrl_gpio8: gpio8grp { 9166a57f224SMarcel Ziswiler fsl,pins = 91760f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */ 9186a57f224SMarcel Ziswiler }; 9196a57f224SMarcel Ziswiler 9206a57f224SMarcel Ziswiler /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 9216a57f224SMarcel Ziswiler pinctrl_gpio_9_dsi: gpio9dsigrp { 9226a57f224SMarcel Ziswiler fsl,pins = 92360f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */ 9246a57f224SMarcel Ziswiler }; 9256a57f224SMarcel Ziswiler 92660f01b5bSMarcel Ziswiler /* Verdin GPIO_10_DSI (pulled-up as active-low) */ 9276a57f224SMarcel Ziswiler pinctrl_gpio_10_dsi: gpio10dsigrp { 9286a57f224SMarcel Ziswiler fsl,pins = 92960f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */ 9306a57f224SMarcel Ziswiler }; 9316a57f224SMarcel Ziswiler 9326a57f224SMarcel Ziswiler pinctrl_gpio_hog1: gpiohog1grp { 9336a57f224SMarcel Ziswiler fsl,pins = 93460f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */ 93560f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */ 93660f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */ 93760f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */ 93860f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */ 93960f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */ 94060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */ 94160f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */ 94260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */ 94360f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */ 94460f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */ 94560f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */ 94660f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */ 94760f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */ 94860f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */ 9496a57f224SMarcel Ziswiler }; 9506a57f224SMarcel Ziswiler 9516a57f224SMarcel Ziswiler pinctrl_gpio_hog2: gpiohog2grp { 9526a57f224SMarcel Ziswiler fsl,pins = 95360f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */ 9546a57f224SMarcel Ziswiler }; 9556a57f224SMarcel Ziswiler 9566a57f224SMarcel Ziswiler pinctrl_gpio_hog3: gpiohog3grp { 9576a57f224SMarcel Ziswiler fsl,pins = 95860f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */ 95960f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */ 9606a57f224SMarcel Ziswiler }; 9616a57f224SMarcel Ziswiler 9626a57f224SMarcel Ziswiler pinctrl_gpio_keys: gpiokeysgrp { 9636a57f224SMarcel Ziswiler fsl,pins = 96460f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */ 9656a57f224SMarcel Ziswiler }; 9666a57f224SMarcel Ziswiler 9676a57f224SMarcel Ziswiler /* On-module I2C */ 9686a57f224SMarcel Ziswiler pinctrl_i2c1: i2c1grp { 9696a57f224SMarcel Ziswiler fsl,pins = 97060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */ 97160f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */ 9726a57f224SMarcel Ziswiler }; 9736a57f224SMarcel Ziswiler 9746a57f224SMarcel Ziswiler pinctrl_i2c1_gpio: i2c1gpiogrp { 9756a57f224SMarcel Ziswiler fsl,pins = 97660f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */ 97760f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */ 9786a57f224SMarcel Ziswiler }; 9796a57f224SMarcel Ziswiler 9806a57f224SMarcel Ziswiler /* Verdin I2C_4_CSI */ 9816a57f224SMarcel Ziswiler pinctrl_i2c2: i2c2grp { 9826a57f224SMarcel Ziswiler fsl,pins = 98360f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */ 98460f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */ 9856a57f224SMarcel Ziswiler }; 9866a57f224SMarcel Ziswiler 9876a57f224SMarcel Ziswiler pinctrl_i2c2_gpio: i2c2gpiogrp { 9886a57f224SMarcel Ziswiler fsl,pins = 98960f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */ 99060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */ 9916a57f224SMarcel Ziswiler }; 9926a57f224SMarcel Ziswiler 9936a57f224SMarcel Ziswiler /* Verdin I2C_2_DSI */ 9946a57f224SMarcel Ziswiler pinctrl_i2c3: i2c3grp { 9956a57f224SMarcel Ziswiler fsl,pins = 99660f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */ 99760f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */ 9986a57f224SMarcel Ziswiler }; 9996a57f224SMarcel Ziswiler 10006a57f224SMarcel Ziswiler pinctrl_i2c3_gpio: i2c3gpiogrp { 10016a57f224SMarcel Ziswiler fsl,pins = 100260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */ 100360f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */ 10046a57f224SMarcel Ziswiler }; 10056a57f224SMarcel Ziswiler 10066a57f224SMarcel Ziswiler /* Verdin I2C_1 */ 10076a57f224SMarcel Ziswiler pinctrl_i2c4: i2c4grp { 10086a57f224SMarcel Ziswiler fsl,pins = 100960f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */ 101060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */ 10116a57f224SMarcel Ziswiler }; 10126a57f224SMarcel Ziswiler 10136a57f224SMarcel Ziswiler pinctrl_i2c4_gpio: i2c4gpiogrp { 10146a57f224SMarcel Ziswiler fsl,pins = 101560f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */ 101660f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */ 10176a57f224SMarcel Ziswiler }; 10186a57f224SMarcel Ziswiler 10196a57f224SMarcel Ziswiler /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 10206a57f224SMarcel Ziswiler pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 10216a57f224SMarcel Ziswiler fsl,pins = 102260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */ 10236a57f224SMarcel Ziswiler }; 10246a57f224SMarcel Ziswiler 10256a57f224SMarcel Ziswiler /* Verdin I2S_2_D_OUT shared with SAI5 */ 10266a57f224SMarcel Ziswiler pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 10276a57f224SMarcel Ziswiler fsl,pins = 102860f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */ 10296a57f224SMarcel Ziswiler }; 10306a57f224SMarcel Ziswiler 10316a57f224SMarcel Ziswiler pinctrl_pcie0: pcie0grp { 10326a57f224SMarcel Ziswiler fsl,pins = 10336a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ 10346a57f224SMarcel Ziswiler /* PMIC_EN_PCIe_CLK, unused */ 10356a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; 10366a57f224SMarcel Ziswiler }; 10376a57f224SMarcel Ziswiler 10386a57f224SMarcel Ziswiler pinctrl_pmic: pmicirqgrp { 10396a57f224SMarcel Ziswiler fsl,pins = 104060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */ 10416a57f224SMarcel Ziswiler }; 10426a57f224SMarcel Ziswiler 10436a57f224SMarcel Ziswiler /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ 10446a57f224SMarcel Ziswiler pinctrl_pwm_1: pwm1grp { 10456a57f224SMarcel Ziswiler fsl,pins = 10466a57f224SMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ 10476a57f224SMarcel Ziswiler }; 10486a57f224SMarcel Ziswiler 10496a57f224SMarcel Ziswiler pinctrl_pwm_2: pwm2grp { 10506a57f224SMarcel Ziswiler fsl,pins = 10516a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ 10526a57f224SMarcel Ziswiler }; 10536a57f224SMarcel Ziswiler 10546a57f224SMarcel Ziswiler pinctrl_pwm_3: pwm3grp { 10556a57f224SMarcel Ziswiler fsl,pins = 10566a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ 10576a57f224SMarcel Ziswiler }; 10586a57f224SMarcel Ziswiler 10596a57f224SMarcel Ziswiler /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ 10606a57f224SMarcel Ziswiler pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { 10616a57f224SMarcel Ziswiler fsl,pins = 106260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */ 10636a57f224SMarcel Ziswiler }; 10646a57f224SMarcel Ziswiler 10656a57f224SMarcel Ziswiler pinctrl_reg_eth: regethgrp { 10666a57f224SMarcel Ziswiler fsl,pins = 106760f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */ 10686a57f224SMarcel Ziswiler }; 10696a57f224SMarcel Ziswiler 10706a57f224SMarcel Ziswiler pinctrl_reg_usb1_en: regusb1engrp { 10716a57f224SMarcel Ziswiler fsl,pins = 107260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */ 10736a57f224SMarcel Ziswiler }; 10746a57f224SMarcel Ziswiler 10756a57f224SMarcel Ziswiler pinctrl_reg_usb2_en: regusb2engrp { 10766a57f224SMarcel Ziswiler fsl,pins = 107760f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */ 10786a57f224SMarcel Ziswiler }; 10796a57f224SMarcel Ziswiler 10806a57f224SMarcel Ziswiler pinctrl_sai2: sai2grp { 10816a57f224SMarcel Ziswiler fsl,pins = 108260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ 1083593c535bSMarcel Ziswiler <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */ 1084593c535bSMarcel Ziswiler <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */ 108560f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ 108660f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ 10876a57f224SMarcel Ziswiler }; 10886a57f224SMarcel Ziswiler 10896a57f224SMarcel Ziswiler pinctrl_sai5: sai5grp { 10906a57f224SMarcel Ziswiler fsl,pins = 109160f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */ 109260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */ 109360f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */ 109460f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */ 10956a57f224SMarcel Ziswiler }; 10966a57f224SMarcel Ziswiler 10976a57f224SMarcel Ziswiler /* control signal for optional ATTPM20P or SE050 */ 10986a57f224SMarcel Ziswiler pinctrl_pmic_tpm_ena: pmictpmenagrp { 10996a57f224SMarcel Ziswiler fsl,pins = 110060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ 11016a57f224SMarcel Ziswiler }; 11026a57f224SMarcel Ziswiler 11036a57f224SMarcel Ziswiler pinctrl_tsp: tspgrp { 11046a57f224SMarcel Ziswiler fsl,pins = 110560f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */ 110660f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */ 110760f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */ 110860f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */ 110960f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */ 11106a57f224SMarcel Ziswiler }; 11116a57f224SMarcel Ziswiler 11126a57f224SMarcel Ziswiler pinctrl_uart1: uart1grp { 11136a57f224SMarcel Ziswiler fsl,pins = 1114593c535bSMarcel Ziswiler <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */ 1115593c535bSMarcel Ziswiler <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */ 11166a57f224SMarcel Ziswiler }; 11176a57f224SMarcel Ziswiler 11186a57f224SMarcel Ziswiler pinctrl_uart2: uart2grp { 11196a57f224SMarcel Ziswiler fsl,pins = 112060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ 1121593c535bSMarcel Ziswiler <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */ 1122593c535bSMarcel Ziswiler <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */ 1123593c535bSMarcel Ziswiler <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */ 11246a57f224SMarcel Ziswiler }; 11256a57f224SMarcel Ziswiler 11266a57f224SMarcel Ziswiler pinctrl_uart3: uart3grp { 11276a57f224SMarcel Ziswiler fsl,pins = 112860f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ 1129593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */ 1130593c535bSMarcel Ziswiler <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */ 113160f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ 11326a57f224SMarcel Ziswiler }; 11336a57f224SMarcel Ziswiler 11346a57f224SMarcel Ziswiler pinctrl_uart4: uart4grp { 11356a57f224SMarcel Ziswiler fsl,pins = 113660f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */ 113760f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */ 11386a57f224SMarcel Ziswiler }; 11396a57f224SMarcel Ziswiler 11406a57f224SMarcel Ziswiler pinctrl_usdhc1: usdhc1grp { 11416a57f224SMarcel Ziswiler fsl,pins = 11426a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, 11436a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, 11446a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, 11456a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, 11466a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, 11476a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, 11486a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, 11496a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, 11506a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, 11516a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, 11526a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 11536a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; 11546a57f224SMarcel Ziswiler }; 11556a57f224SMarcel Ziswiler 11566a57f224SMarcel Ziswiler pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 11576a57f224SMarcel Ziswiler fsl,pins = 11586a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, 11596a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, 11606a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, 11616a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, 11626a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, 11636a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, 11646a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, 11656a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, 11666a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, 11676a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, 11686a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 11696a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; 11706a57f224SMarcel Ziswiler }; 11716a57f224SMarcel Ziswiler 11726a57f224SMarcel Ziswiler pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 11736a57f224SMarcel Ziswiler fsl,pins = 11746a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, 11756a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, 11766a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, 11776a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, 11786a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, 11796a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, 11806a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, 11816a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, 11826a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, 11836a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, 11846a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 11856a57f224SMarcel Ziswiler <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; 11866a57f224SMarcel Ziswiler }; 11876a57f224SMarcel Ziswiler 11886a57f224SMarcel Ziswiler pinctrl_usdhc2_cd: usdhc2cdgrp { 11896a57f224SMarcel Ziswiler fsl,pins = 119060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */ 11916a57f224SMarcel Ziswiler }; 11926a57f224SMarcel Ziswiler 11934f6b5de9SMarcel Ziswiler pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 11944f6b5de9SMarcel Ziswiler fsl,pins = 11954f6b5de9SMarcel Ziswiler <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */ 11964f6b5de9SMarcel Ziswiler }; 11974f6b5de9SMarcel Ziswiler 11986a57f224SMarcel Ziswiler pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 11996a57f224SMarcel Ziswiler fsl,pins = 120060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ 12016a57f224SMarcel Ziswiler }; 12026a57f224SMarcel Ziswiler 1203f84ccff6SMarcel Ziswiler /* 1204f84ccff6SMarcel Ziswiler * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the 1205f84ccff6SMarcel Ziswiler * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. 1206f84ccff6SMarcel Ziswiler */ 12076a57f224SMarcel Ziswiler pinctrl_usdhc2: usdhc2grp { 12086a57f224SMarcel Ziswiler fsl,pins = 1209593c535bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 121060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ 121160f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ 121260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ 121360f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ 121460f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ 1215593c535bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */ 12166a57f224SMarcel Ziswiler }; 12176a57f224SMarcel Ziswiler 12186a57f224SMarcel Ziswiler pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 12196a57f224SMarcel Ziswiler fsl,pins = 1220593c535bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 122160f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, 122260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, 122360f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, 122460f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, 122560f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, 1226593c535bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>; 12276a57f224SMarcel Ziswiler }; 12286a57f224SMarcel Ziswiler 12296a57f224SMarcel Ziswiler pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 12306a57f224SMarcel Ziswiler fsl,pins = 1231593c535bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 123260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, 123360f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, 123460f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, 123560f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, 123660f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, 1237593c535bSMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>; 12386a57f224SMarcel Ziswiler }; 12396a57f224SMarcel Ziswiler 12404f6b5de9SMarcel Ziswiler /* Avoid backfeeding with removed card power */ 12414f6b5de9SMarcel Ziswiler pinctrl_usdhc2_sleep: usdhc2slpgrp { 12424f6b5de9SMarcel Ziswiler fsl,pins = 12434f6b5de9SMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>, 12444f6b5de9SMarcel Ziswiler <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, 12454f6b5de9SMarcel Ziswiler <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, 12464f6b5de9SMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>, 12474f6b5de9SMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>, 12484f6b5de9SMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>, 12494f6b5de9SMarcel Ziswiler <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>; 12504f6b5de9SMarcel Ziswiler }; 12514f6b5de9SMarcel Ziswiler 125298e4f193SMarcel Ziswiler /* 125398e4f193SMarcel Ziswiler * On-module Wi-Fi/BT or type specific SDHC interface 125498e4f193SMarcel Ziswiler * (e.g. on X52 extension slot of Verdin Development Board) 125598e4f193SMarcel Ziswiler */ 12566a57f224SMarcel Ziswiler pinctrl_usdhc3: usdhc3grp { 12576a57f224SMarcel Ziswiler fsl,pins = 125860f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, 125960f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, 126060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, 1261593c535bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>, 1262593c535bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>, 1263593c535bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>; 12646a57f224SMarcel Ziswiler }; 12656a57f224SMarcel Ziswiler 12666a57f224SMarcel Ziswiler pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 12676a57f224SMarcel Ziswiler fsl,pins = 126860f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, 126960f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, 127060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, 1271593c535bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>, 1272593c535bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>, 1273593c535bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>; 12746a57f224SMarcel Ziswiler }; 12756a57f224SMarcel Ziswiler 12766a57f224SMarcel Ziswiler pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 12776a57f224SMarcel Ziswiler fsl,pins = 127860f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, 127960f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, 128060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, 1281593c535bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>, 1282593c535bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>, 1283593c535bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>; 12846a57f224SMarcel Ziswiler }; 12856a57f224SMarcel Ziswiler 12866a57f224SMarcel Ziswiler pinctrl_wdog: wdoggrp { 12876a57f224SMarcel Ziswiler fsl,pins = 128860f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */ 12896a57f224SMarcel Ziswiler }; 12906a57f224SMarcel Ziswiler 12916a57f224SMarcel Ziswiler pinctrl_wifi_ctrl: wifictrlgrp { 12926a57f224SMarcel Ziswiler fsl,pins = 129360f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */ 129460f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */ 129560f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */ 12966a57f224SMarcel Ziswiler }; 12976a57f224SMarcel Ziswiler 12986a57f224SMarcel Ziswiler pinctrl_wifi_i2s: bti2sgrp { 12996a57f224SMarcel Ziswiler fsl,pins = 130060f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */ 130160f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */ 130260f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */ 130360f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */ 13046a57f224SMarcel Ziswiler }; 13056a57f224SMarcel Ziswiler 13066a57f224SMarcel Ziswiler pinctrl_wifi_pwr_en: wifipwrengrp { 13076a57f224SMarcel Ziswiler fsl,pins = 130860f01b5bSMarcel Ziswiler <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */ 13096a57f224SMarcel Ziswiler }; 13106a57f224SMarcel Ziswiler}; 1311