16a57f224SMarcel Ziswiler// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 26a57f224SMarcel Ziswiler/* 36a57f224SMarcel Ziswiler * Copyright 2022 Toradex 46a57f224SMarcel Ziswiler */ 56a57f224SMarcel Ziswiler 66a57f224SMarcel Ziswiler/ { 76a57f224SMarcel Ziswiler sound_card: sound-card { 86a57f224SMarcel Ziswiler compatible = "simple-audio-card"; 96a57f224SMarcel Ziswiler simple-audio-card,bitclock-master = <&dailink_master>; 106a57f224SMarcel Ziswiler simple-audio-card,format = "i2s"; 116a57f224SMarcel Ziswiler simple-audio-card,frame-master = <&dailink_master>; 126a57f224SMarcel Ziswiler simple-audio-card,name = "imx8mm-wm8904"; 136a57f224SMarcel Ziswiler simple-audio-card,routing = 146a57f224SMarcel Ziswiler "Headphone Jack", "HPOUTL", 156a57f224SMarcel Ziswiler "Headphone Jack", "HPOUTR", 166a57f224SMarcel Ziswiler "IN2L", "Line In Jack", 176a57f224SMarcel Ziswiler "IN2R", "Line In Jack", 186a57f224SMarcel Ziswiler "Headphone Jack", "MICBIAS", 196a57f224SMarcel Ziswiler "IN1L", "Headphone Jack"; 206a57f224SMarcel Ziswiler simple-audio-card,widgets = 216a57f224SMarcel Ziswiler "Microphone", "Headphone Jack", 226a57f224SMarcel Ziswiler "Headphone", "Headphone Jack", 236a57f224SMarcel Ziswiler "Line", "Line In Jack"; 246a57f224SMarcel Ziswiler 256a57f224SMarcel Ziswiler dailink_master: simple-audio-card,codec { 266a57f224SMarcel Ziswiler clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; 276a57f224SMarcel Ziswiler sound-dai = <&wm8904_1a>; 286a57f224SMarcel Ziswiler }; 296a57f224SMarcel Ziswiler 306a57f224SMarcel Ziswiler simple-audio-card,cpu { 316a57f224SMarcel Ziswiler sound-dai = <&sai2>; 326a57f224SMarcel Ziswiler }; 336a57f224SMarcel Ziswiler }; 346a57f224SMarcel Ziswiler}; 356a57f224SMarcel Ziswiler 366a57f224SMarcel Ziswiler/* Verdin SPI_1 */ 376a57f224SMarcel Ziswiler&ecspi2 { 386a57f224SMarcel Ziswiler status = "okay"; 396a57f224SMarcel Ziswiler}; 406a57f224SMarcel Ziswiler 416a57f224SMarcel Ziswiler/* EEPROM on display adapter boards */ 426a57f224SMarcel Ziswiler&eeprom_display_adapter { 436a57f224SMarcel Ziswiler status = "okay"; 446a57f224SMarcel Ziswiler}; 456a57f224SMarcel Ziswiler 466a57f224SMarcel Ziswiler/* EEPROM on Verdin Development board */ 476a57f224SMarcel Ziswiler&eeprom_carrier_board { 486a57f224SMarcel Ziswiler status = "okay"; 496a57f224SMarcel Ziswiler}; 506a57f224SMarcel Ziswiler 516a57f224SMarcel Ziswiler&fec1 { 526a57f224SMarcel Ziswiler status = "okay"; 536a57f224SMarcel Ziswiler}; 546a57f224SMarcel Ziswiler 556a57f224SMarcel Ziswiler/* Verdin QSPI_1 */ 566a57f224SMarcel Ziswiler&flexspi { 576a57f224SMarcel Ziswiler status = "okay"; 586a57f224SMarcel Ziswiler}; 596a57f224SMarcel Ziswiler 606a57f224SMarcel Ziswiler/* Current measurement into module VCC */ 616a57f224SMarcel Ziswiler&hwmon { 626a57f224SMarcel Ziswiler status = "okay"; 636a57f224SMarcel Ziswiler}; 646a57f224SMarcel Ziswiler 656a57f224SMarcel Ziswiler&hwmon_temp { 666a57f224SMarcel Ziswiler vs-supply = <®_1p8v>; 676a57f224SMarcel Ziswiler status = "okay"; 686a57f224SMarcel Ziswiler}; 696a57f224SMarcel Ziswiler 706a57f224SMarcel Ziswiler&i2c3 { 716a57f224SMarcel Ziswiler status = "okay"; 726a57f224SMarcel Ziswiler}; 736a57f224SMarcel Ziswiler 746a57f224SMarcel Ziswiler/* Verdin I2C_1 */ 756a57f224SMarcel Ziswiler&i2c4 { 766a57f224SMarcel Ziswiler status = "okay"; 776a57f224SMarcel Ziswiler 786a57f224SMarcel Ziswiler /* Audio Codec */ 796a57f224SMarcel Ziswiler wm8904_1a: audio-codec@1a { 806a57f224SMarcel Ziswiler compatible = "wlf,wm8904"; 816a57f224SMarcel Ziswiler AVDD-supply = <®_3p3v>; 826a57f224SMarcel Ziswiler clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; 836a57f224SMarcel Ziswiler clock-names = "mclk"; 846a57f224SMarcel Ziswiler CPVDD-supply = <®_3p3v>; 856a57f224SMarcel Ziswiler DBVDD-supply = <®_3p3v>; 866a57f224SMarcel Ziswiler DCVDD-supply = <®_3p3v>; 876a57f224SMarcel Ziswiler MICVDD-supply = <®_3p3v>; 886a57f224SMarcel Ziswiler reg = <0x1a>; 896a57f224SMarcel Ziswiler #sound-dai-cells = <0>; 906a57f224SMarcel Ziswiler }; 916a57f224SMarcel Ziswiler}; 926a57f224SMarcel Ziswiler 936a57f224SMarcel Ziswiler/* Verdin PCIE_1 */ 946a57f224SMarcel Ziswiler&pcie0 { 956a57f224SMarcel Ziswiler status = "okay"; 966a57f224SMarcel Ziswiler}; 976a57f224SMarcel Ziswiler 986a57f224SMarcel Ziswiler&pcie_phy { 996a57f224SMarcel Ziswiler status = "okay"; 1006a57f224SMarcel Ziswiler}; 1016a57f224SMarcel Ziswiler 1026a57f224SMarcel Ziswiler/* Verdin PWM_3_DSI */ 1036a57f224SMarcel Ziswiler&pwm1 { 1046a57f224SMarcel Ziswiler status = "okay"; 1056a57f224SMarcel Ziswiler}; 1066a57f224SMarcel Ziswiler 1076a57f224SMarcel Ziswiler/* Verdin PWM_1 */ 1086a57f224SMarcel Ziswiler&pwm2 { 1096a57f224SMarcel Ziswiler status = "okay"; 1106a57f224SMarcel Ziswiler}; 1116a57f224SMarcel Ziswiler 1126a57f224SMarcel Ziswiler/* Verdin PWM_2 */ 1136a57f224SMarcel Ziswiler&pwm3 { 1146a57f224SMarcel Ziswiler status = "okay"; 1156a57f224SMarcel Ziswiler}; 1166a57f224SMarcel Ziswiler 117*473b34b8SMarcel Ziswiler/* Verdin I2S_1 */ 1186a57f224SMarcel Ziswiler&sai2 { 1196a57f224SMarcel Ziswiler status = "okay"; 1206a57f224SMarcel Ziswiler}; 1216a57f224SMarcel Ziswiler 1226a57f224SMarcel Ziswiler/* Verdin UART_3 */ 1236a57f224SMarcel Ziswiler&uart1 { 1246a57f224SMarcel Ziswiler status = "okay"; 1256a57f224SMarcel Ziswiler}; 1266a57f224SMarcel Ziswiler 1276a57f224SMarcel Ziswiler/* Verdin UART_1 */ 1286a57f224SMarcel Ziswiler&uart2 { 1296a57f224SMarcel Ziswiler status = "okay"; 1306a57f224SMarcel Ziswiler}; 1316a57f224SMarcel Ziswiler 1326a57f224SMarcel Ziswiler/* Verdin UART_2 */ 1336a57f224SMarcel Ziswiler&uart3 { 1346a57f224SMarcel Ziswiler status = "okay"; 1356a57f224SMarcel Ziswiler}; 1366a57f224SMarcel Ziswiler 1376a57f224SMarcel Ziswiler/* Verdin USB_1 */ 1386a57f224SMarcel Ziswiler&usbotg1 { 1396a57f224SMarcel Ziswiler status = "okay"; 1406a57f224SMarcel Ziswiler}; 1416a57f224SMarcel Ziswiler 1426a57f224SMarcel Ziswiler/* Verdin USB_2 */ 1436a57f224SMarcel Ziswiler&usbotg2 { 1446a57f224SMarcel Ziswiler status = "okay"; 1456a57f224SMarcel Ziswiler}; 1466a57f224SMarcel Ziswiler 1476a57f224SMarcel Ziswiler/* Verdin SD_1 */ 1486a57f224SMarcel Ziswiler&usdhc2 { 1496a57f224SMarcel Ziswiler status = "okay"; 1506a57f224SMarcel Ziswiler}; 151