1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy-imx8-pcie.h> 13 14#include "imx8mm.dtsi" 15 16/ { 17 model = "Gateworks Venice GW7902 i.MX8MM board"; 18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm"; 19 20 aliases { 21 ethernet1 = ð1; 22 usb0 = &usbotg1; 23 usb1 = &usbotg2; 24 }; 25 26 chosen { 27 stdout-path = &uart2; 28 }; 29 30 memory@40000000 { 31 device_type = "memory"; 32 reg = <0x0 0x40000000 0 0x80000000>; 33 }; 34 35 can20m: can20m { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <20000000>; 39 clock-output-names = "can20m"; 40 }; 41 42 gpio-keys { 43 compatible = "gpio-keys"; 44 45 user-pb { 46 label = "user_pb"; 47 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 48 linux,code = <BTN_0>; 49 }; 50 51 user-pb1x { 52 label = "user_pb1x"; 53 linux,code = <BTN_1>; 54 interrupt-parent = <&gsc>; 55 interrupts = <0>; 56 }; 57 58 key-erased { 59 label = "key_erased"; 60 linux,code = <BTN_2>; 61 interrupt-parent = <&gsc>; 62 interrupts = <1>; 63 }; 64 65 eeprom-wp { 66 label = "eeprom_wp"; 67 linux,code = <BTN_3>; 68 interrupt-parent = <&gsc>; 69 interrupts = <2>; 70 }; 71 72 tamper { 73 label = "tamper"; 74 linux,code = <BTN_4>; 75 interrupt-parent = <&gsc>; 76 interrupts = <5>; 77 }; 78 79 switch-hold { 80 label = "switch_hold"; 81 linux,code = <BTN_5>; 82 interrupt-parent = <&gsc>; 83 interrupts = <7>; 84 }; 85 }; 86 87 led-controller { 88 compatible = "gpio-leds"; 89 pinctrl-names = "default"; 90 pinctrl-0 = <&pinctrl_gpio_leds>; 91 92 led-0 { 93 function = LED_FUNCTION_STATUS; 94 color = <LED_COLOR_ID_GREEN>; 95 label = "panel1"; 96 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; 97 default-state = "off"; 98 }; 99 100 led-1 { 101 function = LED_FUNCTION_STATUS; 102 color = <LED_COLOR_ID_GREEN>; 103 label = "panel2"; 104 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 105 default-state = "off"; 106 }; 107 108 led-2 { 109 function = LED_FUNCTION_STATUS; 110 color = <LED_COLOR_ID_GREEN>; 111 label = "panel3"; 112 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 113 default-state = "off"; 114 }; 115 116 led-3 { 117 function = LED_FUNCTION_STATUS; 118 color = <LED_COLOR_ID_GREEN>; 119 label = "panel4"; 120 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 121 default-state = "off"; 122 }; 123 124 led-4 { 125 function = LED_FUNCTION_STATUS; 126 color = <LED_COLOR_ID_GREEN>; 127 label = "panel5"; 128 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; 129 default-state = "off"; 130 }; 131 }; 132 133 pcie0_refclk: pcie0-refclk { 134 compatible = "fixed-clock"; 135 #clock-cells = <0>; 136 clock-frequency = <100000000>; 137 }; 138 139 pps { 140 compatible = "pps-gpio"; 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_pps>; 143 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 144 status = "okay"; 145 }; 146 147 reg_3p3v: regulator-3p3v { 148 compatible = "regulator-fixed"; 149 regulator-name = "3P3V"; 150 regulator-min-microvolt = <3300000>; 151 regulator-max-microvolt = <3300000>; 152 regulator-always-on; 153 }; 154 155 reg_usb1_vbus: regulator-usb1 { 156 compatible = "regulator-fixed"; 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pinctrl_reg_usb1>; 159 regulator-name = "usb_usb1_vbus"; 160 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; 161 enable-active-high; 162 regulator-min-microvolt = <5000000>; 163 regulator-max-microvolt = <5000000>; 164 }; 165 166 reg_wifi: regulator-wifi { 167 compatible = "regulator-fixed"; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_reg_wl>; 170 regulator-name = "wifi"; 171 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 172 enable-active-high; 173 startup-delay-us = <100>; 174 regulator-min-microvolt = <3300000>; 175 regulator-max-microvolt = <3300000>; 176 }; 177}; 178 179&A53_0 { 180 cpu-supply = <&buck2>; 181}; 182 183&A53_1 { 184 cpu-supply = <&buck2>; 185}; 186 187&A53_2 { 188 cpu-supply = <&buck2>; 189}; 190 191&A53_3 { 192 cpu-supply = <&buck2>; 193}; 194 195&ddrc { 196 operating-points-v2 = <&ddrc_opp_table>; 197 198 ddrc_opp_table: opp-table { 199 compatible = "operating-points-v2"; 200 201 opp-25M { 202 opp-hz = /bits/ 64 <25000000>; 203 }; 204 205 opp-100M { 206 opp-hz = /bits/ 64 <100000000>; 207 }; 208 209 opp-750M { 210 opp-hz = /bits/ 64 <750000000>; 211 }; 212 }; 213}; 214 215&ecspi1 { 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_spi1>; 218 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 219 status = "okay"; 220 221 can@0 { 222 compatible = "microchip,mcp2515"; 223 reg = <0>; 224 clocks = <&can20m>; 225 oscillator-frequency = <20000000>; 226 interrupt-parent = <&gpio2>; 227 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 228 spi-max-frequency = <10000000>; 229 }; 230}; 231 232/* off-board header */ 233&ecspi2 { 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_spi2>; 236 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 237 status = "okay"; 238}; 239 240&fec1 { 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_fec1>; 243 phy-mode = "rgmii-id"; 244 phy-handle = <ðphy0>; 245 local-mac-address = [00 00 00 00 00 00]; 246 status = "okay"; 247 248 mdio { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 252 ethphy0: ethernet-phy@0 { 253 compatible = "ethernet-phy-ieee802.3-c22"; 254 reg = <0>; 255 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 256 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 257 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 258 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 259 }; 260 }; 261}; 262 263&i2c1 { 264 clock-frequency = <100000>; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_i2c1>; 267 status = "okay"; 268 269 gsc: gsc@20 { 270 compatible = "gw,gsc"; 271 reg = <0x20>; 272 pinctrl-0 = <&pinctrl_gsc>; 273 interrupt-parent = <&gpio2>; 274 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 275 interrupt-controller; 276 #interrupt-cells = <1>; 277 278 adc { 279 compatible = "gw,gsc-adc"; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 283 channel@6 { 284 gw,mode = <0>; 285 reg = <0x06>; 286 label = "temp"; 287 }; 288 289 channel@8 { 290 gw,mode = <1>; 291 reg = <0x08>; 292 label = "vdd_bat"; 293 }; 294 295 channel@82 { 296 gw,mode = <2>; 297 reg = <0x82>; 298 label = "vin"; 299 gw,voltage-divider-ohms = <22100 1000>; 300 gw,voltage-offset-microvolt = <700000>; 301 }; 302 303 channel@84 { 304 gw,mode = <2>; 305 reg = <0x84>; 306 label = "vin_4p0"; 307 gw,voltage-divider-ohms = <10000 10000>; 308 }; 309 310 channel@86 { 311 gw,mode = <2>; 312 reg = <0x86>; 313 label = "vdd_3p3"; 314 gw,voltage-divider-ohms = <10000 10000>; 315 }; 316 317 channel@88 { 318 gw,mode = <2>; 319 reg = <0x88>; 320 label = "vdd_0p9"; 321 }; 322 323 channel@8c { 324 gw,mode = <2>; 325 reg = <0x8c>; 326 label = "vdd_soc"; 327 }; 328 329 channel@8e { 330 gw,mode = <2>; 331 reg = <0x8e>; 332 label = "vdd_arm"; 333 }; 334 335 channel@90 { 336 gw,mode = <2>; 337 reg = <0x90>; 338 label = "vdd_1p8"; 339 }; 340 341 channel@92 { 342 gw,mode = <2>; 343 reg = <0x92>; 344 label = "vdd_dram"; 345 }; 346 347 channel@98 { 348 gw,mode = <2>; 349 reg = <0x98>; 350 label = "vdd_1p0"; 351 }; 352 353 channel@9a { 354 gw,mode = <2>; 355 reg = <0x9a>; 356 label = "vdd_2p5"; 357 gw,voltage-divider-ohms = <10000 10000>; 358 }; 359 360 channel@a2 { 361 gw,mode = <2>; 362 reg = <0xa2>; 363 label = "vdd_gsc"; 364 gw,voltage-divider-ohms = <10000 10000>; 365 }; 366 }; 367 }; 368 369 gpio: gpio@23 { 370 compatible = "nxp,pca9555"; 371 reg = <0x23>; 372 gpio-controller; 373 #gpio-cells = <2>; 374 interrupt-parent = <&gsc>; 375 interrupts = <4>; 376 }; 377 378 pmic@4b { 379 compatible = "rohm,bd71847"; 380 reg = <0x4b>; 381 pinctrl-names = "default"; 382 pinctrl-0 = <&pinctrl_pmic>; 383 interrupt-parent = <&gpio3>; 384 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 385 rohm,reset-snvs-powered; 386 #clock-cells = <0>; 387 clocks = <&osc_32k 0>; 388 clock-output-names = "clk-32k-out"; 389 390 regulators { 391 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 392 BUCK1 { 393 regulator-name = "buck1"; 394 regulator-min-microvolt = <700000>; 395 regulator-max-microvolt = <1300000>; 396 regulator-boot-on; 397 regulator-always-on; 398 regulator-ramp-delay = <1250>; 399 }; 400 401 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 402 buck2: BUCK2 { 403 regulator-name = "buck2"; 404 regulator-min-microvolt = <700000>; 405 regulator-max-microvolt = <1300000>; 406 regulator-boot-on; 407 regulator-always-on; 408 regulator-ramp-delay = <1250>; 409 rohm,dvs-run-voltage = <1000000>; 410 rohm,dvs-idle-voltage = <900000>; 411 }; 412 413 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 414 BUCK3 { 415 regulator-name = "buck3"; 416 regulator-min-microvolt = <700000>; 417 regulator-max-microvolt = <1350000>; 418 regulator-boot-on; 419 regulator-always-on; 420 }; 421 422 /* vdd_3p3 */ 423 BUCK4 { 424 regulator-name = "buck4"; 425 regulator-min-microvolt = <3000000>; 426 regulator-max-microvolt = <3300000>; 427 regulator-boot-on; 428 regulator-always-on; 429 }; 430 431 /* vdd_1p8 */ 432 BUCK5 { 433 regulator-name = "buck5"; 434 regulator-min-microvolt = <1605000>; 435 regulator-max-microvolt = <1995000>; 436 regulator-boot-on; 437 regulator-always-on; 438 }; 439 440 /* vdd_dram */ 441 BUCK6 { 442 regulator-name = "buck6"; 443 regulator-min-microvolt = <800000>; 444 regulator-max-microvolt = <1400000>; 445 regulator-boot-on; 446 regulator-always-on; 447 }; 448 449 /* nvcc_snvs_1p8 */ 450 LDO1 { 451 regulator-name = "ldo1"; 452 regulator-min-microvolt = <1600000>; 453 regulator-max-microvolt = <1900000>; 454 regulator-boot-on; 455 regulator-always-on; 456 }; 457 458 /* vdd_snvs_0p8 */ 459 LDO2 { 460 regulator-name = "ldo2"; 461 regulator-min-microvolt = <800000>; 462 regulator-max-microvolt = <900000>; 463 regulator-boot-on; 464 regulator-always-on; 465 }; 466 467 /* vdda_1p8 */ 468 LDO3 { 469 regulator-name = "ldo3"; 470 regulator-min-microvolt = <1800000>; 471 regulator-max-microvolt = <3300000>; 472 regulator-boot-on; 473 regulator-always-on; 474 }; 475 476 LDO4 { 477 regulator-name = "ldo4"; 478 regulator-min-microvolt = <900000>; 479 regulator-max-microvolt = <1800000>; 480 regulator-boot-on; 481 regulator-always-on; 482 }; 483 484 LDO6 { 485 regulator-name = "ldo6"; 486 regulator-min-microvolt = <900000>; 487 regulator-max-microvolt = <1800000>; 488 regulator-boot-on; 489 regulator-always-on; 490 }; 491 }; 492 }; 493 494 eeprom@50 { 495 compatible = "atmel,24c02"; 496 reg = <0x50>; 497 pagesize = <16>; 498 }; 499 500 eeprom@51 { 501 compatible = "atmel,24c02"; 502 reg = <0x51>; 503 pagesize = <16>; 504 }; 505 506 eeprom@52 { 507 compatible = "atmel,24c02"; 508 reg = <0x52>; 509 pagesize = <16>; 510 }; 511 512 eeprom@53 { 513 compatible = "atmel,24c02"; 514 reg = <0x53>; 515 pagesize = <16>; 516 }; 517 518 rtc@68 { 519 compatible = "dallas,ds1672"; 520 reg = <0x68>; 521 }; 522}; 523 524&i2c2 { 525 clock-frequency = <400000>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&pinctrl_i2c2>; 528 status = "okay"; 529 530 accelerometer@19 { 531 compatible = "st,lis2de12"; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&pinctrl_accel>; 534 reg = <0x19>; 535 st,drdy-int-pin = <1>; 536 interrupt-parent = <&gpio1>; 537 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 538 interrupt-names = "INT1"; 539 }; 540}; 541 542/* off-board header */ 543&i2c3 { 544 clock-frequency = <400000>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&pinctrl_i2c3>; 547 status = "okay"; 548}; 549 550/* off-board header */ 551&i2c4 { 552 clock-frequency = <400000>; 553 pinctrl-names = "default"; 554 pinctrl-0 = <&pinctrl_i2c4>; 555 status = "okay"; 556}; 557 558&pcie_phy { 559 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 560 fsl,clkreq-unsupported; 561 clocks = <&clk IMX8MM_CLK_DUMMY>; 562 status = "okay"; 563}; 564 565&pcie0 { 566 pinctrl-names = "default"; 567 pinctrl-0 = <&pinctrl_pcie0>; 568 reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; 569 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, 570 <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>; 571 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; 572 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 573 <&clk IMX8MM_CLK_PCIE1_CTRL>; 574 assigned-clock-rates = <10000000>, <250000000>; 575 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 576 <&clk IMX8MM_SYS_PLL2_250M>; 577 status = "okay"; 578 579 pcie@0,0 { 580 reg = <0x0000 0 0 0 0>; 581 #address-cells = <1>; 582 #size-cells = <0>; 583 584 eth1: pcie@1,0 { 585 reg = <0x0000 0 0 0 0>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 589 local-mac-address = [00 00 00 00 00 00]; 590 }; 591 }; 592}; 593 594/* off-board header */ 595&sai3 { 596 pinctrl-names = "default"; 597 pinctrl-0 = <&pinctrl_sai3>; 598 assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 599 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 600 assigned-clock-rates = <24576000>; 601 status = "okay"; 602}; 603 604/* RS232/RS485/RS422 selectable */ 605&uart1 { 606 pinctrl-names = "default"; 607 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; 608 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; 609 cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; 610 status = "okay"; 611}; 612 613/* RS232 console */ 614&uart2 { 615 pinctrl-names = "default"; 616 pinctrl-0 = <&pinctrl_uart2>; 617 status = "okay"; 618}; 619 620/* bluetooth HCI */ 621&uart3 { 622 pinctrl-names = "default"; 623 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 624 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 625 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 626 status = "okay"; 627 628 bluetooth { 629 compatible = "brcm,bcm4330-bt"; 630 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 631 }; 632}; 633 634/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */ 635&uart4 { 636 pinctrl-names = "default"; 637 pinctrl-0 = <&pinctrl_uart4>; 638 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 639 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; 640 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; 641 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; 642 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; 643 status = "okay"; 644}; 645 646&usbotg1 { 647 dr_mode = "host"; 648 vbus-supply = <®_usb1_vbus>; 649 disable-over-current; 650 status = "okay"; 651}; 652 653&usbotg2 { 654 dr_mode = "host"; 655 disable-over-current; 656 status = "okay"; 657}; 658 659/* SDIO WiFi */ 660&usdhc2 { 661 pinctrl-names = "default"; 662 pinctrl-0 = <&pinctrl_usdhc2>; 663 bus-width = <4>; 664 non-removable; 665 vmmc-supply = <®_wifi>; 666 status = "okay"; 667}; 668 669/* eMMC */ 670&usdhc3 { 671 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 672 pinctrl-0 = <&pinctrl_usdhc3>; 673 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 674 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 675 bus-width = <8>; 676 non-removable; 677 status = "okay"; 678}; 679 680&wdog1 { 681 pinctrl-names = "default"; 682 pinctrl-0 = <&pinctrl_wdog>; 683 fsl,ext-reset-output; 684 status = "okay"; 685}; 686 687&iomuxc { 688 pinctrl-names = "default"; 689 pinctrl-0 = <&pinctrl_hog>; 690 691 pinctrl_hog: hoggrp { 692 fsl,pins = < 693 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ 694 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */ 695 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ 696 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ 697 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ 698 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ 699 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ 700 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */ 701 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ 702 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ 703 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ 704 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ 705 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */ 706 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */ 707 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */ 708 >; 709 }; 710 711 pinctrl_accel: accelgrp { 712 fsl,pins = < 713 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159 714 >; 715 }; 716 717 pinctrl_fec1: fec1grp { 718 fsl,pins = < 719 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 720 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 721 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 722 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 723 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 724 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 725 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 726 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 727 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 728 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 729 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 730 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 731 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 732 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 733 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ 734 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ 735 MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 736 MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 737 >; 738 }; 739 740 pinctrl_gsc: gscgrp { 741 fsl,pins = < 742 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40 743 >; 744 }; 745 746 pinctrl_i2c1: i2c1grp { 747 fsl,pins = < 748 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 749 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 750 >; 751 }; 752 753 pinctrl_i2c2: i2c2grp { 754 fsl,pins = < 755 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 756 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 757 >; 758 }; 759 760 pinctrl_i2c3: i2c3grp { 761 fsl,pins = < 762 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 763 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 764 >; 765 }; 766 767 pinctrl_i2c4: i2c4grp { 768 fsl,pins = < 769 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 770 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 771 >; 772 }; 773 774 pinctrl_gpio_leds: gpioledgrp { 775 fsl,pins = < 776 MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 777 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 778 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 779 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 780 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 781 >; 782 }; 783 784 pinctrl_pcie0: pciegrp { 785 fsl,pins = < 786 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41 787 >; 788 }; 789 790 pinctrl_pmic: pmicgrp { 791 fsl,pins = < 792 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 793 >; 794 }; 795 796 pinctrl_pps: ppsgrp { 797 fsl,pins = < 798 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */ 799 >; 800 }; 801 802 pinctrl_reg_wl: regwlgrp { 803 fsl,pins = < 804 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */ 805 >; 806 }; 807 808 pinctrl_reg_usb1: regusb1grp { 809 fsl,pins = < 810 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41 811 >; 812 }; 813 814 pinctrl_sai3: sai3grp { 815 fsl,pins = < 816 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 817 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 818 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 819 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 820 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 821 >; 822 }; 823 824 pinctrl_spi1: spi1grp { 825 fsl,pins = < 826 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 827 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 828 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 829 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 830 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */ 831 >; 832 }; 833 834 pinctrl_spi2: spi2grp { 835 fsl,pins = < 836 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 837 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 838 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 839 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */ 840 >; 841 }; 842 843 pinctrl_uart1: uart1grp { 844 fsl,pins = < 845 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 846 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 847 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */ 848 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */ 849 >; 850 }; 851 852 pinctrl_uart1_gpio: uart1gpiogrp { 853 fsl,pins = < 854 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */ 855 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */ 856 MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */ 857 >; 858 }; 859 860 pinctrl_uart2: uart2grp { 861 fsl,pins = < 862 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 863 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 864 >; 865 }; 866 867 pinctrl_uart3_gpio: uart3_gpiogrp { 868 fsl,pins = < 869 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */ 870 >; 871 }; 872 873 pinctrl_uart3: uart3grp { 874 fsl,pins = < 875 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 876 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 877 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */ 878 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */ 879 >; 880 }; 881 882 pinctrl_uart4: uart4grp { 883 fsl,pins = < 884 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 885 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 886 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */ 887 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */ 888 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */ 889 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */ 890 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */ 891 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */ 892 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */ 893 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */ 894 >; 895 }; 896 897 pinctrl_usdhc2: usdhc2grp { 898 fsl,pins = < 899 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 900 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 901 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 902 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 903 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 904 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 905 >; 906 }; 907 908 pinctrl_usdhc3: usdhc3grp { 909 fsl,pins = < 910 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 911 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 912 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 913 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 914 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 915 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 916 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 917 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 918 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 919 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 920 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 921 >; 922 }; 923 924 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 925 fsl,pins = < 926 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 927 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 928 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 929 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 930 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 931 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 932 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 933 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 934 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 935 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 936 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 937 >; 938 }; 939 940 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 941 fsl,pins = < 942 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 943 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 944 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 945 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 946 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 947 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 948 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 949 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 950 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 951 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 952 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 953 >; 954 }; 955 956 pinctrl_wdog: wdoggrp { 957 fsl,pins = < 958 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 959 >; 960 }; 961}; 962