1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/net/ti-dp83867.h>
12
13#include "imx8mm.dtsi"
14
15/ {
16	model = "Gateworks Venice GW7902 i.MX8MM board";
17	compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
18
19	aliases {
20		usb0 = &usbotg1;
21		usb1 = &usbotg2;
22	};
23
24	chosen {
25		stdout-path = &uart2;
26	};
27
28	memory@40000000 {
29		device_type = "memory";
30		reg = <0x0 0x40000000 0 0x80000000>;
31	};
32
33	can20m: can20m {
34		compatible = "fixed-clock";
35		#clock-cells = <0>;
36		clock-frequency = <20000000>;
37		clock-output-names = "can20m";
38	};
39
40	gpio-keys {
41		compatible = "gpio-keys";
42
43		user-pb {
44			label = "user_pb";
45			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
46			linux,code = <BTN_0>;
47		};
48
49		user-pb1x {
50			label = "user_pb1x";
51			linux,code = <BTN_1>;
52			interrupt-parent = <&gsc>;
53			interrupts = <0>;
54		};
55
56		key-erased {
57			label = "key_erased";
58			linux,code = <BTN_2>;
59			interrupt-parent = <&gsc>;
60			interrupts = <1>;
61		};
62
63		eeprom-wp {
64			label = "eeprom_wp";
65			linux,code = <BTN_3>;
66			interrupt-parent = <&gsc>;
67			interrupts = <2>;
68		};
69
70		tamper {
71			label = "tamper";
72			linux,code = <BTN_4>;
73			interrupt-parent = <&gsc>;
74			interrupts = <5>;
75		};
76
77		switch-hold {
78			label = "switch_hold";
79			linux,code = <BTN_5>;
80			interrupt-parent = <&gsc>;
81			interrupts = <7>;
82		};
83	};
84
85	led-controller {
86		compatible = "gpio-leds";
87		pinctrl-names = "default";
88		pinctrl-0 = <&pinctrl_gpio_leds>;
89
90		led-0 {
91			function = LED_FUNCTION_STATUS;
92			color = <LED_COLOR_ID_GREEN>;
93			label = "panel1";
94			gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
95			default-state = "off";
96		};
97
98		led-1 {
99			function = LED_FUNCTION_STATUS;
100			color = <LED_COLOR_ID_GREEN>;
101			label = "panel2";
102			gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
103			default-state = "off";
104		};
105
106		led-2 {
107			function = LED_FUNCTION_STATUS;
108			color = <LED_COLOR_ID_GREEN>;
109			label = "panel3";
110			gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
111			default-state = "off";
112		};
113
114		led-3 {
115			function = LED_FUNCTION_STATUS;
116			color = <LED_COLOR_ID_GREEN>;
117			label = "panel4";
118			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
119			default-state = "off";
120		};
121
122		led-4 {
123			function = LED_FUNCTION_STATUS;
124			color = <LED_COLOR_ID_GREEN>;
125			label = "panel5";
126			gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
127			default-state = "off";
128		};
129	};
130
131	pps {
132		compatible = "pps-gpio";
133		pinctrl-names = "default";
134		pinctrl-0 = <&pinctrl_pps>;
135		gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
136		status = "okay";
137	};
138
139	reg_3p3v: regulator-3p3v {
140		compatible = "regulator-fixed";
141		regulator-name = "3P3V";
142		regulator-min-microvolt = <3300000>;
143		regulator-max-microvolt = <3300000>;
144		regulator-always-on;
145	};
146
147	reg_usb1_vbus: regulator-usb1 {
148		compatible = "regulator-fixed";
149		pinctrl-names = "default";
150		pinctrl-0 = <&pinctrl_reg_usb1>;
151		regulator-name = "usb_usb1_vbus";
152		gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
153		enable-active-high;
154		regulator-min-microvolt = <5000000>;
155		regulator-max-microvolt = <5000000>;
156	};
157
158	reg_wifi: regulator-wifi {
159		compatible = "regulator-fixed";
160		pinctrl-names = "default";
161		pinctrl-0 = <&pinctrl_reg_wl>;
162		regulator-name = "wifi";
163		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
164		enable-active-high;
165		startup-delay-us = <100>;
166		regulator-min-microvolt = <3300000>;
167		regulator-max-microvolt = <3300000>;
168	};
169};
170
171&A53_0 {
172	cpu-supply = <&buck2>;
173};
174
175&A53_1 {
176	cpu-supply = <&buck2>;
177};
178
179&A53_2 {
180	cpu-supply = <&buck2>;
181};
182
183&A53_3 {
184	cpu-supply = <&buck2>;
185};
186
187&ddrc {
188	operating-points-v2 = <&ddrc_opp_table>;
189
190	ddrc_opp_table: opp-table {
191		compatible = "operating-points-v2";
192
193		opp-25M {
194			opp-hz = /bits/ 64 <25000000>;
195		};
196
197		opp-100M {
198			opp-hz = /bits/ 64 <100000000>;
199		};
200
201		opp-750M {
202			opp-hz = /bits/ 64 <750000000>;
203		};
204	};
205};
206
207&ecspi1 {
208	pinctrl-names = "default";
209	pinctrl-0 = <&pinctrl_spi1>;
210	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
211	status = "okay";
212
213	can@0 {
214		compatible = "microchip,mcp2515";
215		reg = <0>;
216		clocks = <&can20m>;
217		oscillator-frequency = <20000000>;
218		interrupt-parent = <&gpio2>;
219		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
220		spi-max-frequency = <10000000>;
221	};
222};
223
224/* off-board header */
225&ecspi2 {
226	pinctrl-names = "default";
227	pinctrl-0 = <&pinctrl_spi2>;
228	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
229	status = "okay";
230};
231
232&fec1 {
233	pinctrl-names = "default";
234	pinctrl-0 = <&pinctrl_fec1>;
235	phy-mode = "rgmii-id";
236	phy-handle = <&ethphy0>;
237	local-mac-address = [00 00 00 00 00 00];
238	status = "okay";
239
240	mdio {
241		#address-cells = <1>;
242		#size-cells = <0>;
243
244		ethphy0: ethernet-phy@0 {
245			compatible = "ethernet-phy-ieee802.3-c22";
246			reg = <0>;
247			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
248			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
249			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
250			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
251		};
252	};
253};
254
255&i2c1 {
256	clock-frequency = <100000>;
257	pinctrl-names = "default";
258	pinctrl-0 = <&pinctrl_i2c1>;
259	status = "okay";
260
261	gsc: gsc@20 {
262		compatible = "gw,gsc";
263		reg = <0x20>;
264		pinctrl-0 = <&pinctrl_gsc>;
265		interrupt-parent = <&gpio2>;
266		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
267		interrupt-controller;
268		#interrupt-cells = <1>;
269
270		adc {
271			compatible = "gw,gsc-adc";
272			#address-cells = <1>;
273			#size-cells = <0>;
274
275			channel@6 {
276				gw,mode = <0>;
277				reg = <0x06>;
278				label = "temp";
279			};
280
281			channel@8 {
282				gw,mode = <1>;
283				reg = <0x08>;
284				label = "vdd_bat";
285			};
286
287			channel@82 {
288				gw,mode = <2>;
289				reg = <0x82>;
290				label = "vin";
291				gw,voltage-divider-ohms = <22100 1000>;
292				gw,voltage-offset-microvolt = <700000>;
293			};
294
295			channel@84 {
296				gw,mode = <2>;
297				reg = <0x84>;
298				label = "vin_4p0";
299				gw,voltage-divider-ohms = <10000 10000>;
300			};
301
302			channel@86 {
303				gw,mode = <2>;
304				reg = <0x86>;
305				label = "vdd_3p3";
306				gw,voltage-divider-ohms = <10000 10000>;
307			};
308
309			channel@88 {
310				gw,mode = <2>;
311				reg = <0x88>;
312				label = "vdd_0p9";
313			};
314
315			channel@8c {
316				gw,mode = <2>;
317				reg = <0x8c>;
318				label = "vdd_soc";
319			};
320
321			channel@8e {
322				gw,mode = <2>;
323				reg = <0x8e>;
324				label = "vdd_arm";
325			};
326
327			channel@90 {
328				gw,mode = <2>;
329				reg = <0x90>;
330				label = "vdd_1p8";
331			};
332
333			channel@92 {
334				gw,mode = <2>;
335				reg = <0x92>;
336				label = "vdd_dram";
337			};
338
339			channel@98 {
340				gw,mode = <2>;
341				reg = <0x98>;
342				label = "vdd_1p0";
343			};
344
345			channel@9a {
346				gw,mode = <2>;
347				reg = <0x9a>;
348				label = "vdd_2p5";
349				gw,voltage-divider-ohms = <10000 10000>;
350			};
351
352			channel@a2 {
353				gw,mode = <2>;
354				reg = <0xa2>;
355				label = "vdd_gsc";
356				gw,voltage-divider-ohms = <10000 10000>;
357			};
358		};
359	};
360
361	gpio: gpio@23 {
362		compatible = "nxp,pca9555";
363		reg = <0x23>;
364		gpio-controller;
365		#gpio-cells = <2>;
366		interrupt-parent = <&gsc>;
367		interrupts = <4>;
368	};
369
370	pmic@4b {
371		compatible = "rohm,bd71847";
372		reg = <0x4b>;
373		pinctrl-names = "default";
374		pinctrl-0 = <&pinctrl_pmic>;
375		interrupt-parent = <&gpio3>;
376		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
377		rohm,reset-snvs-powered;
378		#clock-cells = <0>;
379		clocks = <&osc_32k 0>;
380		clock-output-names = "clk-32k-out";
381
382		regulators {
383			/* vdd_soc: 0.805-0.900V (typ=0.8V) */
384			BUCK1 {
385				regulator-name = "buck1";
386				regulator-min-microvolt = <700000>;
387				regulator-max-microvolt = <1300000>;
388				regulator-boot-on;
389				regulator-always-on;
390				regulator-ramp-delay = <1250>;
391			};
392
393			/* vdd_arm: 0.805-1.0V (typ=0.9V) */
394			buck2: BUCK2 {
395				regulator-name = "buck2";
396				regulator-min-microvolt = <700000>;
397				regulator-max-microvolt = <1300000>;
398				regulator-boot-on;
399				regulator-always-on;
400				regulator-ramp-delay = <1250>;
401				rohm,dvs-run-voltage = <1000000>;
402				rohm,dvs-idle-voltage = <900000>;
403			};
404
405			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
406			BUCK3 {
407				regulator-name = "buck3";
408				regulator-min-microvolt = <700000>;
409				regulator-max-microvolt = <1350000>;
410				regulator-boot-on;
411				regulator-always-on;
412			};
413
414			/* vdd_3p3 */
415			BUCK4 {
416				regulator-name = "buck4";
417				regulator-min-microvolt = <3000000>;
418				regulator-max-microvolt = <3300000>;
419				regulator-boot-on;
420				regulator-always-on;
421			};
422
423			/* vdd_1p8 */
424			BUCK5 {
425				regulator-name = "buck5";
426				regulator-min-microvolt = <1605000>;
427				regulator-max-microvolt = <1995000>;
428				regulator-boot-on;
429				regulator-always-on;
430			};
431
432			/* vdd_dram */
433			BUCK6 {
434				regulator-name = "buck6";
435				regulator-min-microvolt = <800000>;
436				regulator-max-microvolt = <1400000>;
437				regulator-boot-on;
438				regulator-always-on;
439			};
440
441			/* nvcc_snvs_1p8 */
442			LDO1 {
443				regulator-name = "ldo1";
444				regulator-min-microvolt = <1600000>;
445				regulator-max-microvolt = <1900000>;
446				regulator-boot-on;
447				regulator-always-on;
448			};
449
450			/* vdd_snvs_0p8 */
451			LDO2 {
452				regulator-name = "ldo2";
453				regulator-min-microvolt = <800000>;
454				regulator-max-microvolt = <900000>;
455				regulator-boot-on;
456				regulator-always-on;
457			};
458
459			/* vdda_1p8 */
460			LDO3 {
461				regulator-name = "ldo3";
462				regulator-min-microvolt = <1800000>;
463				regulator-max-microvolt = <3300000>;
464				regulator-boot-on;
465				regulator-always-on;
466			};
467
468			LDO4 {
469				regulator-name = "ldo4";
470				regulator-min-microvolt = <900000>;
471				regulator-max-microvolt = <1800000>;
472				regulator-boot-on;
473				regulator-always-on;
474			};
475
476			LDO6 {
477				regulator-name = "ldo6";
478				regulator-min-microvolt = <900000>;
479				regulator-max-microvolt = <1800000>;
480				regulator-boot-on;
481				regulator-always-on;
482			};
483		};
484	};
485
486	eeprom@50 {
487		compatible = "atmel,24c02";
488		reg = <0x50>;
489		pagesize = <16>;
490	};
491
492	eeprom@51 {
493		compatible = "atmel,24c02";
494		reg = <0x51>;
495		pagesize = <16>;
496	};
497
498	eeprom@52 {
499		compatible = "atmel,24c02";
500		reg = <0x52>;
501		pagesize = <16>;
502	};
503
504	eeprom@53 {
505		compatible = "atmel,24c02";
506		reg = <0x53>;
507		pagesize = <16>;
508	};
509
510	rtc@68 {
511		compatible = "dallas,ds1672";
512		reg = <0x68>;
513	};
514};
515
516&i2c2 {
517	clock-frequency = <400000>;
518	pinctrl-names = "default";
519	pinctrl-0 = <&pinctrl_i2c2>;
520	status = "okay";
521
522	accelerometer@19 {
523		compatible = "st,lis2de12";
524		pinctrl-names = "default";
525		pinctrl-0 = <&pinctrl_accel>;
526		reg = <0x19>;
527		st,drdy-int-pin = <1>;
528		interrupt-parent = <&gpio1>;
529		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
530		interrupt-names = "INT1";
531	};
532};
533
534/* off-board header */
535&i2c3 {
536	clock-frequency = <400000>;
537	pinctrl-names = "default";
538	pinctrl-0 = <&pinctrl_i2c3>;
539	status = "okay";
540};
541
542/* off-board header */
543&i2c4 {
544	clock-frequency = <400000>;
545	pinctrl-names = "default";
546	pinctrl-0 = <&pinctrl_i2c4>;
547	status = "okay";
548};
549
550/* off-board header */
551&sai3 {
552	pinctrl-names = "default";
553	pinctrl-0 = <&pinctrl_sai3>;
554	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
555	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
556	assigned-clock-rates = <24576000>;
557	status = "okay";
558};
559
560/* RS232/RS485/RS422 selectable */
561&uart1 {
562	pinctrl-names = "default";
563	pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
564	rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
565	cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
566	status = "okay";
567};
568
569/* RS232 console */
570&uart2 {
571	pinctrl-names = "default";
572	pinctrl-0 = <&pinctrl_uart2>;
573	status = "okay";
574};
575
576/* bluetooth HCI */
577&uart3 {
578	pinctrl-names = "default";
579	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
580	rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
581	cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
582	status = "okay";
583
584	bluetooth {
585		compatible = "brcm,bcm4330-bt";
586		shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
587	};
588};
589
590/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
591&uart4 {
592	pinctrl-names = "default";
593	pinctrl-0 = <&pinctrl_uart4>;
594	rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
595	cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
596	dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
597	dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
598	dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
599	status = "okay";
600};
601
602&usbotg1 {
603	dr_mode = "host";
604	vbus-supply = <&reg_usb1_vbus>;
605	disable-over-current;
606	status = "okay";
607};
608
609&usbotg2 {
610	dr_mode = "host";
611	disable-over-current;
612	status = "okay";
613};
614
615/* SDIO WiFi */
616&usdhc2 {
617	pinctrl-names = "default";
618	pinctrl-0 = <&pinctrl_usdhc2>;
619	bus-width = <4>;
620	non-removable;
621	vmmc-supply = <&reg_wifi>;
622	status = "okay";
623};
624
625/* eMMC */
626&usdhc3 {
627	pinctrl-names = "default", "state_100mhz", "state_200mhz";
628	pinctrl-0 = <&pinctrl_usdhc3>;
629	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
630	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
631	bus-width = <8>;
632	non-removable;
633	status = "okay";
634};
635
636&wdog1 {
637	pinctrl-names = "default";
638	pinctrl-0 = <&pinctrl_wdog>;
639	fsl,ext-reset-output;
640	status = "okay";
641};
642
643&iomuxc {
644	pinctrl-names = "default";
645	pinctrl-0 = <&pinctrl_hog>;
646
647	pinctrl_hog: hoggrp {
648		fsl,pins = <
649			MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1	0x40000159 /* M2_GDIS# */
650			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x40000041 /* M2_RST# */
651			MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7	0x40000119 /* M2_OFF# */
652			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x40000159 /* M2_WDIS# */
653			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14	0x40000041 /* AMP GPIO1 */
654			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12	0x40000041 /* AMP GPIO2 */
655			MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11	0x40000041 /* AMP GPIO3 */
656			MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20	0x40000041 /* AMP_GPIO4 */
657			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041 /* APP GPIO1 */
658			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* APP GPIO2 */
659			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x40000041 /* UART2_EN# */
660			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x40000041 /* MIPI_GPIO1 */
661			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x40000041 /* MIPI_GPIO2 */
662			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000041 /* MIPI_GPIO3/PWM2 */
663			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* MIPI_GPIO4/PWM3 */
664		>;
665	};
666
667	pinctrl_accel: accelgrp {
668		fsl,pins = <
669			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x159
670		>;
671	};
672
673	pinctrl_fec1: fec1grp {
674		fsl,pins = <
675			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
676			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
677			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
678			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
679			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
680			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
681			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
682			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
683			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
684			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
685			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
686			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
687			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
688			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
689			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19 /* RST# */
690			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19 /* IRQ# */
691			MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN	0x141
692			MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT	0x141
693		>;
694	};
695
696	pinctrl_gsc: gscgrp {
697		fsl,pins = <
698			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x40
699		>;
700	};
701
702	pinctrl_i2c1: i2c1grp {
703		fsl,pins = <
704			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
705			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
706		>;
707	};
708
709	pinctrl_i2c2: i2c2grp {
710		fsl,pins = <
711			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
712			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
713		>;
714	};
715
716	pinctrl_i2c3: i2c3grp {
717		fsl,pins = <
718			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
719			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
720		>;
721	};
722
723	pinctrl_i2c4: i2c4grp {
724		fsl,pins = <
725			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
726			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
727		>;
728	};
729
730	pinctrl_gpio_leds: gpioledgrp {
731		fsl,pins = <
732			MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21	0x19
733			MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23	0x19
734			MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22	0x19
735			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20	0x19
736			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x19
737		>;
738	};
739
740	pinctrl_pmic: pmicgrp {
741		fsl,pins = <
742			MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8	0x41
743		>;
744	};
745
746	pinctrl_pps: ppsgrp {
747		fsl,pins = <
748			MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x141 /* PPS */
749		>;
750	};
751
752	pinctrl_reg_wl: regwlgrp {
753		fsl,pins = <
754			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41 /* WLAN_WLON */
755		>;
756	};
757
758	pinctrl_reg_usb1: regusb1grp {
759		fsl,pins = <
760			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7	0x41
761		>;
762	};
763
764	pinctrl_sai3: sai3grp {
765		fsl,pins = <
766			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK	0xd6
767			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
768			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK	0xd6
769			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0	0xd6
770			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC	0xd6
771		>;
772	};
773
774	pinctrl_spi1: spi1grp {
775		fsl,pins = <
776			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82
777			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82
778			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82
779			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x40
780			MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3	0x140 /* CAN_IRQ# */
781		>;
782	};
783
784	pinctrl_spi2: spi2grp {
785		fsl,pins = <
786			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x82
787			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x82
788			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x82
789			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x40 /* SS0 */
790		>;
791	};
792
793	pinctrl_uart1: uart1grp {
794		fsl,pins = <
795			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
796			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
797			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10	0x140 /* RTS */
798			MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24	0x140 /* CTS */
799		>;
800	};
801
802	pinctrl_uart1_gpio: uart1gpiogrp {
803		fsl,pins = <
804			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26	0x40000110 /* HALF */
805			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25	0x40000110 /* TERM */
806			MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23	0x40000110 /* RS485 */
807		>;
808	};
809
810	pinctrl_uart2: uart2grp {
811		fsl,pins = <
812			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
813			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
814		>;
815	};
816
817	pinctrl_uart3_gpio: uart3_gpiogrp {
818		fsl,pins = <
819			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41 /* BT_EN# */
820		>;
821	};
822
823	pinctrl_uart3: uart3grp {
824		fsl,pins = <
825			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
826			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
827			MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0		0x140 /* CTS */
828			MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1		0x140 /* RTS */
829		>;
830	};
831
832	pinctrl_uart4: uart4grp {
833		fsl,pins = <
834			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
835			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
836			MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1		0x140 /* CTS */
837			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x140 /* RTS */
838			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3	0x140 /* DTR */
839			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4	0x140 /* DSR */
840			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x140 /* DCD */
841			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x140 /* RI */
842			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x140 /* GNSS_PPS */
843			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x141 /* GNSS_GASP */
844		>;
845	};
846
847	pinctrl_usdhc2: usdhc2grp {
848		fsl,pins = <
849			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
850			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
851			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
852			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
853			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
854			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
855		>;
856	};
857
858	pinctrl_usdhc3: usdhc3grp {
859		fsl,pins = <
860			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
861			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
862			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
863			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
864			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
865			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
866			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
867			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
868			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
869			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
870			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
871		>;
872	};
873
874	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
875		fsl,pins = <
876			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
877			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
878			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
879			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
880			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
881			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
882			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
883			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
884			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
885			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
886			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
887		>;
888	};
889
890	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
891		fsl,pins = <
892			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
893			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
894			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
895			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
896			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
897			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
898			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
899			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
900			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
901			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
902			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
903		>;
904	};
905
906	pinctrl_wdog: wdoggrp {
907		fsl,pins = <
908			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
909		>;
910	};
911};
912