1*4c33cb31SAndrew Davis// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4c33cb31SAndrew Davis/* 3*4c33cb31SAndrew Davis * Copyright 2022 Gateworks Corporation 4*4c33cb31SAndrew Davis * 5*4c33cb31SAndrew Davis * GW72xx RS485 HD: 6*4c33cb31SAndrew Davis * - GPIO1_0 rs485_term selects on-chip termination 7*4c33cb31SAndrew Davis * - GPIO4_0 rs485_en needs to be driven high (active) 8*4c33cb31SAndrew Davis * - GPIO4_2 rs485_hd needs to be driven high (active) 9*4c33cb31SAndrew Davis * - UART4_TX is DE for RS485 transmitter 10*4c33cb31SAndrew Davis * - RS485_EN needs to be pulled high 11*4c33cb31SAndrew Davis * - RS485_HALF needs to be pulled high 12*4c33cb31SAndrew Davis */ 13*4c33cb31SAndrew Davis 14*4c33cb31SAndrew Davis#include <dt-bindings/gpio/gpio.h> 15*4c33cb31SAndrew Davis 16*4c33cb31SAndrew Davis#include "imx8mm-pinfunc.h" 17*4c33cb31SAndrew Davis 18*4c33cb31SAndrew Davis/dts-v1/; 19*4c33cb31SAndrew Davis/plugin/; 20*4c33cb31SAndrew Davis 21*4c33cb31SAndrew Davis&{/} { 22*4c33cb31SAndrew Davis compatible = "gw,imx8mm-gw72xx-0x"; 23*4c33cb31SAndrew Davis}; 24*4c33cb31SAndrew Davis 25*4c33cb31SAndrew Davis&gpio4 { 26*4c33cb31SAndrew Davis rs485_en { 27*4c33cb31SAndrew Davis gpio-hog; 28*4c33cb31SAndrew Davis gpios = <0 GPIO_ACTIVE_HIGH>; 29*4c33cb31SAndrew Davis output-high; 30*4c33cb31SAndrew Davis line-name = "rs485_en"; 31*4c33cb31SAndrew Davis }; 32*4c33cb31SAndrew Davis 33*4c33cb31SAndrew Davis rs485_hd { 34*4c33cb31SAndrew Davis gpio-hog; 35*4c33cb31SAndrew Davis gpios = <2 GPIO_ACTIVE_HIGH>; 36*4c33cb31SAndrew Davis output-high; 37*4c33cb31SAndrew Davis line-name = "rs485_hd"; 38*4c33cb31SAndrew Davis }; 39*4c33cb31SAndrew Davis}; 40*4c33cb31SAndrew Davis 41*4c33cb31SAndrew Davis&uart2 { 42*4c33cb31SAndrew Davis pinctrl-names = "default"; 43*4c33cb31SAndrew Davis pinctrl-0 = <&pinctrl_uart2>; 44*4c33cb31SAndrew Davis rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; 45*4c33cb31SAndrew Davis linux,rs485-enabled-at-boot-time; 46*4c33cb31SAndrew Davis status = "okay"; 47*4c33cb31SAndrew Davis}; 48*4c33cb31SAndrew Davis 49*4c33cb31SAndrew Davis&uart4 { 50*4c33cb31SAndrew Davis status = "disabled"; 51*4c33cb31SAndrew Davis}; 52*4c33cb31SAndrew Davis 53*4c33cb31SAndrew Davis&iomuxc { 54*4c33cb31SAndrew Davis pinctrl_uart2: uart2grp { 55*4c33cb31SAndrew Davis fsl,pins = < 56*4c33cb31SAndrew Davis MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 57*4c33cb31SAndrew Davis MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 58*4c33cb31SAndrew Davis MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 59*4c33cb31SAndrew Davis >; 60*4c33cb31SAndrew Davis }; 61*4c33cb31SAndrew Davis}; 62