1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/leds/common.h> 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9 10/ { 11 aliases { 12 usb0 = &usbotg1; 13 usb1 = &usbotg2; 14 }; 15 16 led-controller { 17 compatible = "gpio-leds"; 18 pinctrl-names = "default"; 19 pinctrl-0 = <&pinctrl_gpio_leds>; 20 21 led-0 { 22 function = LED_FUNCTION_STATUS; 23 color = <LED_COLOR_ID_GREEN>; 24 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 25 default-state = "on"; 26 linux,default-trigger = "heartbeat"; 27 }; 28 29 led-1 { 30 function = LED_FUNCTION_STATUS; 31 color = <LED_COLOR_ID_RED>; 32 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 33 default-state = "off"; 34 }; 35 }; 36 37 pcie0_refclk: pcie0-refclk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <100000000>; 41 }; 42 43 pps { 44 compatible = "pps-gpio"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_pps>; 47 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; 48 status = "okay"; 49 }; 50}; 51 52/* off-board header */ 53&ecspi2 { 54 pinctrl-names = "default"; 55 pinctrl-0 = <&pinctrl_spi2>; 56 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 57 status = "okay"; 58}; 59 60&gpio1 { 61 gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0", 62 "", "dio1", "", "", "", "", "", "", 63 "", "", "", "", "", "", "", "", 64 "", "", "", "", "", "", "", ""; 65}; 66 67&gpio4 { 68 gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#", 69 "", "", "", "", "", "", "", "", 70 "", "", "", "", "", "", "", "", 71 "", "", "", "", "", "", "", ""; 72}; 73 74&i2c2 { 75 clock-frequency = <400000>; 76 pinctrl-names = "default"; 77 pinctrl-0 = <&pinctrl_i2c2>; 78 status = "okay"; 79 80 accelerometer@19 { 81 pinctrl-names = "default"; 82 pinctrl-0 = <&pinctrl_accel>; 83 compatible = "st,lis2de12"; 84 reg = <0x19>; 85 st,drdy-int-pin = <1>; 86 interrupt-parent = <&gpio4>; 87 interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 88 interrupt-names = "INT1"; 89 }; 90}; 91 92/* off-board header */ 93&i2c3 { 94 clock-frequency = <400000>; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_i2c3>; 97 status = "okay"; 98}; 99 100&pcie_phy { 101 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 102 fsl,clkreq-unsupported; 103 clocks = <&pcie0_refclk>; 104 clock-names = "ref"; 105 status = "okay"; 106}; 107 108&pcie0 { 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_pcie0>; 111 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; 112 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, 113 <&clk IMX8MM_CLK_PCIE1_AUX>; 114 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 115 <&clk IMX8MM_CLK_PCIE1_CTRL>; 116 assigned-clock-rates = <10000000>, <250000000>; 117 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 118 <&clk IMX8MM_SYS_PLL2_250M>; 119 status = "okay"; 120}; 121 122/* GPS */ 123&uart1 { 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_uart1>; 126 status = "okay"; 127}; 128 129/* off-board header */ 130&uart3 { 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_uart3>; 133 status = "okay"; 134}; 135 136&usbotg1 { 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pinctrl_usbotg1>; 139 dr_mode = "otg"; 140 over-current-active-low; 141 status = "okay"; 142}; 143 144&usbotg2 { 145 dr_mode = "host"; 146 disable-over-current; 147 status = "okay"; 148}; 149 150&iomuxc { 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_hog>; 153 154 pinctrl_hog: hoggrp { 155 fsl,pins = < 156 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ 157 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ 158 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ 159 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ 160 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ 161 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */ 162 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */ 163 >; 164 }; 165 166 pinctrl_accel: accelgrp { 167 fsl,pins = < 168 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 169 >; 170 }; 171 172 pinctrl_gpio_leds: gpioledgrp { 173 fsl,pins = < 174 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 175 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 176 >; 177 }; 178 179 pinctrl_i2c3: i2c3grp { 180 fsl,pins = < 181 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 182 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 183 >; 184 }; 185 186 pinctrl_pcie0: pcie0grp { 187 fsl,pins = < 188 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 189 >; 190 }; 191 192 pinctrl_pps: ppsgrp { 193 fsl,pins = < 194 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 195 >; 196 }; 197 198 pinctrl_spi2: spi2grp { 199 fsl,pins = < 200 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 201 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 202 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 203 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 204 >; 205 }; 206 207 pinctrl_uart1: uart1grp { 208 fsl,pins = < 209 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 210 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 211 >; 212 }; 213 214 pinctrl_uart3: uart3grp { 215 fsl,pins = < 216 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 217 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 218 >; 219 }; 220 221 pinctrl_usbotg1: usbotg1grp { 222 fsl,pins = < 223 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141 224 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 225 >; 226 }; 227}; 228