1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/net/ti-dp83867.h>
9
10/ {
11	memory@40000000 {
12		device_type = "memory";
13		reg = <0x0 0x40000000 0 0x80000000>;
14	};
15
16	gpio-keys {
17		compatible = "gpio-keys";
18
19		key-user-pb {
20			label = "user_pb";
21			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
22			linux,code = <BTN_0>;
23		};
24
25		key-user-pb1x {
26			label = "user_pb1x";
27			linux,code = <BTN_1>;
28			interrupt-parent = <&gsc>;
29			interrupts = <0>;
30		};
31
32		key-erased {
33			label = "key_erased";
34			linux,code = <BTN_2>;
35			interrupt-parent = <&gsc>;
36			interrupts = <1>;
37		};
38
39		key-eeprom-wp {
40			label = "eeprom_wp";
41			linux,code = <BTN_3>;
42			interrupt-parent = <&gsc>;
43			interrupts = <2>;
44		};
45
46		key-tamper {
47			label = "tamper";
48			linux,code = <BTN_4>;
49			interrupt-parent = <&gsc>;
50			interrupts = <5>;
51		};
52
53		switch-hold {
54			label = "switch_hold";
55			linux,code = <BTN_5>;
56			interrupt-parent = <&gsc>;
57			interrupts = <7>;
58		};
59	};
60};
61
62&A53_0 {
63	cpu-supply = <&buck3_reg>;
64};
65
66&A53_1 {
67	cpu-supply = <&buck3_reg>;
68};
69
70&A53_2 {
71	cpu-supply = <&buck3_reg>;
72};
73
74&A53_3 {
75	cpu-supply = <&buck3_reg>;
76};
77
78&ddrc {
79	operating-points-v2 = <&ddrc_opp_table>;
80
81	ddrc_opp_table: opp-table {
82		compatible = "operating-points-v2";
83
84		opp-25000000 {
85			opp-hz = /bits/ 64 <25000000>;
86		};
87
88		opp-100000000 {
89			opp-hz = /bits/ 64 <100000000>;
90		};
91
92		opp-750000000 {
93			opp-hz = /bits/ 64 <750000000>;
94		};
95	};
96};
97
98&fec1 {
99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_fec1>;
101	phy-mode = "rgmii-id";
102	phy-handle = <&ethphy0>;
103	status = "okay";
104
105	mdio {
106		#address-cells = <1>;
107		#size-cells = <0>;
108
109		ethphy0: ethernet-phy@0 {
110			compatible = "ethernet-phy-ieee802.3-c22";
111			reg = <0>;
112			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
113			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
114			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
115			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
116		};
117	};
118};
119
120&i2c1 {
121	clock-frequency = <100000>;
122	pinctrl-names = "default", "gpio";
123	pinctrl-0 = <&pinctrl_i2c1>;
124	pinctrl-1 = <&pinctrl_i2c1_gpio>;
125	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
126	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
127	status = "okay";
128
129	gsc: gsc@20 {
130		compatible = "gw,gsc";
131		reg = <0x20>;
132		pinctrl-0 = <&pinctrl_gsc>;
133		interrupt-parent = <&gpio2>;
134		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
135		interrupt-controller;
136		#interrupt-cells = <1>;
137		#address-cells = <1>;
138		#size-cells = <0>;
139
140		adc {
141			compatible = "gw,gsc-adc";
142			#address-cells = <1>;
143			#size-cells = <0>;
144
145			channel@6 {
146				gw,mode = <0>;
147				reg = <0x06>;
148				label = "temp";
149			};
150
151			channel@8 {
152				gw,mode = <1>;
153				reg = <0x08>;
154				label = "vdd_bat";
155			};
156
157			channel@16 {
158				gw,mode = <4>;
159				reg = <0x16>;
160				label = "fan_tach";
161			};
162
163			channel@82 {
164				gw,mode = <2>;
165				reg = <0x82>;
166				label = "vdd_vin";
167				gw,voltage-divider-ohms = <22100 1000>;
168			};
169
170			channel@84 {
171				gw,mode = <2>;
172				reg = <0x84>;
173				label = "vdd_adc1";
174				gw,voltage-divider-ohms = <10000 10000>;
175			};
176
177			channel@86 {
178				gw,mode = <2>;
179				reg = <0x86>;
180				label = "vdd_adc2";
181				gw,voltage-divider-ohms = <10000 10000>;
182			};
183
184			channel@88 {
185				gw,mode = <2>;
186				reg = <0x88>;
187				label = "vdd_dram";
188			};
189
190			channel@8c {
191				gw,mode = <2>;
192				reg = <0x8c>;
193				label = "vdd_1p2";
194			};
195
196			channel@8e {
197				gw,mode = <2>;
198				reg = <0x8e>;
199				label = "vdd_1p0";
200			};
201
202			channel@90 {
203				gw,mode = <2>;
204				reg = <0x90>;
205				label = "vdd_2p5";
206				gw,voltage-divider-ohms = <10000 10000>;
207			};
208
209			channel@92 {
210				gw,mode = <2>;
211				reg = <0x92>;
212				label = "vdd_3p3";
213				gw,voltage-divider-ohms = <10000 10000>;
214			};
215
216			channel@98 {
217				gw,mode = <2>;
218				reg = <0x98>;
219				label = "vdd_0p95";
220			};
221
222			channel@9a {
223				gw,mode = <2>;
224				reg = <0x9a>;
225				label = "vdd_1p8";
226			};
227
228			channel@a2 {
229				gw,mode = <2>;
230				reg = <0xa2>;
231				label = "vdd_gsc";
232				gw,voltage-divider-ohms = <10000 10000>;
233			};
234		};
235
236		fan-controller@0 {
237			#address-cells = <1>;
238			#size-cells = <0>;
239			compatible = "gw,gsc-fan";
240			reg = <0x0a>;
241		};
242	};
243
244	gpio: gpio@23 {
245		compatible = "nxp,pca9555";
246		reg = <0x23>;
247		gpio-controller;
248		#gpio-cells = <2>;
249		interrupt-parent = <&gsc>;
250		interrupts = <4>;
251	};
252
253	eeprom@50 {
254		compatible = "atmel,24c02";
255		reg = <0x50>;
256		pagesize = <16>;
257	};
258
259	eeprom@51 {
260		compatible = "atmel,24c02";
261		reg = <0x51>;
262		pagesize = <16>;
263	};
264
265	eeprom@52 {
266		compatible = "atmel,24c02";
267		reg = <0x52>;
268		pagesize = <16>;
269	};
270
271	eeprom@53 {
272		compatible = "atmel,24c02";
273		reg = <0x53>;
274		pagesize = <16>;
275	};
276
277	rtc@68 {
278		compatible = "dallas,ds1672";
279		reg = <0x68>;
280	};
281
282	pmic@69 {
283		compatible = "mps,mp5416";
284		reg = <0x69>;
285
286		regulators {
287			/* vdd_0p95: DRAM/GPU/VPU */
288			buck1 {
289				regulator-name = "buck1";
290				regulator-min-microvolt = <800000>;
291				regulator-max-microvolt = <1000000>;
292				regulator-min-microamp = <3800000>;
293				regulator-max-microamp = <6800000>;
294				regulator-boot-on;
295				regulator-always-on;
296			};
297
298			/* vdd_soc */
299			buck2 {
300				regulator-name = "buck2";
301				regulator-min-microvolt = <800000>;
302				regulator-max-microvolt = <900000>;
303				regulator-min-microamp = <2200000>;
304				regulator-max-microamp = <5200000>;
305				regulator-boot-on;
306				regulator-always-on;
307			};
308
309			/* vdd_arm */
310			buck3_reg: buck3 {
311				regulator-name = "buck3";
312				regulator-min-microvolt = <800000>;
313				regulator-max-microvolt = <1000000>;
314				regulator-min-microamp = <3800000>;
315				regulator-max-microamp = <6800000>;
316				regulator-always-on;
317			};
318
319			/* vdd_1p8 */
320			buck4 {
321				regulator-name = "buck4";
322				regulator-min-microvolt = <1800000>;
323				regulator-max-microvolt = <1800000>;
324				regulator-min-microamp = <2200000>;
325				regulator-max-microamp = <5200000>;
326				regulator-boot-on;
327				regulator-always-on;
328			};
329
330			/* nvcc_snvs_1p8 */
331			ldo1 {
332				regulator-name = "ldo1";
333				regulator-min-microvolt = <1800000>;
334				regulator-max-microvolt = <1800000>;
335				regulator-boot-on;
336				regulator-always-on;
337			};
338
339			/* vdd_snvs_0p8 */
340			ldo2 {
341				regulator-name = "ldo2";
342				regulator-min-microvolt = <800000>;
343				regulator-max-microvolt = <800000>;
344				regulator-boot-on;
345				regulator-always-on;
346			};
347
348			/* vdd_0p9 */
349			ldo3 {
350				regulator-name = "ldo3";
351				regulator-min-microvolt = <900000>;
352				regulator-max-microvolt = <900000>;
353				regulator-boot-on;
354				regulator-always-on;
355			};
356
357			/* vdd_1p8 */
358			ldo4 {
359				regulator-name = "ldo4";
360				regulator-min-microvolt = <1800000>;
361				regulator-max-microvolt = <1800000>;
362				regulator-boot-on;
363				regulator-always-on;
364			};
365		};
366	};
367};
368
369&i2c2 {
370	clock-frequency = <400000>;
371	pinctrl-names = "default", "gpio";
372	pinctrl-0 = <&pinctrl_i2c2>;
373	pinctrl-1 = <&pinctrl_i2c2_gpio>;
374	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
375	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
376	status = "okay";
377
378	eeprom@52 {
379		compatible = "atmel,24c32";
380		reg = <0x52>;
381		pagesize = <32>;
382	};
383};
384
385/* console */
386&uart2 {
387	pinctrl-names = "default";
388	pinctrl-0 = <&pinctrl_uart2>;
389	status = "okay";
390};
391
392/* eMMC */
393&usdhc3 {
394	pinctrl-names = "default", "state_100mhz", "state_200mhz";
395	pinctrl-0 = <&pinctrl_usdhc3>;
396	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
397	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
398	bus-width = <8>;
399	non-removable;
400	status = "okay";
401};
402
403&wdog1 {
404	pinctrl-names = "default";
405	pinctrl-0 = <&pinctrl_wdog>;
406	fsl,ext-reset-output;
407	status = "okay";
408};
409
410&iomuxc {
411	pinctrl_fec1: fec1grp {
412		fsl,pins = <
413			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
414			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
415			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
416			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
417			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
418			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
419			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
420			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
421			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
422			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
423			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
424			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
425			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
426			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
427			MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0			0x19
428		>;
429	};
430
431	pinctrl_gsc: gscgrp {
432		fsl,pins = <
433			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x159
434		>;
435	};
436
437	pinctrl_i2c1: i2c1grp {
438		fsl,pins = <
439			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
440			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
441		>;
442	};
443
444	pinctrl_i2c1_gpio: i2c1gpiogrp {
445		fsl,pins = <
446			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
447			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
448		>;
449	};
450
451	pinctrl_i2c2: i2c2grp {
452		fsl,pins = <
453			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
454			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
455		>;
456	};
457
458	pinctrl_i2c2_gpio: i2c2gpiogrp {
459		fsl,pins = <
460			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3
461			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3
462		>;
463	};
464
465	pinctrl_uart2: uart2grp {
466		fsl,pins = <
467			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
468			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
469		>;
470	};
471
472	pinctrl_usdhc3: usdhc3grp {
473		fsl,pins = <
474			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
475			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
476			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
477			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
478			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
479			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
480			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
481			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
482			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
483			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
484			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
485		>;
486	};
487
488	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
489		fsl,pins = <
490			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
491			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
492			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
493			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
494			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
495			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
496			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
497			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
498			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
499			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
500			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
501		>;
502	};
503
504	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
505		fsl,pins = <
506			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
507			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
508			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
509			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
510			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
511			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
512			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
513			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
514			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
515			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
516			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
517		>;
518	};
519
520	pinctrl_wdog: wdoggrp {
521		fsl,pins = <
522			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
523		>;
524	};
525};
526