1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org> 5 */ 6 7#include "imx8mm.dtsi" 8 9/ { 10 model = "Variscite VAR-SOM-MX8MM module"; 11 compatible = "variscite,var-som-mx8mm", "fsl,imx8mm"; 12 13 chosen { 14 stdout-path = &uart4; 15 }; 16 17 memory@40000000 { 18 device_type = "memory"; 19 reg = <0x0 0x40000000 0 0x80000000>; 20 }; 21 22 reg_eth_phy: regulator-eth-phy { 23 compatible = "regulator-fixed"; 24 pinctrl-names = "default"; 25 pinctrl-0 = <&pinctrl_reg_eth_phy>; 26 regulator-name = "eth_phy_pwr"; 27 regulator-min-microvolt = <3300000>; 28 regulator-max-microvolt = <3300000>; 29 gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; 30 enable-active-high; 31 }; 32}; 33 34&A53_0 { 35 cpu-supply = <&buck2_reg>; 36}; 37 38&A53_1 { 39 cpu-supply = <&buck2_reg>; 40}; 41 42&A53_2 { 43 cpu-supply = <&buck2_reg>; 44}; 45 46&A53_3 { 47 cpu-supply = <&buck2_reg>; 48}; 49 50&ddrc { 51 operating-points-v2 = <&ddrc_opp_table>; 52 53 ddrc_opp_table: opp-table { 54 compatible = "operating-points-v2"; 55 56 opp-25M { 57 opp-hz = /bits/ 64 <25000000>; 58 }; 59 60 opp-100M { 61 opp-hz = /bits/ 64 <100000000>; 62 }; 63 64 opp-750M { 65 opp-hz = /bits/ 64 <750000000>; 66 }; 67 }; 68}; 69 70&ecspi1 { 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_ecspi1>; 73 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, 74 <&gpio1 0 GPIO_ACTIVE_LOW>; 75 /delete-property/ dmas; 76 /delete-property/ dma-names; 77 status = "okay"; 78 79 /* Resistive touch controller */ 80 touchscreen@0 { 81 reg = <0>; 82 compatible = "ti,ads7846"; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&pinctrl_restouch>; 85 interrupt-parent = <&gpio1>; 86 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 87 88 spi-max-frequency = <1500000>; 89 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; 90 91 ti,x-min = /bits/ 16 <125>; 92 touchscreen-size-x = /bits/ 16 <4008>; 93 ti,y-min = /bits/ 16 <282>; 94 touchscreen-size-y = /bits/ 16 <3864>; 95 ti,x-plate-ohms = /bits/ 16 <180>; 96 touchscreen-max-pressure = /bits/ 16 <255>; 97 touchscreen-average-samples = /bits/ 16 <10>; 98 ti,debounce-tol = /bits/ 16 <3>; 99 ti,debounce-rep = /bits/ 16 <1>; 100 ti,settle-delay-usec = /bits/ 16 <150>; 101 ti,keep-vref-on; 102 wakeup-source; 103 }; 104}; 105 106&fec1 { 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_fec1>; 109 phy-mode = "rgmii"; 110 phy-handle = <ðphy>; 111 phy-supply = <®_eth_phy>; 112 fsl,magic-packet; 113 status = "okay"; 114 115 mdio { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 ethphy: ethernet-phy@4 { 120 compatible = "ethernet-phy-ieee802.3-c22"; 121 reg = <4>; 122 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 123 reset-assert-us = <10000>; 124 reset-deassert-us = <10000>; 125 }; 126 }; 127}; 128 129&i2c1 { 130 clock-frequency = <400000>; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_i2c1>; 133 status = "okay"; 134 135 pmic@4b { 136 compatible = "rohm,bd71847"; 137 reg = <0x4b>; 138 pinctrl-0 = <&pinctrl_pmic>; 139 interrupt-parent = <&gpio2>; 140 /* 141 * The interrupt is not correct. It should be level low, 142 * however with internal pull up this causes IRQ storm. 143 */ 144 interrupts = <8 IRQ_TYPE_EDGE_RISING>; 145 rohm,reset-snvs-powered; 146 147 #clock-cells = <0>; 148 clocks = <&osc_32k 0>; 149 clock-output-names = "clk-32k-out"; 150 151 regulators { 152 buck1_reg: BUCK1 { 153 regulator-name = "buck1"; 154 regulator-min-microvolt = <700000>; 155 regulator-max-microvolt = <1300000>; 156 regulator-boot-on; 157 regulator-always-on; 158 regulator-ramp-delay = <1250>; 159 }; 160 161 buck2_reg: BUCK2 { 162 regulator-name = "buck2"; 163 regulator-min-microvolt = <700000>; 164 regulator-max-microvolt = <1300000>; 165 regulator-boot-on; 166 regulator-always-on; 167 regulator-ramp-delay = <1250>; 168 rohm,dvs-run-voltage = <1000000>; 169 rohm,dvs-idle-voltage = <900000>; 170 }; 171 172 buck3_reg: BUCK3 { 173 regulator-name = "buck3"; 174 regulator-min-microvolt = <700000>; 175 regulator-max-microvolt = <1350000>; 176 regulator-boot-on; 177 regulator-always-on; 178 }; 179 180 buck4_reg: BUCK4 { 181 regulator-name = "buck4"; 182 regulator-min-microvolt = <3000000>; 183 regulator-max-microvolt = <3300000>; 184 regulator-boot-on; 185 regulator-always-on; 186 }; 187 188 buck5_reg: BUCK5 { 189 regulator-name = "buck5"; 190 regulator-min-microvolt = <1605000>; 191 regulator-max-microvolt = <1995000>; 192 regulator-boot-on; 193 regulator-always-on; 194 }; 195 196 buck6_reg: BUCK6 { 197 regulator-name = "buck6"; 198 regulator-min-microvolt = <800000>; 199 regulator-max-microvolt = <1400000>; 200 regulator-boot-on; 201 regulator-always-on; 202 }; 203 204 ldo1_reg: LDO1 { 205 regulator-name = "ldo1"; 206 regulator-min-microvolt = <1600000>; 207 regulator-max-microvolt = <1900000>; 208 regulator-boot-on; 209 regulator-always-on; 210 }; 211 212 ldo2_reg: LDO2 { 213 regulator-name = "ldo2"; 214 regulator-min-microvolt = <800000>; 215 regulator-max-microvolt = <900000>; 216 regulator-boot-on; 217 regulator-always-on; 218 }; 219 220 ldo3_reg: LDO3 { 221 regulator-name = "ldo3"; 222 regulator-min-microvolt = <1800000>; 223 regulator-max-microvolt = <3300000>; 224 regulator-boot-on; 225 regulator-always-on; 226 }; 227 228 ldo4_reg: LDO4 { 229 regulator-name = "ldo4"; 230 regulator-min-microvolt = <900000>; 231 regulator-max-microvolt = <1800000>; 232 regulator-boot-on; 233 regulator-always-on; 234 }; 235 236 ldo5_reg: LDO5 { 237 regulator-compatible = "ldo5"; 238 regulator-min-microvolt = <1800000>; 239 regulator-max-microvolt = <1800000>; 240 regulator-always-on; 241 }; 242 243 ldo6_reg: LDO6 { 244 regulator-name = "ldo6"; 245 regulator-min-microvolt = <900000>; 246 regulator-max-microvolt = <1800000>; 247 regulator-boot-on; 248 regulator-always-on; 249 }; 250 }; 251 }; 252}; 253 254&i2c3 { 255 clock-frequency = <400000>; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_i2c3>; 258 status = "okay"; 259 260 /* TODO: configure audio, as of now just put a placeholder */ 261 wm8904: codec@1a { 262 compatible = "wlf,wm8904"; 263 reg = <0x1a>; 264 status = "disabled"; 265 }; 266}; 267 268&snvs_pwrkey { 269 status = "okay"; 270}; 271 272/* Bluetooth */ 273&uart2 { 274 pinctrl-names = "default"; 275 pinctrl-0 = <&pinctrl_uart2>; 276 assigned-clocks = <&clk IMX8MM_CLK_UART2>; 277 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 278 uart-has-rtscts; 279 status = "okay"; 280}; 281 282/* Console */ 283&uart4 { 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_uart4>; 286 status = "okay"; 287}; 288 289&usbotg1 { 290 dr_mode = "otg"; 291 usb-role-switch; 292 status = "okay"; 293}; 294 295&usbotg2 { 296 dr_mode = "otg"; 297 usb-role-switch; 298 status = "okay"; 299}; 300 301/* WIFI */ 302&usdhc1 { 303 #address-cells = <1>; 304 #size-cells = <0>; 305 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 306 pinctrl-0 = <&pinctrl_usdhc1>; 307 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 308 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 309 bus-width = <4>; 310 non-removable; 311 keep-power-in-suspend; 312 status = "okay"; 313 314 brcmf: bcrmf@1 { 315 reg = <1>; 316 compatible = "brcm,bcm4329-fmac"; 317 }; 318}; 319 320/* SD */ 321&usdhc2 { 322 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 323 assigned-clock-rates = <200000000>; 324 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 325 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 326 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 327 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 328 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 329 bus-width = <4>; 330 vmmc-supply = <®_usdhc2_vmmc>; 331 status = "okay"; 332}; 333 334/* eMMC */ 335&usdhc3 { 336 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 337 assigned-clock-rates = <400000000>; 338 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 339 pinctrl-0 = <&pinctrl_usdhc3>; 340 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 341 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 342 bus-width = <8>; 343 non-removable; 344 status = "okay"; 345}; 346 347&wdog1 { 348 pinctrl-names = "default"; 349 pinctrl-0 = <&pinctrl_wdog>; 350 fsl,ext-reset-output; 351 status = "okay"; 352}; 353 354&iomuxc { 355 pinctrl_ecspi1: ecspi1grp { 356 fsl,pins = < 357 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 358 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 359 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 360 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13 361 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13 362 >; 363 }; 364 365 pinctrl_fec1: fec1grp { 366 fsl,pins = < 367 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 368 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 369 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 370 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 371 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 372 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 373 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 374 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 375 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 376 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 377 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 378 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 379 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 380 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 381 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 382 >; 383 }; 384 385 pinctrl_i2c1: i2c1grp { 386 fsl,pins = < 387 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 388 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 389 >; 390 }; 391 392 pinctrl_i2c3: i2c3grp { 393 fsl,pins = < 394 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 395 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 396 >; 397 }; 398 399 pinctrl_pmic: pmicirqgrp { 400 fsl,pins = < 401 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x41 402 >; 403 }; 404 405 pinctrl_reg_eth_phy: regethphygrp { 406 fsl,pins = < 407 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 408 >; 409 }; 410 411 pinctrl_restouch: restouchgrp { 412 fsl,pins = < 413 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 414 >; 415 }; 416 417 pinctrl_uart2: uart2grp { 418 fsl,pins = < 419 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 420 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 421 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 422 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 423 >; 424 }; 425 426 pinctrl_uart4: uart4grp { 427 fsl,pins = < 428 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 429 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 430 >; 431 }; 432 433 pinctrl_usdhc1: usdhc1grp { 434 fsl,pins = < 435 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 436 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 437 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 438 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 439 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 440 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 441 >; 442 }; 443 444 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 445 fsl,pins = < 446 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 447 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 448 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 449 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 450 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 451 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 452 >; 453 }; 454 455 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 456 fsl,pins = < 457 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 458 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 459 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 460 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 461 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 462 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 463 >; 464 }; 465 466 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 467 fsl,pins = < 468 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1 469 >; 470 }; 471 472 pinctrl_usdhc2: usdhc2grp { 473 fsl,pins = < 474 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 475 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 476 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 477 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 478 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 479 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 480 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 481 >; 482 }; 483 484 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 485 fsl,pins = < 486 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 487 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 488 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 489 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 490 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 491 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 492 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 493 >; 494 }; 495 496 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 497 fsl,pins = < 498 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 499 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 500 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 501 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 502 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 503 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 504 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 505 >; 506 }; 507 508 pinctrl_usdhc3: usdhc3grp { 509 fsl,pins = < 510 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 511 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 512 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 513 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 514 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 515 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 516 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 517 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 518 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 519 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 520 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 521 >; 522 }; 523 524 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 525 fsl,pins = < 526 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 527 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 528 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 529 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 530 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 531 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 532 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 533 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 534 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 535 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 536 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 537 >; 538 }; 539 540 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 541 fsl,pins = < 542 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 543 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 544 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 545 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 546 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 547 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 548 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 549 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 550 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 551 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 552 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 553 >; 554 }; 555 556 pinctrl_wdog: wdoggrp { 557 fsl,pins = < 558 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 559 >; 560 }; 561}; 562