1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2/*
3 * Copyright 2020-2021 TQ-Systems GmbH
4 */
5
6/dts-v1/;
7
8#include "imx8mm-tqma8mqml.dtsi"
9#include "mba8mx.dtsi"
10
11/ {
12	model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx";
13	compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
14
15	aliases {
16		eeprom0 = &eeprom3;
17		mmc0 = &usdhc3;
18		mmc1 = &usdhc2;
19		mmc2 = &usdhc1;
20		rtc0 = &pcf85063;
21		rtc1 = &snvs_rtc;
22	};
23
24	reg_usdhc2_vmmc: regulator-vmmc {
25		compatible = "regulator-fixed";
26		pinctrl-names = "default";
27		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
28		regulator-name = "VSD_3V3";
29		regulator-min-microvolt = <3300000>;
30		regulator-max-microvolt = <3300000>;
31		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
32		enable-active-high;
33		startup-delay-us = <100>;
34		off-on-delay-us = <12000>;
35	};
36
37	extcon_usbotg1: extcon-usbotg1 {
38		compatible = "linux,extcon-usb-gpio";
39		pinctrl-names = "default";
40		pinctrl-0 = <&pinctrl_usb1_extcon>;
41		id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
42	};
43};
44
45&i2c1 {
46	expander2: gpio@27 {
47		compatible = "nxp,pca9555";
48		reg = <0x27>;
49		gpio-controller;
50		#gpio-cells = <2>;
51		vcc-supply = <&reg_vcc_3v3>;
52		pinctrl-names = "default";
53		pinctrl-0 = <&pinctrl_expander>;
54		interrupt-parent = <&gpio1>;
55		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
56		interrupt-controller;
57		#interrupt-cells = <2>;
58	};
59};
60
61&sai3 {
62	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
63	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
64	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
65	clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
66		<&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
67		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
68		<&clk IMX8MM_AUDIO_PLL2_OUT>;
69};
70
71&tlv320aic3x04 {
72	clock-names = "mclk";
73	clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
74};
75
76&uart1 {
77	assigned-clocks = <&clk IMX8MM_CLK_UART1>;
78	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
79};
80
81&uart2 {
82	assigned-clocks = <&clk IMX8MM_CLK_UART2>;
83	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
84};
85
86&usbotg1 {
87	pinctrl-names = "default";
88	pinctrl-0 = <&pinctrl_usbotg1>;
89	dr_mode = "otg";
90	extcon = <&extcon_usbotg1>;
91	srp-disable;
92	hnp-disable;
93	adp-disable;
94	power-active-high;
95	over-current-active-low;
96	status = "okay";
97};
98
99&usbotg2 {
100	dr_mode = "host";
101	disable-over-current;
102	vbus-supply = <&reg_hub_vbus>;
103	status = "okay";
104};
105
106&iomuxc {
107	pinctrl_ecspi1: ecspi1grp {
108		fsl,pins = <MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x00000006>,
109			   <MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x00000006>,
110			   <MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x00000006>,
111			   <MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x00000006>;
112	};
113
114	pinctrl_ecspi2: ecspi2grp {
115		fsl,pins = <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x00000006>,
116			   <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x00000006>,
117			   <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x00000006>,
118			   <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x00000006>;
119	};
120
121	pinctrl_expander: expandergrp {
122		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x94>;
123	};
124
125	pinctrl_fec1: fec1grp {
126		fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x40000002>,
127			   <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x40000002>,
128			   <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x14>,
129			   <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x14>,
130			   <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x14>,
131			   <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x14>,
132			   <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x90>,
133			   <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x90>,
134			   <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x90>,
135			   <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x90>,
136			   <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x14>,
137			   <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x90>,
138			   <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x90>,
139			   <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x14>;
140	};
141
142	pinctrl_gpiobutton: gpiobuttongrp {
143		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x84>,
144			   <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x84>,
145			   <MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0		0x84>;
146	};
147
148	pinctrl_gpioled: gpioledgrp {
149		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x84>,
150			   <MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14		0x84>;
151	};
152
153	pinctrl_i2c2: i2c2grp {
154		fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x40000004>,
155			   <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x40000004>;
156	};
157
158	pinctrl_i2c2_gpio: i2c2gpiogrp {
159		fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x40000004>,
160			   <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x40000004>;
161	};
162
163	pinctrl_i2c3: i2c3grp {
164		fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x40000004>,
165			   <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x40000004>;
166	};
167
168	pinctrl_i2c3_gpio: i2c3gpiogrp {
169		fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x40000004>,
170			   <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x40000004>;
171	};
172
173	pinctrl_pwm3: pwm3grp {
174		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT		0x14>;
175	};
176
177	pinctrl_pwm4: pwm4grp {
178		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT		0x14>;
179	};
180
181	pinctrl_sai3: sai3grp {
182		fsl,pins = <MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK		0x94>,
183			   <MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK		0x94>,
184			   <MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC		0x94>,
185			   <MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0x94>,
186			   <MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0x94>,
187			   <MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0x94>,
188			   <MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0x94>;
189	};
190
191	pinctrl_uart1: uart1grp {
192		fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX		0x16>,
193			   <MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX		0x16>;
194	};
195
196	pinctrl_uart2: uart2grp {
197		fsl,pins = <MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x16>,
198			   <MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x16>;
199	};
200
201	pinctrl_uart3: uart3grp {
202		fsl,pins = <MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x16>,
203			   <MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x16>;
204	};
205
206	pinctrl_uart4: uart4grp {
207		fsl,pins = <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x16>,
208			   <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x16>;
209	};
210
211	pinctrl_usbotg1: usbotg1grp {
212		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR	0x84>,
213			   <MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x84>;
214	};
215
216	pinctrl_usb1_extcon: usb1-extcongrp {
217		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x1c0>;
218	};
219
220	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
221		fsl,pins = <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x84>;
222	};
223
224	pinctrl_usdhc2: usdhc2grp {
225		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
226			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
227			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
228			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
229			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
230			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
231			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
232	};
233
234	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
235		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
236			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
237			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
238			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
239			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
240			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
241			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
242	};
243
244	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
245		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
246			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
247			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
248			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
249			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
250			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
251			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
252	};
253};
254