1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH 4 * Author: Teresa Remmet <t.remmet@phytec.de> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12#include "imx8mm-phycore-som.dtsi" 13 14/ { 15 model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK"; 16 compatible = "phytec,imx8mm-phyboard-polis-rdk", 17 "phytec,imx8mm-phycore-som", "fsl,imx8mm"; 18 19 chosen { 20 stdout-path = &uart3; 21 }; 22 23 bt_osc_32k: bt-lp-clock { 24 compatible = "fixed-clock"; 25 clock-frequency = <32768>; 26 clock-output-names = "bt_osc_32k"; 27 #clock-cells = <0>; 28 }; 29 30 can_osc_40m: can-clock { 31 compatible = "fixed-clock"; 32 clock-frequency = <40000000>; 33 clock-output-names = "can_osc_40m"; 34 #clock-cells = <0>; 35 }; 36 37 fan { 38 compatible = "gpio-fan"; 39 gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; 40 gpio-fan,speed-map = <0 0 41 13000 1>; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_fan>; 44 #cooling-cells = <2>; 45 }; 46 47 leds { 48 compatible = "gpio-leds"; 49 pinctrl-names = "default"; 50 pinctrl-0 = <&pinctrl_leds>; 51 52 led-0 { 53 color = <LED_COLOR_ID_RED>; 54 function = LED_FUNCTION_DISK; 55 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 56 linux,default-trigger = "mmc2"; 57 }; 58 59 led-1 { 60 color = <LED_COLOR_ID_BLUE>; 61 function = LED_FUNCTION_DISK; 62 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; 63 linux,default-trigger = "mmc1"; 64 }; 65 66 led-2 { 67 color = <LED_COLOR_ID_GREEN>; 68 function = LED_FUNCTION_CPU; 69 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; 70 linux,default-trigger = "heartbeat"; 71 }; 72 }; 73 74 usdhc1_pwrseq: pwr-seq { 75 compatible = "mmc-pwrseq-simple"; 76 post-power-on-delay-ms = <100>; 77 power-off-delay-us = <60>; 78 reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; 79 }; 80 81 reg_can_en: regulator-can-en { 82 compatible = "regulator-fixed"; 83 gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; 84 pinctrl-names = "default"; 85 pinctrl-0 = <&pinctrl_can_en>; 86 regulator-max-microvolt = <3300000>; 87 regulator-min-microvolt = <3300000>; 88 regulator-name = "CAN_EN"; 89 startup-delay-us = <20>; 90 }; 91 92 reg_usb_otg1_vbus: regulator-usb-otg1 { 93 compatible = "regulator-fixed"; 94 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 95 enable-active-high; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_usbotg1pwrgrp>; 98 regulator-name = "usb_otg1_vbus"; 99 regulator-max-microvolt = <5000000>; 100 regulator-min-microvolt = <5000000>; 101 }; 102 103 reg_usdhc2_vmmc: regulator-usdhc2 { 104 compatible = "regulator-fixed"; 105 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 106 enable-active-high; 107 off-on-delay-us = <20000>; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 110 regulator-max-microvolt = <3300000>; 111 regulator-min-microvolt = <3300000>; 112 regulator-name = "VSD_3V3"; 113 }; 114 115 reg_vcc_3v3: regulator-vcc-3v3 { 116 compatible = "regulator-fixed"; 117 regulator-max-microvolt = <3300000>; 118 regulator-min-microvolt = <3300000>; 119 regulator-name = "VCC_3V3"; 120 }; 121}; 122 123/* SPI - CAN MCP251XFD */ 124&ecspi1 { 125 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_ecspi1>; 128 status = "okay"; 129 130 can0: can@0 { 131 compatible = "microchip,mcp251xfd"; 132 clocks = <&can_osc_40m>; 133 interrupt-parent = <&gpio1>; 134 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_can_int>; 137 reg = <0>; 138 spi-max-frequency = <20000000>; 139 xceiver-supply = <®_can_en>; 140 }; 141}; 142 143&gpio1 { 144 gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT", 145 "", "", "", "RESET_ETHPHY", 146 "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "", 147 "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE"; 148}; 149 150&gpio2 { 151 gpio-line-names = "", "", "", "", 152 "", "", "BT_REG_ON", "WL_REG_ON", 153 "BT_DEV_WAKE", "BT_HOST_WAKE", "", "", 154 "X_SD2_CD_B", "", "", "", 155 "", "", "", "SD2_RESET_B"; 156}; 157 158&gpio4 { 159 gpio-line-names = "", "", "", "", 160 "", "", "", "", 161 "FAN", "miniPCIe_nPERST", "", "", 162 "COEX1", "COEX2"; 163}; 164 165&gpio5 { 166 gpio-line-names = "", "", "", "", 167 "", "", "", "", 168 "", "ECSPI1_SS0"; 169}; 170 171/* PCIe */ 172&pcie0 { 173 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 174 <&clk IMX8MM_CLK_PCIE1_CTRL>; 175 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 176 <&clk IMX8MM_SYS_PLL2_250M>; 177 assigned-clock-rates = <10000000>, <250000000>; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_pcie>; 180 reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; 181 status = "okay"; 182}; 183 184&pcie_phy { 185 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 186 fsl,clkreq-unsupported; 187 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 188 fsl,tx-deemph-gen1 = <0x2d>; 189 fsl,tx-deemph-gen2 = <0xf>; 190 status = "okay"; 191}; 192 193&rv3028 { 194 trickle-resistor-ohms = <3000>; 195}; 196 197&snvs_pwrkey { 198 status = "okay"; 199}; 200 201/* UART - RS232/RS485 */ 202&uart1 { 203 assigned-clocks = <&clk IMX8MM_CLK_UART1>; 204 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_uart1>; 207 uart-has-rtscts; 208 status = "okay"; 209}; 210 211/* UART - Sterling-LWB Bluetooth */ 212&uart2 { 213 assigned-clocks = <&clk IMX8MM_CLK_UART2>; 214 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 215 fsl,dte-mode; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_uart2_bt>; 218 uart-has-rtscts; 219 status = "okay"; 220 221 bluetooth { 222 compatible = "brcm,bcm43438-bt"; 223 clocks = <&bt_osc_32k>; 224 clock-names = "lpo"; 225 device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 226 interrupt-names = "host-wakeup"; 227 interrupt-parent = <&gpio2>; 228 interrupts = <9 IRQ_TYPE_EDGE_BOTH>; 229 max-speed = <2000000>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_bt>; 232 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 233 vddio-supply = <®_vcc_3v3>; 234 }; 235}; 236 237/* UART - console */ 238&uart3 { 239 pinctrl-names = "default"; 240 pinctrl-0 = <&pinctrl_uart3>; 241 status = "okay"; 242}; 243 244/* USB */ 245&usbotg1 { 246 adp-disable; 247 dr_mode = "otg"; 248 over-current-active-low; 249 samsung,picophy-pre-emp-curr-control = <3>; 250 samsung,picophy-dc-vol-level-adjust = <7>; 251 srp-disable; 252 vbus-supply = <®_usb_otg1_vbus>; 253 status = "okay"; 254}; 255 256&usbotg2 { 257 disable-over-current; 258 dr_mode = "host"; 259 samsung,picophy-pre-emp-curr-control = <3>; 260 samsung,picophy-dc-vol-level-adjust = <7>; 261 status = "okay"; 262}; 263 264/* SDIO - Sterling-LWB Wifi */ 265&usdhc1 { 266 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; 267 assigned-clock-rates = <200000000>; 268 bus-width = <4>; 269 mmc-pwrseq = <&usdhc1_pwrseq>; 270 non-removable; 271 no-1-8-v; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 status = "okay"; 277 278 brcmf: wifi@1 { 279 compatible = "brcm,bcm4329-fmac"; 280 reg = <1>; 281 }; 282}; 283 284/* SD-Card */ 285&usdhc2 { 286 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 287 assigned-clock-rates = <200000000>; 288 bus-width = <4>; 289 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 290 disable-wp; 291 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 292 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 293 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 294 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 295 vmmc-supply = <®_usdhc2_vmmc>; 296 vqmmc-supply = <®_nvcc_sd2>; 297 status = "okay"; 298}; 299 300&iomuxc { 301 pinctrl_bt: btgrp { 302 fsl,pins = < 303 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 304 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 305 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 306 >; 307 }; 308 309 pinctrl_can_en: can-engrp { 310 fsl,pins = < 311 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 312 >; 313 }; 314 315 pinctrl_can_int: can-intgrp { 316 fsl,pins = < 317 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 318 >; 319 }; 320 321 pinctrl_ecspi1: ecspi1grp { 322 fsl,pins = < 323 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80 324 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80 325 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80 326 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 327 >; 328 }; 329 330 pinctrl_fan: fan0grp { 331 fsl,pins = < 332 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 333 >; 334 }; 335 336 pinctrl_leds: leds1grp { 337 fsl,pins = < 338 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 339 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 340 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 341 >; 342 }; 343 344 pinctrl_pcie: pciegrp { 345 fsl,pins = < 346 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00 347 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 348 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12 349 >; 350 }; 351 352 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 353 fsl,pins = < 354 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 355 >; 356 }; 357 358 pinctrl_uart1: uart1grp { 359 fsl,pins = < 360 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 361 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00 362 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00 363 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00 364 >; 365 }; 366 367 pinctrl_uart2_bt: uart2btgrp { 368 fsl,pins = < 369 MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00 370 MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00 371 MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00 372 MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00 373 >; 374 }; 375 376 pinctrl_uart3: uart3grp { 377 fsl,pins = < 378 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 379 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 380 >; 381 }; 382 383 pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { 384 fsl,pins = < 385 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 386 >; 387 }; 388 389 pinctrl_usdhc1: usdhc1grp { 390 fsl,pins = < 391 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 392 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 393 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 394 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 395 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 396 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 397 >; 398 }; 399 400 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 401 fsl,pins = < 402 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 403 >; 404 }; 405 406 pinctrl_usdhc2: usdhc2grp { 407 fsl,pins = < 408 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 409 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 410 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 411 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 412 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 413 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 414 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 415 >; 416 }; 417 418 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 419 fsl,pins = < 420 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 421 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 422 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 423 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 424 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 425 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 426 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 427 >; 428 }; 429 430 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 431 fsl,pins = < 432 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 433 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 434 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 435 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 436 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 437 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 438 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 439 >; 440 }; 441 442 pinctrl_wlan: wlangrp { 443 fsl,pins = < 444 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00 445 >; 446 }; 447}; 448