1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for Boundary Devices i.MX8MMini Nitrogen8MM Rev2 board.
4 * Adrien Grassein <adrien.grassein@gmail.com.com>
5 */
6/dts-v1/;
7#include "imx8mm.dtsi"
8
9/ {
10	model = "Boundary Devices i.MX8MMini Nitrogen8MM Rev2";
11	compatible = "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm";
12};
13
14&A53_0 {
15	cpu-supply = <&reg_buck3>;
16};
17
18&A53_1 {
19	cpu-supply = <&reg_buck3>;
20};
21
22&A53_2 {
23	cpu-supply = <&reg_buck3>;
24};
25
26&A53_3 {
27	cpu-supply = <&reg_buck3>;
28};
29
30&fec1 {
31	pinctrl-names = "default";
32	pinctrl-0 = <&pinctrl_fec1>;
33	phy-mode = "rgmii-id";
34	phy-handle = <&ethphy0>;
35	fsl,magic-packet;
36	status = "okay";
37
38	mdio {
39		#address-cells = <1>;
40		#size-cells = <0>;
41
42		ethphy0: ethernet-phy@4 {
43			compatible = "ethernet-phy-ieee802.3-c22";
44			reg = <4>;
45			interrupts-extended = <&gpio3 16 IRQ_TYPE_LEVEL_LOW>;
46		};
47	};
48};
49
50&i2c1 {
51	clock-frequency = <100000>;
52	pinctrl-names = "default";
53	pinctrl-0 = <&pinctrl_i2c1>;
54	status = "okay";
55
56	pmic@8 {
57		compatible = "nxp,pf8121a";
58		reg = <0x8>;
59
60		regulators {
61			reg_ldo1: ldo1 {
62				regulator-min-microvolt = <1500000>;
63				regulator-max-microvolt = <5000000>;
64				regulator-boot-on;
65				regulator-always-on;
66			};
67
68			reg_ldo2: ldo2 {
69				regulator-min-microvolt = <1500000>;
70				regulator-max-microvolt = <5000000>;
71				regulator-boot-on;
72				regulator-always-on;
73			};
74
75			reg_ldo3: ldo3 {
76				regulator-min-microvolt = <1500000>;
77				regulator-max-microvolt = <5000000>;
78				regulator-boot-on;
79				regulator-always-on;
80			};
81
82			reg_ldo4: ldo4 {
83				regulator-min-microvolt = <1500000>;
84				regulator-max-microvolt = <5000000>;
85				regulator-boot-on;
86				regulator-always-on;
87			};
88
89			reg_buck1: buck1 {
90				regulator-min-microvolt = <400000>;
91				regulator-max-microvolt = <1800000>;
92				regulator-boot-on;
93				regulator-always-on;
94			};
95
96			reg_buck2: buck2 {
97				regulator-min-microvolt = <400000>;
98				regulator-max-microvolt = <1800000>;
99				regulator-boot-on;
100				regulator-always-on;
101			};
102
103			reg_buck3: buck3 {
104				regulator-min-microvolt = <400000>;
105				regulator-max-microvolt = <1800000>;
106				regulator-boot-on;
107				regulator-always-on;
108			};
109
110			reg_buck4: buck4 {
111				regulator-min-microvolt = <400000>;
112				regulator-max-microvolt = <1800000>;
113				regulator-boot-on;
114				regulator-always-on;
115			};
116
117			reg_buck5: buck5 {
118				regulator-min-microvolt = <400000>;
119				regulator-max-microvolt = <1800000>;
120				regulator-boot-on;
121				regulator-always-on;
122			};
123
124			reg_buck6: buck6 {
125				regulator-min-microvolt = <400000>;
126				regulator-max-microvolt = <1800000>;
127				regulator-boot-on;
128				regulator-always-on;
129			};
130
131			reg_buck7: buck7 {
132				regulator-min-microvolt = <3300000>;
133				regulator-max-microvolt = <3300000>;
134				regulator-boot-on;
135				regulator-always-on;
136			};
137
138			reg_vsnvs: vsnvs {
139				regulator-min-microvolt = <1800000>;
140				regulator-max-microvolt = <3300000>;
141				regulator-boot-on;
142			};
143		};
144	};
145};
146
147&i2c3 {
148	clock-frequency = <100000>;
149	pinctrl-names = "default";
150	pinctrl-0 = <&pinctrl_i2c3>;
151	status = "okay";
152
153	i2cmux@70 {
154		compatible = "nxp,pca9540";
155		reg = <0x70>;
156		#address-cells = <1>;
157		#size-cells = <0>;
158
159		i2c3 {
160			reg = <0>;
161			#address-cells = <1>;
162			#size-cells = <0>;
163
164			rtc@68 {
165				compatible = "microcrystal,rv4162";
166				reg = <0x68>;
167				pinctrl-names = "default";
168				pinctrl-0 = <&pinctrl_i2c3a_rv4162>;
169				interrupts-extended = <&gpio4 22 IRQ_TYPE_LEVEL_LOW>;
170				wakeup-source;
171			};
172		};
173	};
174};
175
176/* console */
177&uart2 {
178	pinctrl-names = "default";
179	pinctrl-0 = <&pinctrl_uart2>;
180	assigned-clocks = <&clk IMX8MM_CLK_UART2>;
181	assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
182	status = "okay";
183};
184
185/* eMMC */
186&usdhc1 {
187	bus-width = <8>;
188	sdhci-caps-mask = <0x80000000 0x0>;
189	non-removable;
190	pinctrl-names = "default", "state_100mhz", "state_200mhz";
191	pinctrl-0 = <&pinctrl_usdhc1>;
192	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
193	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
194	status = "okay";
195};
196
197/* sdcard */
198&usdhc2 {
199	bus-width = <4>;
200	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
201	pinctrl-names = "default", "state_100mhz", "state_200mhz";
202	pinctrl-0 = <&pinctrl_usdhc2>;
203	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
204	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
205	vqmmc-supply = <&reg_ldo2>;
206	status = "okay";
207};
208
209&wdog1 {
210	pinctrl-names = "default";
211	pinctrl-0 = <&pinctrl_wdog>;
212	fsl,ext-reset-output;
213	status = "okay";
214};
215
216&iomuxc {
217	pinctrl-names = "default";
218	pinctrl-0 = <&pinctrl_hog>;
219
220	pinctrl_fec1: fec1grp {
221		fsl,pins = <
222			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
223			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
224			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
225			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
226			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
227			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
228			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
229			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
230			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
231			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
232			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
233			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
234			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
235			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
236			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16		0x159
237		>;
238	};
239
240	pinctrl_hog: hoggrp {
241		fsl,pins = <
242			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x09
243			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x09
244		>;
245	};
246
247	pinctrl_i2c1: i2c1grp {
248		fsl,pins = <
249			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
250			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
251		>;
252	};
253
254	pinctrl_i2c3: i2c3grp {
255		fsl,pins = <
256			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
257			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
258		>;
259	};
260
261	pinctrl_i2c3a_rv4162: i2c3a-rv4162grp {
262		fsl,pins = <
263			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1c0
264		>;
265	};
266
267	pinctrl_uart2: uart2grp {
268		fsl,pins = <
269			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
270			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
271		>;
272	};
273
274	pinctrl_usdhc1: usdhc1grp {
275		fsl,pins = <
276			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
277			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
278			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
279			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
280			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
281			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
282			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d0
283			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d0
284			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d0
285			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d0
286			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x141
287		>;
288	};
289
290	pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
291		fsl,pins = <
292			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
293			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
294			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
295			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
296			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
297			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
298			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d4
299			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d4
300			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d4
301			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d4
302		>;
303	};
304
305	pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
306		fsl,pins = <
307			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
308			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
309			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
310			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
311			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
312			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
313			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d6
314			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d6
315			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d6
316			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d6
317		>;
318	};
319
320	pinctrl_usdhc2: usdhc2grp {
321		fsl,pins = <
322			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
323			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
324			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
325			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
326			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
327			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
328			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
329		>;
330	};
331
332	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
333		fsl,pins = <
334			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
335			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
336			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
337			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
338			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
339			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
340		>;
341	};
342
343	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
344		fsl,pins = <
345			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
346			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
347			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
348			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
349			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
350			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
351		>;
352	};
353
354	pinctrl_usdhc3: usdhc3grp {
355		fsl,pins = <
356			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
357			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
358			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
359			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
360			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
361			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
362			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x03
363		>;
364	};
365
366	pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
367		fsl,pins = <
368			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
369			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
370			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
371			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
372			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
373			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
374		>;
375	};
376
377	pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
378		fsl,pins = <
379			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
380			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
381			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
382			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
383			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
384			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
385		>;
386	};
387
388	pinctrl_wdog: wdoggrp {
389		fsl,pins = <
390			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140
391		>;
392	};
393};
394