1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2022 Kontron Electronics GmbH
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include "imx8mm.dtsi"
8
9/ {
10	model = "Kontron OSM-S i.MX8MM (N802X SOM)";
11	compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm";
12
13	memory@40000000 {
14		device_type = "memory";
15		/*
16		 * There are multiple SoM flavors with different DDR sizes.
17		 * The smallest is 1GB. For larger sizes the bootloader will
18		 * update the reg property.
19		 */
20		reg = <0x0 0x40000000 0 0x80000000>;
21	};
22
23	chosen {
24		stdout-path = &uart3;
25	};
26};
27
28&A53_0 {
29	cpu-supply = <&reg_vdd_arm>;
30};
31
32&A53_1 {
33	cpu-supply = <&reg_vdd_arm>;
34};
35
36&A53_2 {
37	cpu-supply = <&reg_vdd_arm>;
38};
39
40&A53_3 {
41	cpu-supply = <&reg_vdd_arm>;
42};
43
44&ddrc {
45	operating-points-v2 = <&ddrc_opp_table>;
46
47	ddrc_opp_table: opp-table {
48		compatible = "operating-points-v2";
49
50		opp-100M {
51			opp-hz = /bits/ 64 <100000000>;
52		};
53
54		opp-750M {
55			opp-hz = /bits/ 64 <750000000>;
56		};
57	};
58};
59
60&ecspi1 {
61	pinctrl-names = "default";
62	pinctrl-0 = <&pinctrl_ecspi1>;
63	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
64	status = "okay";
65
66	flash@0 {
67		compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
68		spi-max-frequency = <80000000>;
69		reg = <0>;
70
71		partitions {
72			compatible = "fixed-partitions";
73			#address-cells = <1>;
74			#size-cells = <1>;
75
76			partition@0 {
77				label = "u-boot";
78				reg = <0x0 0x1e0000>;
79			};
80
81			partition@1e0000 {
82				label = "env";
83				reg = <0x1e0000 0x10000>;
84			};
85
86			partition@1f0000 {
87				label = "env_redundant";
88				reg = <0x1f0000 0x10000>;
89			};
90		};
91	};
92};
93
94&i2c1 {
95	clock-frequency = <400000>;
96	pinctrl-names = "default";
97	pinctrl-0 = <&pinctrl_i2c1>;
98	status = "okay";
99
100	pca9450: pmic@25 {
101		compatible = "nxp,pca9450a";
102		reg = <0x25>;
103		pinctrl-names = "default";
104		pinctrl-0 = <&pinctrl_pmic>;
105		interrupt-parent = <&gpio1>;
106		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
107
108		regulators {
109			reg_vdd_soc: BUCK1 {
110				regulator-name = "+0V8_VDD_SOC (BUCK1)";
111				regulator-min-microvolt = <800000>;
112				regulator-max-microvolt = <850000>;
113				regulator-boot-on;
114				regulator-always-on;
115				regulator-ramp-delay = <3125>;
116				nxp,dvs-run-voltage = <850000>;
117				nxp,dvs-standby-voltage = <800000>;
118			};
119
120			reg_vdd_arm: BUCK2 {
121				regulator-name = "+0V9_VDD_ARM (BUCK2)";
122				regulator-min-microvolt = <850000>;
123				regulator-max-microvolt = <950000>;
124				regulator-boot-on;
125				regulator-always-on;
126				regulator-ramp-delay = <3125>;
127				nxp,dvs-run-voltage = <950000>;
128				nxp,dvs-standby-voltage = <850000>;
129			};
130
131			reg_vdd_dram: BUCK3 {
132				regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)";
133				regulator-min-microvolt = <850000>;
134				regulator-max-microvolt = <950000>;
135				regulator-boot-on;
136				regulator-always-on;
137			};
138
139			reg_vdd_3v3: BUCK4 {
140				regulator-name = "+3V3 (BUCK4)";
141				regulator-min-microvolt = <3300000>;
142				regulator-max-microvolt = <3300000>;
143				regulator-boot-on;
144				regulator-always-on;
145			};
146
147			reg_vdd_1v8: BUCK5 {
148				regulator-name = "+1V8 (BUCK5)";
149				regulator-min-microvolt = <1800000>;
150				regulator-max-microvolt = <1800000>;
151				regulator-boot-on;
152				regulator-always-on;
153			};
154
155			reg_nvcc_dram: BUCK6 {
156				regulator-name = "+1V1_NVCC_DRAM (BUCK6)";
157				regulator-min-microvolt = <1100000>;
158				regulator-max-microvolt = <1100000>;
159				regulator-boot-on;
160				regulator-always-on;
161			};
162
163			reg_nvcc_snvs: LDO1 {
164				regulator-name = "+1V8_NVCC_SNVS (LDO1)";
165				regulator-min-microvolt = <1800000>;
166				regulator-max-microvolt = <1800000>;
167				regulator-boot-on;
168				regulator-always-on;
169			};
170
171			reg_vdd_snvs: LDO2 {
172				regulator-name = "+0V8_VDD_SNVS (LDO2)";
173				regulator-min-microvolt = <800000>;
174				regulator-max-microvolt = <900000>;
175				regulator-boot-on;
176				regulator-always-on;
177			};
178
179			reg_vdda: LDO3 {
180				regulator-name = "+1V8_VDDA (LDO3)";
181				regulator-min-microvolt = <1800000>;
182				regulator-max-microvolt = <1800000>;
183				regulator-boot-on;
184				regulator-always-on;
185			};
186
187			reg_vdd_phy: LDO4 {
188				regulator-name = "+0V9_VDD_PHY (LDO4)";
189				regulator-min-microvolt = <900000>;
190				regulator-max-microvolt = <900000>;
191				regulator-boot-on;
192				regulator-always-on;
193			};
194
195			reg_nvcc_sd: LDO5 {
196				regulator-name = "NVCC_SD (LDO5)";
197				regulator-min-microvolt = <1800000>;
198				regulator-max-microvolt = <3300000>;
199			};
200		};
201	};
202
203	rtc@52 {
204		compatible = "microcrystal,rv3028";
205		reg = <0x52>;
206		pinctrl-names = "default";
207		pinctrl-0 = <&pinctrl_rtc>;
208		interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>;
209		trickle-diode-disable;
210	};
211};
212
213&uart3 { /* console */
214	pinctrl-names = "default";
215	pinctrl-0 = <&pinctrl_uart3>;
216	status = "okay";
217};
218
219&usdhc1 {
220	pinctrl-names = "default", "state_100mhz", "state_200mhz";
221	pinctrl-0 = <&pinctrl_usdhc1>;
222	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
223	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
224	vmmc-supply = <&reg_vdd_3v3>;
225	vqmmc-supply = <&reg_vdd_1v8>;
226	bus-width = <8>;
227	non-removable;
228	status = "okay";
229};
230
231&wdog1 {
232	pinctrl-names = "default";
233	pinctrl-0 = <&pinctrl_wdog>;
234	fsl,ext-reset-output;
235	status = "okay";
236};
237
238&iomuxc {
239	pinctrl_ecspi1: ecspi1grp {
240		fsl,pins = <
241			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x82
242			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x82
243			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x82
244			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x19
245		>;
246	};
247
248	pinctrl_i2c1: i2c1grp {
249		fsl,pins = <
250			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
251			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
252		>;
253	};
254
255	pinctrl_pmic: pmicgrp {
256		fsl,pins = <
257			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x141
258		>;
259	};
260
261	pinctrl_rtc: rtcgrp {
262		fsl,pins = <
263			MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1			0x19
264		>;
265	};
266
267	pinctrl_uart3: uart3grp {
268		fsl,pins = <
269			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x140
270			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x140
271		>;
272	};
273
274	pinctrl_usdhc1: usdhc1grp {
275		fsl,pins = <
276			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x190
277			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d0
278			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0
279			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0
280			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0
281			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0
282			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d0
283			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d0
284			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d0
285			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d0
286			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0x019
287			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x190
288		>;
289	};
290
291	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
292		fsl,pins = <
293			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x194
294			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d4
295			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4
296			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4
297			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4
298			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4
299			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d4
300			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d4
301			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d4
302			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d4
303			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0x019
304			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x194
305		>;
306	};
307
308	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
309		fsl,pins = <
310			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x196
311			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d6
312			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6
313			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6
314			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6
315			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6
316			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d6
317			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d6
318			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d6
319			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d6
320			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0x019
321			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x196
322		>;
323	};
324
325	pinctrl_wdog: wdoggrp {
326		fsl,pins = <
327			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
328		>;
329	};
330};
331