1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2019 Kontron Electronics GmbH
4 */
5
6/dts-v1/;
7
8#include "imx8mm-kontron-sl.dtsi"
9
10/ {
11	model = "Kontron BL i.MX8MM (N801X S)";
12	compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";
13
14	aliases {
15		ethernet1 = &usbnet;
16	};
17
18	/* fixed crystal dedicated to mcp2515 */
19	osc_can: clock-osc-can {
20		compatible = "fixed-clock";
21		#clock-cells = <0>;
22		clock-frequency = <16000000>;
23		clock-output-names = "osc-can";
24	};
25
26	leds {
27		compatible = "gpio-leds";
28		pinctrl-names = "default";
29		pinctrl-0 = <&pinctrl_gpio_led>;
30
31		led1 {
32			label = "led1";
33			gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
34			linux,default-trigger = "heartbeat";
35		};
36
37		led2 {
38			label = "led2";
39			gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
40		};
41
42		led3 {
43			label = "led3";
44			gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
45		};
46
47		led4 {
48			label = "led4";
49			gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
50		};
51
52		led5 {
53			label = "led5";
54			gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
55		};
56
57		led6 {
58			label = "led6";
59			gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
60		};
61	};
62
63	pwm-beeper {
64		compatible = "pwm-beeper";
65		pwms = <&pwm2 0 5000 0>;
66	};
67
68	reg_rst_eth2: regulator-rst-eth2 {
69		compatible = "regulator-fixed";
70		regulator-name = "rst-usb-eth2";
71		pinctrl-names = "default";
72		pinctrl-0 = <&pinctrl_usb_eth2>;
73		gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
74		enable-active-high;
75		regulator-always-on;
76	};
77
78	reg_vdd_5v: regulator-5v {
79		compatible = "regulator-fixed";
80		regulator-name = "vdd-5v";
81		regulator-min-microvolt = <5000000>;
82		regulator-max-microvolt = <5000000>;
83	};
84};
85
86&ecspi2 {
87	pinctrl-names = "default";
88	pinctrl-0 = <&pinctrl_ecspi2>;
89	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
90	status = "okay";
91
92	can0: can@0 {
93		compatible = "microchip,mcp2515";
94		reg = <0>;
95		pinctrl-names = "default";
96		pinctrl-0 = <&pinctrl_can>;
97		clocks = <&osc_can>;
98		interrupt-parent = <&gpio4>;
99		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
100		spi-max-frequency = <10000000>;
101		vdd-supply = <&reg_vdd_3v3>;
102		xceiver-supply = <&reg_vdd_5v>;
103	};
104};
105
106&ecspi3 {
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_ecspi3>;
109	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
110	status = "okay";
111};
112
113&fec1 {
114	pinctrl-names = "default";
115	pinctrl-0 = <&pinctrl_enet>;
116	phy-connection-type = "rgmii-rxid";
117	phy-handle = <&ethphy>;
118	status = "okay";
119
120	mdio {
121		#address-cells = <1>;
122		#size-cells = <0>;
123
124		ethphy: ethernet-phy@0 {
125			reg = <0>;
126			reset-assert-us = <1>;
127			reset-deassert-us = <15000>;
128			reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
129		};
130	};
131};
132
133&i2c4 {
134	clock-frequency = <100000>;
135	pinctrl-names = "default";
136	pinctrl-0 = <&pinctrl_i2c4>;
137	status = "okay";
138
139	rtc@32 {
140		compatible = "epson,rx8900";
141		reg = <0x32>;
142	};
143};
144
145&pwm2 {
146	pinctrl-names = "default";
147	pinctrl-0 = <&pinctrl_pwm2>;
148	status = "okay";
149};
150
151&uart1 {
152	pinctrl-names = "default";
153	pinctrl-0 = <&pinctrl_uart1>;
154	uart-has-rtscts;
155	status = "okay";
156};
157
158&uart2 {
159	pinctrl-names = "default";
160	pinctrl-0 = <&pinctrl_uart2>;
161	linux,rs485-enabled-at-boot-time;
162	uart-has-rtscts;
163	status = "okay";
164};
165
166&usbotg1 {
167	dr_mode = "otg";
168	over-current-active-low;
169	status = "okay";
170};
171
172&usbotg2 {
173	dr_mode = "host";
174	disable-over-current;
175	#address-cells = <1>;
176	#size-cells = <0>;
177	status = "okay";
178
179	usb1@1 {
180		compatible = "usb424,9514";
181		reg = <1>;
182		#address-cells = <1>;
183		#size-cells = <0>;
184
185		usbnet: ethernet@1 {
186			compatible = "usb424,ec00";
187			reg = <1>;
188			local-mac-address = [ 00 00 00 00 00 00 ];
189		};
190	};
191};
192
193&usdhc2 {
194	pinctrl-names = "default", "state_100mhz", "state_200mhz";
195	pinctrl-0 = <&pinctrl_usdhc2>;
196	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
197	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
198	vmmc-supply = <&reg_vdd_3v3>;
199	vqmmc-supply = <&reg_nvcc_sd>;
200	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
201	status = "okay";
202};
203
204&iomuxc {
205	pinctrl-names = "default";
206	pinctrl-0 = <&pinctrl_gpio>;
207
208	pinctrl_can: cangrp {
209		fsl,pins = <
210			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x19
211		>;
212	};
213
214	pinctrl_ecspi2: ecspi2grp {
215		fsl,pins = <
216			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
217			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82
218			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82
219			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x19
220		>;
221	};
222
223	pinctrl_ecspi3: ecspi3grp {
224		fsl,pins = <
225			MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO		0x82
226			MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x82
227			MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x82
228			MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x19
229		>;
230	};
231
232	pinctrl_enet: enetgrp {
233		fsl,pins = <
234			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
235			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
236			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
237			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
238			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
239			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
240			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
241			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
242			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
243			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
244			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
245			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
246			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
247			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
248			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19 /* PHY RST */
249			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25		0x19 /* ETH IRQ */
250		>;
251	};
252
253	pinctrl_gpio_led: gpioledgrp {
254		fsl,pins = <
255			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19
256			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x19
257			MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x19
258			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x19
259			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17		0x19
260			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x19
261			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x19
262		>;
263	};
264
265	pinctrl_gpio: gpiogrp {
266		fsl,pins = <
267			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19
268			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
269			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
270			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19
271			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
272			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x19
273			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19
274			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x19
275		>;
276	};
277
278	pinctrl_i2c4: i2c4grp {
279		fsl,pins = <
280			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x400001c3
281			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x400001c3
282		>;
283	};
284
285	pinctrl_pwm2: pwm2grp {
286		fsl,pins = <
287			MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT			0x19
288		>;
289	};
290
291	pinctrl_uart1: uart1grp {
292		fsl,pins = <
293			MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX		0x140
294			MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX		0x140
295			MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B		0x140
296			MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B		0x140
297		>;
298	};
299
300	pinctrl_uart2: uart2grp {
301		fsl,pins = <
302			MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX		0x140
303			MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX		0x140
304			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B		0x140
305			MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B		0x140
306		>;
307	};
308
309	pinctrl_usb_eth2: usbeth2grp {
310		fsl,pins = <
311			MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x19
312		>;
313	};
314
315	pinctrl_usdhc2: usdhc2grp {
316		fsl,pins = <
317			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x190
318			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0
319			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0
320			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0
321			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0
322			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0
323			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x019
324			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0
325		>;
326	};
327
328	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
329		fsl,pins = <
330			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x194
331			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4
332			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4
333			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4
334			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4
335			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4
336			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x019
337			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0
338		>;
339	};
340
341	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
342		fsl,pins = <
343			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x196
344			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6
345			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6
346			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6
347			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6
348			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6
349			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x019
350			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0
351		>;
352	};
353};
354