1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2022 Kontron Electronics GmbH
4 */
5
6/dts-v1/;
7
8#include "imx8mm-kontron-osm-s.dtsi"
9
10/ {
11	model = "Kontron BL i.MX8MM OSM-S (N802X S)";
12	compatible = "kontron,imx8mm-bl-osm-s", "kontron,imx8mm-osm-s", "fsl,imx8mm";
13
14	aliases {
15		ethernet1 = &usbnet;
16	};
17
18	/* fixed crystal dedicated to mcp2542fd */
19	osc_can: clock-osc-can {
20		compatible = "fixed-clock";
21		#clock-cells = <0>;
22		clock-frequency = <40000000>;
23		clock-output-names = "osc-can";
24	};
25
26	leds {
27		compatible = "gpio-leds";
28		pinctrl-names = "default";
29		pinctrl-0 = <&pinctrl_gpio_led>;
30
31		led1 {
32			label = "led1";
33			gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
34			linux,default-trigger = "heartbeat";
35		};
36
37		led2 {
38			label = "led2";
39			gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
40		};
41
42		led3 {
43			label = "led3";
44			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
45		};
46	};
47
48	pwm-beeper {
49		compatible = "pwm-beeper";
50		pwms = <&pwm2 0 5000 0>;
51	};
52
53	reg_rst_eth2: regulator-rst-eth2 {
54		compatible = "regulator-fixed";
55		pinctrl-names = "default";
56		pinctrl-0 = <&pinctrl_usb_eth2>;
57		gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
58		enable-active-high;
59		regulator-always-on;
60		regulator-name = "rst-usb-eth2";
61	};
62
63	reg_usb1_vbus: regulator-usb1-vbus {
64		compatible = "regulator-fixed";
65		pinctrl-names = "default";
66		pinctrl-0 = <&pinctrl_reg_usb1_vbus>;
67		gpio = <&gpio3 25 GPIO_ACTIVE_LOW>;
68		regulator-min-microvolt = <5000000>;
69		regulator-max-microvolt = <5000000>;
70		regulator-name = "usb1-vbus";
71	};
72
73	reg_vdd_5v: regulator-5v {
74		compatible = "regulator-fixed";
75		regulator-always-on;
76		regulator-min-microvolt = <5000000>;
77		regulator-max-microvolt = <5000000>;
78		regulator-name = "vdd-5v";
79	};
80};
81
82&ecspi2 {
83	pinctrl-names = "default";
84	pinctrl-0 = <&pinctrl_ecspi2>;
85	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
86	status = "okay";
87
88	can@0 {
89		compatible = "microchip,mcp251xfd";
90		reg = <0>;
91		pinctrl-names = "default";
92		pinctrl-0 = <&pinctrl_can>;
93		clocks = <&osc_can>;
94		interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>;
95		/*
96		 * Limit the SPI clock to 15 MHz to prevent issues
97		 * with corrupted data due to chip errata.
98		 */
99		spi-max-frequency = <15000000>;
100		vdd-supply = <&reg_vdd_3v3>;
101		xceiver-supply = <&reg_vdd_5v>;
102	};
103};
104
105&ecspi3 {
106	pinctrl-names = "default";
107	pinctrl-0 = <&pinctrl_ecspi3>;
108	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
109	status = "okay";
110
111	eeram@0 {
112		compatible = "microchip,48l640";
113		reg = <0>;
114		spi-max-frequency = <20000000>;
115	};
116};
117
118&fec1 {
119	pinctrl-names = "default";
120	pinctrl-0 = <&pinctrl_enet>;
121	phy-connection-type = "rgmii-rxid";
122	phy-handle = <&ethphy>;
123	status = "okay";
124
125	mdio {
126		#address-cells = <1>;
127		#size-cells = <0>;
128
129		ethphy: ethernet-phy@0 {
130			reg = <0>;
131			reset-assert-us = <1>;
132			reset-deassert-us = <15000>;
133			reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
134		};
135	};
136};
137
138&gpio1 {
139	pinctrl-names = "default";
140	pinctrl-0 = <&pinctrl_gpio1>;
141	gpio-line-names = "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out",
142			  "dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "",
143			  "", "", "", "", "", "", "", "",
144			  "", "", "", "", "", "", "", "";
145};
146
147&gpio5 {
148	pinctrl-names = "default";
149	pinctrl-0 = <&pinctrl_gpio5>;
150	gpio-line-names = "", "", "dio4-in", "", "", "", "", "",
151			  "", "", "", "", "", "", "", "",
152			  "", "", "", "", "", "", "", "",
153			  "", "", "", "", "", "", "", "";
154};
155
156&i2c4 {
157	clock-frequency = <100000>;
158	pinctrl-names = "default";
159	pinctrl-0 = <&pinctrl_i2c4>;
160	status = "okay";
161};
162
163&pwm2 {
164	pinctrl-names = "default";
165	pinctrl-0 = <&pinctrl_pwm2>;
166	status = "okay";
167};
168
169&uart1 {
170	pinctrl-names = "default";
171	pinctrl-0 = <&pinctrl_uart1>;
172	uart-has-rtscts;
173	status = "okay";
174};
175
176&uart2 {
177	pinctrl-names = "default";
178	pinctrl-0 = <&pinctrl_uart2>;
179	linux,rs485-enabled-at-boot-time;
180	uart-has-rtscts;
181	status = "okay";
182};
183
184&usbotg1 {
185	dr_mode = "otg";
186	disable-over-current;
187	vbus-supply = <&reg_usb1_vbus>;
188	status = "okay";
189};
190
191&usbotg2 {
192	dr_mode = "host";
193	disable-over-current;
194	#address-cells = <1>;
195	#size-cells = <0>;
196	status = "okay";
197
198	usb1@1 {
199		compatible = "usb424,9514";
200		reg = <1>;
201		#address-cells = <1>;
202		#size-cells = <0>;
203
204		usbnet: ethernet@1 {
205			compatible = "usb424,ec00";
206			reg = <1>;
207			local-mac-address = [ 00 00 00 00 00 00 ];
208		};
209	};
210};
211
212&usdhc2 {
213	pinctrl-names = "default", "state_100mhz", "state_200mhz";
214	pinctrl-0 = <&pinctrl_usdhc2>;
215	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
216	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
217	vmmc-supply = <&reg_vdd_3v3>;
218	vqmmc-supply = <&reg_nvcc_sd>;
219	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
220	status = "okay";
221};
222
223&iomuxc {
224	pinctrl_can: cangrp {
225		fsl,pins = <
226			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x19
227		>;
228	};
229
230	pinctrl_ecspi2: ecspi2grp {
231		fsl,pins = <
232			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
233			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82
234			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82
235			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x19
236		>;
237	};
238
239	pinctrl_ecspi3: ecspi3grp {
240		fsl,pins = <
241			MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO		0x82
242			MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x82
243			MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x82
244			MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x19
245		>;
246	};
247
248	pinctrl_enet: enetgrp {
249		fsl,pins = <
250			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
251			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
252			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
253			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
254			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
255			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
256			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
257			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
258			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
259			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
260			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
261			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
262			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
263			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
264			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x19 /* PHY RST */
265			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x19 /* ETH IRQ */
266		>;
267	};
268
269	pinctrl_gpio_led: gpioledgrp {
270		fsl,pins = <
271			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x19
272			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x19
273			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x19
274		>;
275	};
276
277	pinctrl_gpio1: gpio1grp {
278		fsl,pins = <
279			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19
280			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
281			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
282			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19
283			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
284			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x19
285			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19
286		>;
287	};
288
289	pinctrl_gpio5: gpio5grp {
290		fsl,pins = <
291			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x19
292		>;
293	};
294
295	pinctrl_i2c4: i2c4grp {
296		fsl,pins = <
297			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000083
298			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000083
299		>;
300	};
301
302	pinctrl_pwm2: pwm2grp {
303		fsl,pins = <
304			MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT			0x19
305		>;
306	};
307
308	pinctrl_reg_usb1_vbus: regusb1vbusgrp {
309		fsl,pins = <
310			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x19
311		>;
312	};
313
314	pinctrl_uart1: uart1grp {
315		fsl,pins = <
316			MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX		0x0
317			MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX		0x0
318			MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B		0x0
319			MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B		0x0
320		>;
321	};
322
323	pinctrl_uart2: uart2grp {
324		fsl,pins = <
325			MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX		0x0
326			MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX		0x0
327			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B		0x0
328			MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B		0x0
329		>;
330	};
331
332	pinctrl_usb_eth2: usbeth2grp {
333		fsl,pins = <
334			MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x19
335		>;
336	};
337
338	pinctrl_usdhc2: usdhc2grp {
339		fsl,pins = <
340			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x90
341			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0
342			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0
343			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0
344			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0
345			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0
346			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19
347			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xd0
348		>;
349	};
350
351	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
352		fsl,pins = <
353			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x94
354			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4
355			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4
356			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4
357			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4
358			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4
359			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19
360			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xd0
361		>;
362	};
363
364	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
365		fsl,pins = <
366			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x96
367			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6
368			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6
369			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6
370			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6
371			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6
372			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19
373			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xd0
374		>;
375	};
376};
377