1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2018 Bang & Olufsen
4 */
5
6#include "imx8mm.dtsi"
7#include <dt-bindings/phy/phy-imx8-pcie.h>
8
9/ {
10	reg_modem: regulator-modem {
11		compatible = "regulator-fixed";
12		pinctrl-names = "default";
13		pinctrl-0 = <&pinctrl_modem_regulator>;
14		regulator-min-microvolt = <3300000>;
15		regulator-max-microvolt = <3300000>;
16		regulator-name = "epdev_on";
17		gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
18		enable-active-high;
19		regulator-always-on;
20	};
21
22	reg_3v3_out: regulator-3v3-out {
23		compatible = "regulator-fixed";
24		regulator-name = "3V3_OUT";
25		regulator-min-microvolt = <3300000>;
26		regulator-max-microvolt = <3300000>;
27	};
28};
29
30&cpu_alert0 {
31	temperature = <95000>;
32};
33
34&cpu_crit0 {
35	temperature = <105000>;
36};
37
38&ddrc {
39	operating-points-v2 = <&ddrc_opp_table>;
40
41	ddrc_opp_table: opp-table {
42		compatible = "operating-points-v2";
43
44		opp-25000000 {
45			opp-hz = /bits/ 64 <25000000>;
46		};
47
48		opp-100000000 {
49			opp-hz = /bits/ 64 <100000000>;
50		};
51
52		opp-600000000 {
53			opp-hz = /bits/ 64 <600000000>;
54		};
55	};
56};
57
58&i2c1 {
59	clock-frequency = <100000>;
60	pinctrl-names = "default", "gpio";
61	pinctrl-0 = <&pinctrl_i2c1>;
62	pinctrl-1 = <&pinctrl_i2c1_gpio>;
63	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
64	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
65	status = "okay";
66
67	pmic@4b {
68		compatible = "rohm,bd71847";
69		reg = <0x4b>;
70		pinctrl-0 = <&pinctrl_pmic>;
71		interrupt-parent = <&gpio1>;
72		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
73		rohm,reset-snvs-powered;
74
75		regulators {
76			buck1_reg: BUCK1 {
77				regulator-name = "buck1";
78				regulator-min-microvolt = <700000>;
79				regulator-max-microvolt = <1300000>;
80				regulator-boot-on;
81				regulator-always-on;
82				regulator-ramp-delay = <1250>;
83				rohm,dvs-run-voltage = <850000>;
84				rohm,dvs-idle-voltage = <850000>;
85				rohm,dvs-suspend-voltage = <850000>;
86			};
87
88			buck2_reg: BUCK2 {
89				regulator-name = "buck2";
90				regulator-min-microvolt = <700000>;
91				regulator-max-microvolt = <1300000>;
92				regulator-boot-on;
93				regulator-always-on;
94				regulator-ramp-delay = <1250>;
95				rohm,dvs-run-voltage = <1000000>;
96				rohm,dvs-idle-voltage = <900000>;
97			};
98
99			buck3_reg: BUCK3 {
100				// buck5 in datasheet
101				regulator-name = "buck3";
102				regulator-min-microvolt = <700000>;
103				regulator-max-microvolt = <1350000>;
104				regulator-boot-on;
105				regulator-always-on;
106			};
107
108			buck4_reg: BUCK4 {
109				// buck6 in datasheet
110				regulator-name = "buck4";
111				regulator-min-microvolt = <3000000>;
112				regulator-max-microvolt = <3300000>;
113				regulator-boot-on;
114				regulator-always-on;
115			};
116
117			buck5_reg: BUCK5 {
118				// buck7 in datasheet
119				regulator-name = "buck5";
120				regulator-min-microvolt = <1605000>;
121				regulator-max-microvolt = <1995000>;
122				regulator-boot-on;
123				regulator-always-on;
124			};
125
126			buck6_reg: BUCK6 {
127				// buck8 in datasheet
128				regulator-name = "buck6";
129				regulator-min-microvolt = <800000>;
130				regulator-max-microvolt = <1400000>;
131				regulator-boot-on;
132				regulator-always-on;
133			};
134
135			ldo1_reg: LDO1 {
136				regulator-name = "ldo1";
137				regulator-min-microvolt = <1800000>;
138				regulator-max-microvolt = <3300000>;
139				regulator-boot-on;
140				regulator-always-on;
141			};
142
143			ldo2_reg: LDO2 {
144				regulator-name = "ldo2";
145				regulator-min-microvolt = <800000>;
146				regulator-max-microvolt = <900000>;
147				regulator-boot-on;
148				regulator-always-on;
149			};
150
151			ldo3_reg: LDO3 {
152				regulator-name = "ldo3";
153				regulator-min-microvolt = <1800000>;
154				regulator-max-microvolt = <3300000>;
155				regulator-boot-on;
156				regulator-always-on;
157			};
158
159			ldo4_reg: LDO4 {
160				regulator-name = "ldo4";
161				regulator-min-microvolt = <900000>;
162				regulator-max-microvolt = <1800000>;
163				regulator-boot-on;
164				regulator-always-on;
165			};
166
167			ldo5_reg: LDO5 {
168				regulator-name = "ldo5";
169				regulator-min-microvolt = <1800000>;
170				regulator-max-microvolt = <3300000>;
171			};
172
173			ldo6_reg: LDO6 {
174				regulator-name = "ldo6";
175				regulator-min-microvolt = <900000>;
176				regulator-max-microvolt = <1800000>;
177				regulator-boot-on;
178				regulator-always-on;
179			};
180		};
181	};
182};
183
184&i2c2 {
185	clock-frequency = <100000>;
186	pinctrl-names = "default", "gpio";
187	pinctrl-0 = <&pinctrl_i2c2>;
188	pinctrl-1 = <&pinctrl_i2c2_gpio>;
189	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
190	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
191	status = "okay";
192};
193
194&i2c3 {
195	pinctrl-names = "default", "gpio";
196	pinctrl-0 = <&pinctrl_i2c3>;
197	pinctrl-1 = <&pinctrl_i2c3_gpio>;
198	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
199	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
200};
201
202&pcie_phy {
203	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
204	fsl,tx-deemph-gen1 = <0x2d>;
205	fsl,tx-deemph-gen2 = <0xf>;
206	status = "okay";
207};
208
209&pcie0 {
210	pinctrl-names = "default";
211	pinctrl-0 = <&pinctrl_pcie0>;
212	reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
213	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>,
214		 <&clk IMX8MM_CLK_PCIE1_AUX>;
215	clock-names = "pcie", "pcie_bus", "pcie_aux";
216	fsl,max-link-speed = <1>;
217	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>;
218	assigned-clock-rates = <10000000>, <250000000>;
219	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>;
220	status = "okay";
221};
222
223&uart1 { /* BT */
224	pinctrl-names = "default";
225	pinctrl-0 = <&pinctrl_uart1>;
226	assigned-clocks = <&clk IMX8MM_CLK_UART1>;
227	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
228	uart-has-rtscts;
229	status = "okay";
230
231	bluetooth {
232		compatible = "brcm,bcm4349-bt";
233		pinctrl-names = "default";
234		pinctrl-0 = <&pinctrl_modem_bt>;
235		device-wakeup-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
236		host-wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
237		shutdown-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
238		vbat-supply = <&reg_3v3_out>;
239		vddio-supply = <&reg_3v3_out>;
240		clocks = <&osc_32k>;
241		max-speed = <3000000>;
242		clock-names = "extclk";
243	};
244};
245
246&uart2 { /* console */
247	pinctrl-names = "default";
248	pinctrl-0 = <&pinctrl_uart2>;
249};
250
251&usdhc1 {
252	pinctrl-names = "default";
253	pinctrl-0 = <&pinctrl_usdhc1>;
254	bus-width = <8>;
255	no-sd;
256	no-sdio;
257	non-removable;
258	status = "okay";
259};
260
261&usdhc2 {
262	pinctrl-names = "default", "state_100mhz", "state_200mhz";
263	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
264	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
265	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
266	bus-width = <4>;
267};
268
269&wdog1 {
270	pinctrl-names = "default";
271	pinctrl-0 = <&pinctrl_wdog>;
272	fsl,ext-reset-output;
273	status = "okay";
274};
275
276&A53_0 {
277	cpu-supply = <&buck2_reg>;
278};
279
280&A53_1 {
281	cpu-supply = <&buck2_reg>;
282};
283
284&A53_2 {
285	cpu-supply = <&buck2_reg>;
286};
287
288&A53_3 {
289	cpu-supply = <&buck2_reg>;
290};
291
292/delete-node/ &sec_jr1; /* Job ring in use by OP-TEE */
293
294&iomuxc {
295	pinctrl_i2c1: i2c1-grp {
296		fsl,pins = <
297			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL	0x400001c3
298			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA	0x400001c3
299		>;
300	};
301
302	pinctrl_i2c1_gpio: i2c1-gpio-grp {
303		fsl,pins = <
304			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
305			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
306		>;
307	};
308
309	pinctrl_i2c2: i2c2-grp {
310		fsl,pins = <
311			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL	0x400001c3
312			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA	0x400001c3
313		>;
314	};
315
316	pinctrl_i2c2_gpio: i2c2-gpio-grp {
317		fsl,pins = <
318			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3
319			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3
320		>;
321	};
322
323	pinctrl_i2c3: i2c3-grp {
324		fsl,pins = <
325			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
326			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
327		>;
328	};
329
330	pinctrl_i2c3_gpio: i2c3-gpio-grp {
331		fsl,pins = <
332			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3
333			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3
334		>;
335	};
336
337	pinctrl_pcie0: pcie0-grp {
338		fsl,pins = <
339			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B	0x61
340			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0x6
341		>;
342	};
343
344	pinctrl_modem_bt: modem-bt-grp {
345		fsl,pins = <
346			MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5			0x19
347			MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x19
348			MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x19
349			MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15		0x19
350			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x141
351		>;
352	};
353
354	pinctrl_modem_regulator: modem-reg-grp {
355		fsl,pins = <
356			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16    0x41
357		>;
358	};
359
360	pinctrl_pmic: pmic-irq-grp {
361		fsl,pins = <
362			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
363		>;
364	};
365
366	pinctrl_uart1: uart1-grp {
367		fsl,pins = <
368			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
369			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
370			MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
371			MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
372		>;
373	};
374
375	pinctrl_uart2: uart2-grp {
376		fsl,pins = <
377			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
378			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
379		>;
380	};
381
382	pinctrl_usdhc1: usdhc1-grp {
383		fsl,pins = <
384			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x40000190
385			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
386			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
387			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
388			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
389			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
390			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d0
391			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d0
392			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d0
393			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d0
394			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x190
395			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d0
396		>;
397	};
398
399	pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
400		fsl,pins = <
401			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x40000194
402			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
403			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
404			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
405			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
406			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
407			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d4
408			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d4
409			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d4
410			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d4
411			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x194
412			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d4
413		>;
414	};
415
416	pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
417		fsl,pins = <
418			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x40000196
419			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
420			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
421			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
422			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
423			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
424			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d6
425			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d6
426			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d6
427			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d6
428			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x196
429			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d6
430		>;
431	};
432
433	pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
434		fsl,pins = <
435			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x1d0
436		>;
437	};
438
439	pinctrl_usdhc2: usdhc2-grp {
440		fsl,pins = <
441			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
442			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
443			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
444			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
445			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
446			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
447			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
448		>;
449	};
450
451	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
452		fsl,pins = <
453			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
454			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
455			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
456			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
457			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
458			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
459			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
460		>;
461	};
462
463	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
464		fsl,pins = <
465			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
466			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
467			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
468			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
469			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
470			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
471			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
472		>;
473	};
474
475	pinctrl_wdog: wdog-grp {
476		fsl,pins = <
477			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
478		>;
479	};
480};
481