1*6cecf54dSJagan Teki// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*6cecf54dSJagan Teki/* 3*6cecf54dSJagan Teki * Copyright (c) 2019 NXP 4*6cecf54dSJagan Teki * Copyright (c) 2019 Engicam srl 5*6cecf54dSJagan Teki * Copyright (c) 2020 Amarula Solutions(India) 6*6cecf54dSJagan Teki */ 7*6cecf54dSJagan Teki 8*6cecf54dSJagan Teki/dts-v1/; 9*6cecf54dSJagan Teki#include "imx8mm.dtsi" 10*6cecf54dSJagan Teki#include "imx8mm-icore-mx8mm.dtsi" 11*6cecf54dSJagan Teki 12*6cecf54dSJagan Teki/ { 13*6cecf54dSJagan Teki model = "Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit"; 14*6cecf54dSJagan Teki compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm", 15*6cecf54dSJagan Teki "fsl,imx8mm"; 16*6cecf54dSJagan Teki 17*6cecf54dSJagan Teki chosen { 18*6cecf54dSJagan Teki stdout-path = &uart2; 19*6cecf54dSJagan Teki }; 20*6cecf54dSJagan Teki}; 21*6cecf54dSJagan Teki 22*6cecf54dSJagan Teki&fec1 { 23*6cecf54dSJagan Teki status = "okay"; 24*6cecf54dSJagan Teki}; 25*6cecf54dSJagan Teki 26*6cecf54dSJagan Teki&i2c2 { 27*6cecf54dSJagan Teki clock-frequency = <400000>; 28*6cecf54dSJagan Teki pinctrl-names = "default"; 29*6cecf54dSJagan Teki pinctrl-0 = <&pinctrl_i2c2>; 30*6cecf54dSJagan Teki status = "okay"; 31*6cecf54dSJagan Teki}; 32*6cecf54dSJagan Teki 33*6cecf54dSJagan Teki&i2c4 { 34*6cecf54dSJagan Teki clock-frequency = <100000>; 35*6cecf54dSJagan Teki pinctrl-names = "default"; 36*6cecf54dSJagan Teki pinctrl-0 = <&pinctrl_i2c4>; 37*6cecf54dSJagan Teki status = "okay"; 38*6cecf54dSJagan Teki}; 39*6cecf54dSJagan Teki 40*6cecf54dSJagan Teki&iomuxc { 41*6cecf54dSJagan Teki pinctrl_i2c2: i2c2grp { 42*6cecf54dSJagan Teki fsl,pins = < 43*6cecf54dSJagan Teki MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 44*6cecf54dSJagan Teki MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 45*6cecf54dSJagan Teki >; 46*6cecf54dSJagan Teki }; 47*6cecf54dSJagan Teki 48*6cecf54dSJagan Teki pinctrl_i2c4: i2c4grp { 49*6cecf54dSJagan Teki fsl,pins = < 50*6cecf54dSJagan Teki MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 51*6cecf54dSJagan Teki MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 52*6cecf54dSJagan Teki >; 53*6cecf54dSJagan Teki }; 54*6cecf54dSJagan Teki 55*6cecf54dSJagan Teki pinctrl_uart2: uart2grp { 56*6cecf54dSJagan Teki fsl,pins = < 57*6cecf54dSJagan Teki MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 58*6cecf54dSJagan Teki MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 59*6cecf54dSJagan Teki >; 60*6cecf54dSJagan Teki }; 61*6cecf54dSJagan Teki 62*6cecf54dSJagan Teki pinctrl_usdhc1_gpio: usdhc1gpiogrp { 63*6cecf54dSJagan Teki fsl,pins = < 64*6cecf54dSJagan Teki MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41 65*6cecf54dSJagan Teki >; 66*6cecf54dSJagan Teki }; 67*6cecf54dSJagan Teki 68*6cecf54dSJagan Teki pinctrl_usdhc1: usdhc1grp { 69*6cecf54dSJagan Teki fsl,pins = < 70*6cecf54dSJagan Teki MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 71*6cecf54dSJagan Teki MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 72*6cecf54dSJagan Teki MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 73*6cecf54dSJagan Teki MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 74*6cecf54dSJagan Teki MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 75*6cecf54dSJagan Teki MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 76*6cecf54dSJagan Teki >; 77*6cecf54dSJagan Teki }; 78*6cecf54dSJagan Teki}; 79*6cecf54dSJagan Teki 80*6cecf54dSJagan Teki&uart2 { 81*6cecf54dSJagan Teki pinctrl-names = "default"; 82*6cecf54dSJagan Teki pinctrl-0 = <&pinctrl_uart2>; 83*6cecf54dSJagan Teki status = "okay"; 84*6cecf54dSJagan Teki}; 85*6cecf54dSJagan Teki 86*6cecf54dSJagan Teki/* SD */ 87*6cecf54dSJagan Teki&usdhc1 { 88*6cecf54dSJagan Teki pinctrl-names = "default"; 89*6cecf54dSJagan Teki pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; 90*6cecf54dSJagan Teki cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 91*6cecf54dSJagan Teki max-frequency = <50000000>; 92*6cecf54dSJagan Teki bus-width = <4>; 93*6cecf54dSJagan Teki no-1-8-v; 94*6cecf54dSJagan Teki keep-power-in-suspend; 95*6cecf54dSJagan Teki status = "okay"; 96*6cecf54dSJagan Teki}; 97