1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9#include <dt-bindings/usb/pd.h>
10#include "imx8mm.dtsi"
11
12/ {
13	chosen {
14		stdout-path = &uart2;
15	};
16
17	memory@40000000 {
18		device_type = "memory";
19		reg = <0x0 0x40000000 0 0x80000000>;
20	};
21
22	leds {
23		compatible = "gpio-leds";
24		pinctrl-names = "default";
25		pinctrl-0 = <&pinctrl_gpio_led>;
26
27		status {
28			label = "status";
29			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
30			default-state = "on";
31		};
32	};
33
34	pcie0_refclk: pcie0-refclk {
35		compatible = "fixed-clock";
36		#clock-cells = <0>;
37		clock-frequency = <100000000>;
38	};
39
40	reg_pcie0: regulator-pcie {
41		compatible = "regulator-fixed";
42		pinctrl-names = "default";
43		pinctrl-0 = <&pinctrl_pcie0_reg>;
44		regulator-name = "MPCIE_3V3";
45		regulator-min-microvolt = <3300000>;
46		regulator-max-microvolt = <3300000>;
47		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
48		enable-active-high;
49	};
50
51	reg_usdhc2_vmmc: regulator-usdhc2 {
52		compatible = "regulator-fixed";
53		pinctrl-names = "default";
54		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
55		regulator-name = "VSD_3V3";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
59		enable-active-high;
60	};
61
62	backlight: backlight {
63		compatible = "pwm-backlight";
64		pwms = <&pwm1 0 5000000 0>;
65		brightness-levels = <0 255>;
66		num-interpolated-steps = <255>;
67		default-brightness-level = <250>;
68	};
69
70	ir-receiver {
71		compatible = "gpio-ir-receiver";
72		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
73		pinctrl-names = "default";
74		pinctrl-0 = <&pinctrl_ir>;
75		linux,autosuspend-period = <125>;
76	};
77
78	audio_codec_bt_sco: audio-codec-bt-sco {
79		compatible = "linux,bt-sco";
80		#sound-dai-cells = <1>;
81	};
82
83	wm8524: audio-codec {
84		#sound-dai-cells = <0>;
85		compatible = "wlf,wm8524";
86		pinctrl-names = "default";
87		pinctrl-0 = <&pinctrl_gpio_wlf>;
88		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
89	};
90
91	sound-bt-sco {
92		compatible = "simple-audio-card";
93		simple-audio-card,name = "bt-sco-audio";
94		simple-audio-card,format = "dsp_a";
95		simple-audio-card,bitclock-inversion;
96		simple-audio-card,frame-master = <&btcpu>;
97		simple-audio-card,bitclock-master = <&btcpu>;
98
99		btcpu: simple-audio-card,cpu {
100			sound-dai = <&sai2>;
101			dai-tdm-slot-num = <2>;
102			dai-tdm-slot-width = <16>;
103		};
104
105		simple-audio-card,codec {
106			sound-dai = <&audio_codec_bt_sco 1>;
107		};
108	};
109
110	sound-wm8524 {
111		compatible = "simple-audio-card";
112		simple-audio-card,name = "wm8524-audio";
113		simple-audio-card,format = "i2s";
114		simple-audio-card,frame-master = <&cpudai>;
115		simple-audio-card,bitclock-master = <&cpudai>;
116		simple-audio-card,widgets =
117			"Line", "Left Line Out Jack",
118			"Line", "Right Line Out Jack";
119		simple-audio-card,routing =
120			"Left Line Out Jack", "LINEVOUTL",
121			"Right Line Out Jack", "LINEVOUTR";
122
123		cpudai: simple-audio-card,cpu {
124			sound-dai = <&sai3>;
125			dai-tdm-slot-num = <2>;
126			dai-tdm-slot-width = <32>;
127		};
128
129		simple-audio-card,codec {
130			sound-dai = <&wm8524>;
131			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
132		};
133	};
134};
135
136&A53_0 {
137	cpu-supply = <&buck2_reg>;
138};
139
140&A53_1 {
141	cpu-supply = <&buck2_reg>;
142};
143
144&A53_2 {
145	cpu-supply = <&buck2_reg>;
146};
147
148&A53_3 {
149	cpu-supply = <&buck2_reg>;
150};
151
152&fec1 {
153	pinctrl-names = "default";
154	pinctrl-0 = <&pinctrl_fec1>;
155	phy-mode = "rgmii-id";
156	phy-handle = <&ethphy0>;
157	fsl,magic-packet;
158	status = "okay";
159
160	mdio {
161		#address-cells = <1>;
162		#size-cells = <0>;
163
164		ethphy0: ethernet-phy@0 {
165			compatible = "ethernet-phy-ieee802.3-c22";
166			reg = <0>;
167			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
168			reset-assert-us = <10000>;
169			qca,disable-smarteee;
170			vddio-supply = <&vddio>;
171
172			vddio: vddio-regulator {
173				regulator-min-microvolt = <1800000>;
174				regulator-max-microvolt = <1800000>;
175			};
176		};
177	};
178};
179
180&i2c1 {
181	clock-frequency = <400000>;
182	pinctrl-names = "default";
183	pinctrl-0 = <&pinctrl_i2c1>;
184	status = "okay";
185
186	pmic@4b {
187		compatible = "rohm,bd71847";
188		reg = <0x4b>;
189		pinctrl-names = "default";
190		pinctrl-0 = <&pinctrl_pmic>;
191		interrupt-parent = <&gpio1>;
192		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
193		rohm,reset-snvs-powered;
194
195		#clock-cells = <0>;
196		clocks = <&osc_32k 0>;
197		clock-output-names = "clk-32k-out";
198
199		regulators {
200			buck1_reg: BUCK1 {
201				regulator-name = "buck1";
202				regulator-min-microvolt = <700000>;
203				regulator-max-microvolt = <1300000>;
204				regulator-boot-on;
205				regulator-always-on;
206				regulator-ramp-delay = <1250>;
207			};
208
209			buck2_reg: BUCK2 {
210				regulator-name = "buck2";
211				regulator-min-microvolt = <700000>;
212				regulator-max-microvolt = <1300000>;
213				regulator-boot-on;
214				regulator-always-on;
215				regulator-ramp-delay = <1250>;
216				rohm,dvs-run-voltage = <1000000>;
217				rohm,dvs-idle-voltage = <900000>;
218			};
219
220			buck3_reg: BUCK3 {
221				// BUCK5 in datasheet
222				regulator-name = "buck3";
223				regulator-min-microvolt = <700000>;
224				regulator-max-microvolt = <1350000>;
225				regulator-boot-on;
226				regulator-always-on;
227			};
228
229			buck4_reg: BUCK4 {
230				// BUCK6 in datasheet
231				regulator-name = "buck4";
232				regulator-min-microvolt = <3000000>;
233				regulator-max-microvolt = <3300000>;
234				regulator-boot-on;
235				regulator-always-on;
236			};
237
238			buck5_reg: BUCK5 {
239				// BUCK7 in datasheet
240				regulator-name = "buck5";
241				regulator-min-microvolt = <1605000>;
242				regulator-max-microvolt = <1995000>;
243				regulator-boot-on;
244				regulator-always-on;
245			};
246
247			buck6_reg: BUCK6 {
248				// BUCK8 in datasheet
249				regulator-name = "buck6";
250				regulator-min-microvolt = <800000>;
251				regulator-max-microvolt = <1400000>;
252				regulator-boot-on;
253				regulator-always-on;
254			};
255
256			ldo1_reg: LDO1 {
257				regulator-name = "ldo1";
258				regulator-min-microvolt = <1600000>;
259				regulator-max-microvolt = <3300000>;
260				regulator-boot-on;
261				regulator-always-on;
262			};
263
264			ldo2_reg: LDO2 {
265				regulator-name = "ldo2";
266				regulator-min-microvolt = <800000>;
267				regulator-max-microvolt = <900000>;
268				regulator-boot-on;
269				regulator-always-on;
270			};
271
272			ldo3_reg: LDO3 {
273				regulator-name = "ldo3";
274				regulator-min-microvolt = <1800000>;
275				regulator-max-microvolt = <3300000>;
276				regulator-boot-on;
277				regulator-always-on;
278			};
279
280			ldo4_reg: LDO4 {
281				regulator-name = "ldo4";
282				regulator-min-microvolt = <900000>;
283				regulator-max-microvolt = <1800000>;
284				regulator-boot-on;
285				regulator-always-on;
286			};
287
288			ldo6_reg: LDO6 {
289				regulator-name = "ldo6";
290				regulator-min-microvolt = <900000>;
291				regulator-max-microvolt = <1800000>;
292				regulator-boot-on;
293				regulator-always-on;
294			};
295		};
296	};
297};
298
299&i2c2 {
300	clock-frequency = <400000>;
301	pinctrl-names = "default";
302	pinctrl-0 = <&pinctrl_i2c2>;
303	status = "okay";
304
305	ptn5110: tcpc@50 {
306		compatible = "nxp,ptn5110";
307		pinctrl-names = "default";
308		pinctrl-0 = <&pinctrl_typec1>;
309		reg = <0x50>;
310		interrupt-parent = <&gpio2>;
311		interrupts = <11 8>;
312		status = "okay";
313
314		port {
315			typec1_dr_sw: endpoint {
316				remote-endpoint = <&usb1_drd_sw>;
317			};
318		};
319
320		typec1_con: connector {
321			compatible = "usb-c-connector";
322			label = "USB-C";
323			power-role = "dual";
324			data-role = "dual";
325			try-power-role = "sink";
326			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
327			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
328				     PDO_VAR(5000, 20000, 3000)>;
329			op-sink-microwatt = <15000000>;
330			self-powered;
331		};
332	};
333};
334
335&i2c3 {
336	clock-frequency = <400000>;
337	pinctrl-names = "default";
338	pinctrl-0 = <&pinctrl_i2c3>;
339	status = "okay";
340
341	pca6416: gpio@20 {
342		compatible = "ti,tca6416";
343		reg = <0x20>;
344		gpio-controller;
345		#gpio-cells = <2>;
346	};
347};
348
349&pcie_phy {
350	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
351	fsl,tx-deemph-gen1 = <0x2d>;
352	fsl,tx-deemph-gen2 = <0xf>;
353	clocks = <&pcie0_refclk>;
354	status = "okay";
355};
356
357&pcie0 {
358	pinctrl-names = "default";
359	pinctrl-0 = <&pinctrl_pcie0>;
360	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
361	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
362		 <&pcie0_refclk>;
363	clock-names = "pcie", "pcie_aux", "pcie_bus";
364	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
365			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
366	assigned-clock-rates = <10000000>, <250000000>;
367	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
368				 <&clk IMX8MM_SYS_PLL2_250M>;
369	vpcie-supply = <&reg_pcie0>;
370	status = "okay";
371};
372
373&sai2 {
374	#sound-dai-cells = <0>;
375	pinctrl-names = "default";
376	pinctrl-0 = <&pinctrl_sai2>;
377	assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
378	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
379	assigned-clock-rates = <24576000>;
380	status = "okay";
381};
382
383&sai3 {
384	pinctrl-names = "default";
385	pinctrl-0 = <&pinctrl_sai3>;
386	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
387	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
388	assigned-clock-rates = <24576000>;
389	status = "okay";
390};
391
392&snvs_pwrkey {
393	status = "okay";
394};
395
396&uart2 { /* console */
397	pinctrl-names = "default";
398	pinctrl-0 = <&pinctrl_uart2>;
399	status = "okay";
400};
401
402&usbotg1 {
403	dr_mode = "otg";
404	hnp-disable;
405	srp-disable;
406	adp-disable;
407	usb-role-switch;
408	disable-over-current;
409	samsung,picophy-pre-emp-curr-control = <3>;
410	samsung,picophy-dc-vol-level-adjust = <7>;
411	status = "okay";
412
413	port {
414		usb1_drd_sw: endpoint {
415			remote-endpoint = <&typec1_dr_sw>;
416		};
417	};
418};
419
420&usdhc2 {
421	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
422	assigned-clock-rates = <200000000>;
423	pinctrl-names = "default", "state_100mhz", "state_200mhz";
424	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
425	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
426	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
427	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
428	bus-width = <4>;
429	vmmc-supply = <&reg_usdhc2_vmmc>;
430	status = "okay";
431};
432
433&wdog1 {
434	pinctrl-names = "default";
435	pinctrl-0 = <&pinctrl_wdog>;
436	fsl,ext-reset-output;
437	status = "okay";
438};
439
440&pwm1 {
441	pinctrl-names = "default";
442	pinctrl-0 = <&pinctrl_backlight>;
443	status = "okay";
444};
445
446&iomuxc {
447	pinctrl_fec1: fec1grp {
448		fsl,pins = <
449			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
450			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
451			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
452			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
453			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
454			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
455			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
456			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
457			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
458			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
459			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
460			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
461			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
462			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
463			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
464		>;
465	};
466
467	pinctrl_gpio_led: gpioledgrp {
468		fsl,pins = <
469			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
470		>;
471	};
472
473	pinctrl_ir: irgrp {
474		fsl,pins = <
475			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
476		>;
477	};
478
479	pinctrl_gpio_wlf: gpiowlfgrp {
480		fsl,pins = <
481			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
482		>;
483	};
484
485	pinctrl_i2c1: i2c1grp {
486		fsl,pins = <
487			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
488			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
489		>;
490	};
491
492	pinctrl_i2c2: i2c2grp {
493		fsl,pins = <
494			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
495			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
496		>;
497	};
498
499	pinctrl_i2c3: i2c3grp {
500		fsl,pins = <
501			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
502			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
503		>;
504	};
505
506	pinctrl_pcie0: pcie0grp {
507		fsl,pins = <
508			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61
509			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41
510		>;
511	};
512
513	pinctrl_pcie0_reg: pcie0reggrp {
514		fsl,pins = <
515			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x41
516		>;
517	};
518
519	pinctrl_pmic: pmicirqgrp {
520		fsl,pins = <
521			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141
522		>;
523	};
524
525	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
526		fsl,pins = <
527			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
528		>;
529	};
530
531	pinctrl_sai2: sai2grp {
532		fsl,pins = <
533			MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
534			MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
535			MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
536			MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6
537		>;
538	};
539
540	pinctrl_sai3: sai3grp {
541		fsl,pins = <
542			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
543			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
544			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
545			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
546		>;
547	};
548
549	pinctrl_typec1: typec1grp {
550		fsl,pins = <
551			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
552		>;
553	};
554
555	pinctrl_uart2: uart2grp {
556		fsl,pins = <
557			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
558			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
559		>;
560	};
561
562	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
563		fsl,pins = <
564			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
565		>;
566	};
567
568	pinctrl_usdhc2: usdhc2grp {
569		fsl,pins = <
570			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
571			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
572			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
573			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
574			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
575			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
576			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
577		>;
578	};
579
580	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
581		fsl,pins = <
582			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
583			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
584			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
585			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
586			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
587			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
588			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
589		>;
590	};
591
592	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
593		fsl,pins = <
594			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
595			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
596			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
597			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
598			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
599			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
600			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
601		>;
602	};
603
604	pinctrl_wdog: wdoggrp {
605		fsl,pins = <
606			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
607		>;
608	};
609
610	pinctrl_backlight: backlightgrp {
611		fsl,pins = <
612			MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT	0x06
613		>;
614	};
615};
616