1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9#include <dt-bindings/usb/pd.h>
10#include "imx8mm.dtsi"
11
12/ {
13	chosen {
14		stdout-path = &uart2;
15	};
16
17	memory@40000000 {
18		device_type = "memory";
19		reg = <0x0 0x40000000 0 0x80000000>;
20	};
21
22	leds {
23		compatible = "gpio-leds";
24		pinctrl-names = "default";
25		pinctrl-0 = <&pinctrl_gpio_led>;
26
27		status {
28			label = "status";
29			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
30			default-state = "on";
31		};
32	};
33
34	pcie0_refclk: pcie0-refclk {
35		compatible = "fixed-clock";
36		#clock-cells = <0>;
37		clock-frequency = <100000000>;
38	};
39
40	reg_pcie0: regulator-pcie {
41		compatible = "regulator-fixed";
42		pinctrl-names = "default";
43		pinctrl-0 = <&pinctrl_pcie0_reg>;
44		regulator-name = "MPCIE_3V3";
45		regulator-min-microvolt = <3300000>;
46		regulator-max-microvolt = <3300000>;
47		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
48		enable-active-high;
49	};
50
51	reg_usdhc2_vmmc: regulator-usdhc2 {
52		compatible = "regulator-fixed";
53		pinctrl-names = "default";
54		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
55		regulator-name = "VSD_3V3";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
59		enable-active-high;
60	};
61
62	ir-receiver {
63		compatible = "gpio-ir-receiver";
64		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
65		pinctrl-names = "default";
66		pinctrl-0 = <&pinctrl_ir>;
67		linux,autosuspend-period = <125>;
68	};
69
70	wm8524: audio-codec {
71		#sound-dai-cells = <0>;
72		compatible = "wlf,wm8524";
73		pinctrl-names = "default";
74		pinctrl-0 = <&pinctrl_gpio_wlf>;
75		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
76	};
77
78	sound-wm8524 {
79		compatible = "simple-audio-card";
80		simple-audio-card,name = "wm8524-audio";
81		simple-audio-card,format = "i2s";
82		simple-audio-card,frame-master = <&cpudai>;
83		simple-audio-card,bitclock-master = <&cpudai>;
84		simple-audio-card,widgets =
85			"Line", "Left Line Out Jack",
86			"Line", "Right Line Out Jack";
87		simple-audio-card,routing =
88			"Left Line Out Jack", "LINEVOUTL",
89			"Right Line Out Jack", "LINEVOUTR";
90
91		cpudai: simple-audio-card,cpu {
92			sound-dai = <&sai3>;
93			dai-tdm-slot-num = <2>;
94			dai-tdm-slot-width = <32>;
95		};
96
97		simple-audio-card,codec {
98			sound-dai = <&wm8524>;
99			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
100		};
101	};
102};
103
104&A53_0 {
105	cpu-supply = <&buck2_reg>;
106};
107
108&A53_1 {
109	cpu-supply = <&buck2_reg>;
110};
111
112&A53_2 {
113	cpu-supply = <&buck2_reg>;
114};
115
116&A53_3 {
117	cpu-supply = <&buck2_reg>;
118};
119
120&fec1 {
121	pinctrl-names = "default";
122	pinctrl-0 = <&pinctrl_fec1>;
123	phy-mode = "rgmii-id";
124	phy-handle = <&ethphy0>;
125	fsl,magic-packet;
126	status = "okay";
127
128	mdio {
129		#address-cells = <1>;
130		#size-cells = <0>;
131
132		ethphy0: ethernet-phy@0 {
133			compatible = "ethernet-phy-ieee802.3-c22";
134			reg = <0>;
135			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
136			reset-assert-us = <10000>;
137			qca,disable-smarteee;
138			vddio-supply = <&vddio>;
139
140			vddio: vddio-regulator {
141				regulator-min-microvolt = <1800000>;
142				regulator-max-microvolt = <1800000>;
143			};
144		};
145	};
146};
147
148&i2c1 {
149	clock-frequency = <400000>;
150	pinctrl-names = "default";
151	pinctrl-0 = <&pinctrl_i2c1>;
152	status = "okay";
153
154	pmic@4b {
155		compatible = "rohm,bd71847";
156		reg = <0x4b>;
157		pinctrl-names = "default";
158		pinctrl-0 = <&pinctrl_pmic>;
159		interrupt-parent = <&gpio1>;
160		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
161		rohm,reset-snvs-powered;
162
163		#clock-cells = <0>;
164		clocks = <&osc_32k 0>;
165		clock-output-names = "clk-32k-out";
166
167		regulators {
168			buck1_reg: BUCK1 {
169				regulator-name = "buck1";
170				regulator-min-microvolt = <700000>;
171				regulator-max-microvolt = <1300000>;
172				regulator-boot-on;
173				regulator-always-on;
174				regulator-ramp-delay = <1250>;
175			};
176
177			buck2_reg: BUCK2 {
178				regulator-name = "buck2";
179				regulator-min-microvolt = <700000>;
180				regulator-max-microvolt = <1300000>;
181				regulator-boot-on;
182				regulator-always-on;
183				regulator-ramp-delay = <1250>;
184				rohm,dvs-run-voltage = <1000000>;
185				rohm,dvs-idle-voltage = <900000>;
186			};
187
188			buck3_reg: BUCK3 {
189				// BUCK5 in datasheet
190				regulator-name = "buck3";
191				regulator-min-microvolt = <700000>;
192				regulator-max-microvolt = <1350000>;
193				regulator-boot-on;
194				regulator-always-on;
195			};
196
197			buck4_reg: BUCK4 {
198				// BUCK6 in datasheet
199				regulator-name = "buck4";
200				regulator-min-microvolt = <3000000>;
201				regulator-max-microvolt = <3300000>;
202				regulator-boot-on;
203				regulator-always-on;
204			};
205
206			buck5_reg: BUCK5 {
207				// BUCK7 in datasheet
208				regulator-name = "buck5";
209				regulator-min-microvolt = <1605000>;
210				regulator-max-microvolt = <1995000>;
211				regulator-boot-on;
212				regulator-always-on;
213			};
214
215			buck6_reg: BUCK6 {
216				// BUCK8 in datasheet
217				regulator-name = "buck6";
218				regulator-min-microvolt = <800000>;
219				regulator-max-microvolt = <1400000>;
220				regulator-boot-on;
221				regulator-always-on;
222			};
223
224			ldo1_reg: LDO1 {
225				regulator-name = "ldo1";
226				regulator-min-microvolt = <1600000>;
227				regulator-max-microvolt = <3300000>;
228				regulator-boot-on;
229				regulator-always-on;
230			};
231
232			ldo2_reg: LDO2 {
233				regulator-name = "ldo2";
234				regulator-min-microvolt = <800000>;
235				regulator-max-microvolt = <900000>;
236				regulator-boot-on;
237				regulator-always-on;
238			};
239
240			ldo3_reg: LDO3 {
241				regulator-name = "ldo3";
242				regulator-min-microvolt = <1800000>;
243				regulator-max-microvolt = <3300000>;
244				regulator-boot-on;
245				regulator-always-on;
246			};
247
248			ldo4_reg: LDO4 {
249				regulator-name = "ldo4";
250				regulator-min-microvolt = <900000>;
251				regulator-max-microvolt = <1800000>;
252				regulator-boot-on;
253				regulator-always-on;
254			};
255
256			ldo6_reg: LDO6 {
257				regulator-name = "ldo6";
258				regulator-min-microvolt = <900000>;
259				regulator-max-microvolt = <1800000>;
260				regulator-boot-on;
261				regulator-always-on;
262			};
263		};
264	};
265};
266
267&i2c2 {
268	clock-frequency = <400000>;
269	pinctrl-names = "default";
270	pinctrl-0 = <&pinctrl_i2c2>;
271	status = "okay";
272
273	ptn5110: tcpc@50 {
274		compatible = "nxp,ptn5110";
275		pinctrl-names = "default";
276		pinctrl-0 = <&pinctrl_typec1>;
277		reg = <0x50>;
278		interrupt-parent = <&gpio2>;
279		interrupts = <11 8>;
280		status = "okay";
281
282		port {
283			typec1_dr_sw: endpoint {
284				remote-endpoint = <&usb1_drd_sw>;
285			};
286		};
287
288		typec1_con: connector {
289			compatible = "usb-c-connector";
290			label = "USB-C";
291			power-role = "dual";
292			data-role = "dual";
293			try-power-role = "sink";
294			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
295			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
296				     PDO_VAR(5000, 20000, 3000)>;
297			op-sink-microwatt = <15000000>;
298			self-powered;
299		};
300	};
301};
302
303&i2c3 {
304	clock-frequency = <400000>;
305	pinctrl-names = "default";
306	pinctrl-0 = <&pinctrl_i2c3>;
307	status = "okay";
308
309	pca6416: gpio@20 {
310		compatible = "ti,tca6416";
311		reg = <0x20>;
312		gpio-controller;
313		#gpio-cells = <2>;
314	};
315};
316
317&pcie_phy {
318	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
319	fsl,tx-deemph-gen1 = <0x2d>;
320	fsl,tx-deemph-gen2 = <0xf>;
321	clocks = <&pcie0_refclk>;
322	status = "okay";
323};
324
325&pcie0 {
326	pinctrl-names = "default";
327	pinctrl-0 = <&pinctrl_pcie0>;
328	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
329	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
330		 <&pcie0_refclk>;
331	clock-names = "pcie", "pcie_aux", "pcie_bus";
332	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
333			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
334	assigned-clock-rates = <10000000>, <250000000>;
335	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
336				 <&clk IMX8MM_SYS_PLL2_250M>;
337	vpcie-supply = <&reg_pcie0>;
338	status = "okay";
339};
340
341&sai3 {
342	pinctrl-names = "default";
343	pinctrl-0 = <&pinctrl_sai3>;
344	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
345	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
346	assigned-clock-rates = <24576000>;
347	status = "okay";
348};
349
350&snvs_pwrkey {
351	status = "okay";
352};
353
354&uart2 { /* console */
355	pinctrl-names = "default";
356	pinctrl-0 = <&pinctrl_uart2>;
357	status = "okay";
358};
359
360&usbotg1 {
361	dr_mode = "otg";
362	hnp-disable;
363	srp-disable;
364	adp-disable;
365	usb-role-switch;
366	disable-over-current;
367	samsung,picophy-pre-emp-curr-control = <3>;
368	samsung,picophy-dc-vol-level-adjust = <7>;
369	status = "okay";
370
371	port {
372		usb1_drd_sw: endpoint {
373			remote-endpoint = <&typec1_dr_sw>;
374		};
375	};
376};
377
378&usdhc2 {
379	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
380	assigned-clock-rates = <200000000>;
381	pinctrl-names = "default", "state_100mhz", "state_200mhz";
382	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
383	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
384	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
385	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
386	bus-width = <4>;
387	vmmc-supply = <&reg_usdhc2_vmmc>;
388	status = "okay";
389};
390
391&wdog1 {
392	pinctrl-names = "default";
393	pinctrl-0 = <&pinctrl_wdog>;
394	fsl,ext-reset-output;
395	status = "okay";
396};
397
398&iomuxc {
399	pinctrl_fec1: fec1grp {
400		fsl,pins = <
401			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
402			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
403			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
404			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
405			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
406			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
407			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
408			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
409			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
410			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
411			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
412			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
413			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
414			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
415			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
416		>;
417	};
418
419	pinctrl_gpio_led: gpioledgrp {
420		fsl,pins = <
421			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
422		>;
423	};
424
425	pinctrl_ir: irgrp {
426		fsl,pins = <
427			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
428		>;
429	};
430
431	pinctrl_gpio_wlf: gpiowlfgrp {
432		fsl,pins = <
433			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
434		>;
435	};
436
437	pinctrl_i2c1: i2c1grp {
438		fsl,pins = <
439			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
440			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
441		>;
442	};
443
444	pinctrl_i2c2: i2c2grp {
445		fsl,pins = <
446			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
447			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
448		>;
449	};
450
451	pinctrl_i2c3: i2c3grp {
452		fsl,pins = <
453			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
454			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
455		>;
456	};
457
458	pinctrl_pcie0: pcie0grp {
459		fsl,pins = <
460			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61
461			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41
462		>;
463	};
464
465	pinctrl_pcie0_reg: pcie0reggrp {
466		fsl,pins = <
467			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x41
468		>;
469	};
470
471	pinctrl_pmic: pmicirqgrp {
472		fsl,pins = <
473			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141
474		>;
475	};
476
477	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
478		fsl,pins = <
479			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
480		>;
481	};
482
483	pinctrl_sai3: sai3grp {
484		fsl,pins = <
485			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
486			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
487			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
488			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
489		>;
490	};
491
492	pinctrl_typec1: typec1grp {
493		fsl,pins = <
494			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
495		>;
496	};
497
498	pinctrl_uart2: uart2grp {
499		fsl,pins = <
500			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
501			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
502		>;
503	};
504
505	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
506		fsl,pins = <
507			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
508		>;
509	};
510
511	pinctrl_usdhc2: usdhc2grp {
512		fsl,pins = <
513			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
514			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
515			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
516			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
517			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
518			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
519			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
520		>;
521	};
522
523	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
524		fsl,pins = <
525			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
526			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
527			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
528			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
529			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
530			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
531			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
532		>;
533	};
534
535	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
536		fsl,pins = <
537			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
538			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
539			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
540			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
541			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
542			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
543			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
544		>;
545	};
546
547	pinctrl_wdog: wdoggrp {
548		fsl,pins = <
549			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
550		>;
551	};
552};
553