1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9#include <dt-bindings/usb/pd.h>
10#include "imx8mm.dtsi"
11
12/ {
13	chosen {
14		stdout-path = &uart2;
15	};
16
17	memory@40000000 {
18		device_type = "memory";
19		reg = <0x0 0x40000000 0 0x80000000>;
20	};
21
22	leds {
23		compatible = "gpio-leds";
24		pinctrl-names = "default";
25		pinctrl-0 = <&pinctrl_gpio_led>;
26
27		status {
28			label = "status";
29			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
30			default-state = "on";
31		};
32	};
33
34	pcie0_refclk: pcie0-refclk {
35		compatible = "fixed-clock";
36		#clock-cells = <0>;
37		clock-frequency = <100000000>;
38	};
39
40	reg_pcie0: regulator-pcie {
41		compatible = "regulator-fixed";
42		pinctrl-names = "default";
43		pinctrl-0 = <&pinctrl_pcie0_reg>;
44		regulator-name = "MPCIE_3V3";
45		regulator-min-microvolt = <3300000>;
46		regulator-max-microvolt = <3300000>;
47		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
48		enable-active-high;
49	};
50
51	reg_usdhc2_vmmc: regulator-usdhc2 {
52		compatible = "regulator-fixed";
53		pinctrl-names = "default";
54		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
55		regulator-name = "VSD_3V3";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
59		enable-active-high;
60	};
61
62	backlight: backlight {
63		compatible = "pwm-backlight";
64		pwms = <&pwm1 0 5000000 0>;
65		brightness-levels = <0 255>;
66		num-interpolated-steps = <255>;
67		default-brightness-level = <250>;
68	};
69
70	ir-receiver {
71		compatible = "gpio-ir-receiver";
72		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
73		pinctrl-names = "default";
74		pinctrl-0 = <&pinctrl_ir>;
75		linux,autosuspend-period = <125>;
76	};
77
78	wm8524: audio-codec {
79		#sound-dai-cells = <0>;
80		compatible = "wlf,wm8524";
81		pinctrl-names = "default";
82		pinctrl-0 = <&pinctrl_gpio_wlf>;
83		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
84	};
85
86	sound-wm8524 {
87		compatible = "simple-audio-card";
88		simple-audio-card,name = "wm8524-audio";
89		simple-audio-card,format = "i2s";
90		simple-audio-card,frame-master = <&cpudai>;
91		simple-audio-card,bitclock-master = <&cpudai>;
92		simple-audio-card,widgets =
93			"Line", "Left Line Out Jack",
94			"Line", "Right Line Out Jack";
95		simple-audio-card,routing =
96			"Left Line Out Jack", "LINEVOUTL",
97			"Right Line Out Jack", "LINEVOUTR";
98
99		cpudai: simple-audio-card,cpu {
100			sound-dai = <&sai3>;
101			dai-tdm-slot-num = <2>;
102			dai-tdm-slot-width = <32>;
103		};
104
105		simple-audio-card,codec {
106			sound-dai = <&wm8524>;
107			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
108		};
109	};
110};
111
112&A53_0 {
113	cpu-supply = <&buck2_reg>;
114};
115
116&A53_1 {
117	cpu-supply = <&buck2_reg>;
118};
119
120&A53_2 {
121	cpu-supply = <&buck2_reg>;
122};
123
124&A53_3 {
125	cpu-supply = <&buck2_reg>;
126};
127
128&fec1 {
129	pinctrl-names = "default";
130	pinctrl-0 = <&pinctrl_fec1>;
131	phy-mode = "rgmii-id";
132	phy-handle = <&ethphy0>;
133	fsl,magic-packet;
134	status = "okay";
135
136	mdio {
137		#address-cells = <1>;
138		#size-cells = <0>;
139
140		ethphy0: ethernet-phy@0 {
141			compatible = "ethernet-phy-ieee802.3-c22";
142			reg = <0>;
143			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
144			reset-assert-us = <10000>;
145			qca,disable-smarteee;
146			vddio-supply = <&vddio>;
147
148			vddio: vddio-regulator {
149				regulator-min-microvolt = <1800000>;
150				regulator-max-microvolt = <1800000>;
151			};
152		};
153	};
154};
155
156&i2c1 {
157	clock-frequency = <400000>;
158	pinctrl-names = "default";
159	pinctrl-0 = <&pinctrl_i2c1>;
160	status = "okay";
161
162	pmic@4b {
163		compatible = "rohm,bd71847";
164		reg = <0x4b>;
165		pinctrl-names = "default";
166		pinctrl-0 = <&pinctrl_pmic>;
167		interrupt-parent = <&gpio1>;
168		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
169		rohm,reset-snvs-powered;
170
171		#clock-cells = <0>;
172		clocks = <&osc_32k 0>;
173		clock-output-names = "clk-32k-out";
174
175		regulators {
176			buck1_reg: BUCK1 {
177				regulator-name = "buck1";
178				regulator-min-microvolt = <700000>;
179				regulator-max-microvolt = <1300000>;
180				regulator-boot-on;
181				regulator-always-on;
182				regulator-ramp-delay = <1250>;
183			};
184
185			buck2_reg: BUCK2 {
186				regulator-name = "buck2";
187				regulator-min-microvolt = <700000>;
188				regulator-max-microvolt = <1300000>;
189				regulator-boot-on;
190				regulator-always-on;
191				regulator-ramp-delay = <1250>;
192				rohm,dvs-run-voltage = <1000000>;
193				rohm,dvs-idle-voltage = <900000>;
194			};
195
196			buck3_reg: BUCK3 {
197				// BUCK5 in datasheet
198				regulator-name = "buck3";
199				regulator-min-microvolt = <700000>;
200				regulator-max-microvolt = <1350000>;
201				regulator-boot-on;
202				regulator-always-on;
203			};
204
205			buck4_reg: BUCK4 {
206				// BUCK6 in datasheet
207				regulator-name = "buck4";
208				regulator-min-microvolt = <3000000>;
209				regulator-max-microvolt = <3300000>;
210				regulator-boot-on;
211				regulator-always-on;
212			};
213
214			buck5_reg: BUCK5 {
215				// BUCK7 in datasheet
216				regulator-name = "buck5";
217				regulator-min-microvolt = <1605000>;
218				regulator-max-microvolt = <1995000>;
219				regulator-boot-on;
220				regulator-always-on;
221			};
222
223			buck6_reg: BUCK6 {
224				// BUCK8 in datasheet
225				regulator-name = "buck6";
226				regulator-min-microvolt = <800000>;
227				regulator-max-microvolt = <1400000>;
228				regulator-boot-on;
229				regulator-always-on;
230			};
231
232			ldo1_reg: LDO1 {
233				regulator-name = "ldo1";
234				regulator-min-microvolt = <1600000>;
235				regulator-max-microvolt = <3300000>;
236				regulator-boot-on;
237				regulator-always-on;
238			};
239
240			ldo2_reg: LDO2 {
241				regulator-name = "ldo2";
242				regulator-min-microvolt = <800000>;
243				regulator-max-microvolt = <900000>;
244				regulator-boot-on;
245				regulator-always-on;
246			};
247
248			ldo3_reg: LDO3 {
249				regulator-name = "ldo3";
250				regulator-min-microvolt = <1800000>;
251				regulator-max-microvolt = <3300000>;
252				regulator-boot-on;
253				regulator-always-on;
254			};
255
256			ldo4_reg: LDO4 {
257				regulator-name = "ldo4";
258				regulator-min-microvolt = <900000>;
259				regulator-max-microvolt = <1800000>;
260				regulator-boot-on;
261				regulator-always-on;
262			};
263
264			ldo6_reg: LDO6 {
265				regulator-name = "ldo6";
266				regulator-min-microvolt = <900000>;
267				regulator-max-microvolt = <1800000>;
268				regulator-boot-on;
269				regulator-always-on;
270			};
271		};
272	};
273};
274
275&i2c2 {
276	clock-frequency = <400000>;
277	pinctrl-names = "default";
278	pinctrl-0 = <&pinctrl_i2c2>;
279	status = "okay";
280
281	ptn5110: tcpc@50 {
282		compatible = "nxp,ptn5110";
283		pinctrl-names = "default";
284		pinctrl-0 = <&pinctrl_typec1>;
285		reg = <0x50>;
286		interrupt-parent = <&gpio2>;
287		interrupts = <11 8>;
288		status = "okay";
289
290		port {
291			typec1_dr_sw: endpoint {
292				remote-endpoint = <&usb1_drd_sw>;
293			};
294		};
295
296		typec1_con: connector {
297			compatible = "usb-c-connector";
298			label = "USB-C";
299			power-role = "dual";
300			data-role = "dual";
301			try-power-role = "sink";
302			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
303			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
304				     PDO_VAR(5000, 20000, 3000)>;
305			op-sink-microwatt = <15000000>;
306			self-powered;
307		};
308	};
309};
310
311&i2c3 {
312	clock-frequency = <400000>;
313	pinctrl-names = "default";
314	pinctrl-0 = <&pinctrl_i2c3>;
315	status = "okay";
316
317	pca6416: gpio@20 {
318		compatible = "ti,tca6416";
319		reg = <0x20>;
320		gpio-controller;
321		#gpio-cells = <2>;
322	};
323};
324
325&pcie_phy {
326	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
327	fsl,tx-deemph-gen1 = <0x2d>;
328	fsl,tx-deemph-gen2 = <0xf>;
329	clocks = <&pcie0_refclk>;
330	status = "okay";
331};
332
333&pcie0 {
334	pinctrl-names = "default";
335	pinctrl-0 = <&pinctrl_pcie0>;
336	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
337	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
338		 <&pcie0_refclk>;
339	clock-names = "pcie", "pcie_aux", "pcie_bus";
340	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
341			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
342	assigned-clock-rates = <10000000>, <250000000>;
343	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
344				 <&clk IMX8MM_SYS_PLL2_250M>;
345	vpcie-supply = <&reg_pcie0>;
346	status = "okay";
347};
348
349&sai3 {
350	pinctrl-names = "default";
351	pinctrl-0 = <&pinctrl_sai3>;
352	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
353	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
354	assigned-clock-rates = <24576000>;
355	status = "okay";
356};
357
358&snvs_pwrkey {
359	status = "okay";
360};
361
362&uart2 { /* console */
363	pinctrl-names = "default";
364	pinctrl-0 = <&pinctrl_uart2>;
365	status = "okay";
366};
367
368&usbotg1 {
369	dr_mode = "otg";
370	hnp-disable;
371	srp-disable;
372	adp-disable;
373	usb-role-switch;
374	disable-over-current;
375	samsung,picophy-pre-emp-curr-control = <3>;
376	samsung,picophy-dc-vol-level-adjust = <7>;
377	status = "okay";
378
379	port {
380		usb1_drd_sw: endpoint {
381			remote-endpoint = <&typec1_dr_sw>;
382		};
383	};
384};
385
386&usdhc2 {
387	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
388	assigned-clock-rates = <200000000>;
389	pinctrl-names = "default", "state_100mhz", "state_200mhz";
390	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
391	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
392	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
393	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
394	bus-width = <4>;
395	vmmc-supply = <&reg_usdhc2_vmmc>;
396	status = "okay";
397};
398
399&wdog1 {
400	pinctrl-names = "default";
401	pinctrl-0 = <&pinctrl_wdog>;
402	fsl,ext-reset-output;
403	status = "okay";
404};
405
406&pwm1 {
407	pinctrl-names = "default";
408	pinctrl-0 = <&pinctrl_backlight>;
409	status = "okay";
410};
411
412&iomuxc {
413	pinctrl_fec1: fec1grp {
414		fsl,pins = <
415			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
416			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
417			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
418			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
419			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
420			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
421			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
422			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
423			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
424			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
425			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
426			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
427			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
428			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
429			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
430		>;
431	};
432
433	pinctrl_gpio_led: gpioledgrp {
434		fsl,pins = <
435			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
436		>;
437	};
438
439	pinctrl_ir: irgrp {
440		fsl,pins = <
441			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
442		>;
443	};
444
445	pinctrl_gpio_wlf: gpiowlfgrp {
446		fsl,pins = <
447			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
448		>;
449	};
450
451	pinctrl_i2c1: i2c1grp {
452		fsl,pins = <
453			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
454			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
455		>;
456	};
457
458	pinctrl_i2c2: i2c2grp {
459		fsl,pins = <
460			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
461			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
462		>;
463	};
464
465	pinctrl_i2c3: i2c3grp {
466		fsl,pins = <
467			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
468			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
469		>;
470	};
471
472	pinctrl_pcie0: pcie0grp {
473		fsl,pins = <
474			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61
475			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41
476		>;
477	};
478
479	pinctrl_pcie0_reg: pcie0reggrp {
480		fsl,pins = <
481			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x41
482		>;
483	};
484
485	pinctrl_pmic: pmicirqgrp {
486		fsl,pins = <
487			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141
488		>;
489	};
490
491	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
492		fsl,pins = <
493			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
494		>;
495	};
496
497	pinctrl_sai3: sai3grp {
498		fsl,pins = <
499			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
500			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
501			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
502			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
503		>;
504	};
505
506	pinctrl_typec1: typec1grp {
507		fsl,pins = <
508			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
509		>;
510	};
511
512	pinctrl_uart2: uart2grp {
513		fsl,pins = <
514			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
515			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
516		>;
517	};
518
519	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
520		fsl,pins = <
521			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
522		>;
523	};
524
525	pinctrl_usdhc2: usdhc2grp {
526		fsl,pins = <
527			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
528			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
529			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
530			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
531			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
532			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
533			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
534		>;
535	};
536
537	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
538		fsl,pins = <
539			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
540			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
541			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
542			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
543			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
544			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
545			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
546		>;
547	};
548
549	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
550		fsl,pins = <
551			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
552			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
553			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
554			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
555			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
556			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
557			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
558		>;
559	};
560
561	pinctrl_wdog: wdoggrp {
562		fsl,pins = <
563			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
564		>;
565	};
566
567	pinctrl_backlight: backlightgrp {
568		fsl,pins = <
569			MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT	0x06
570		>;
571	};
572};
573