1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9#include <dt-bindings/usb/pd.h>
10#include "imx8mm.dtsi"
11
12/ {
13	chosen {
14		stdout-path = &uart2;
15	};
16
17	memory@40000000 {
18		device_type = "memory";
19		reg = <0x0 0x40000000 0 0x80000000>;
20	};
21
22	leds {
23		compatible = "gpio-leds";
24		pinctrl-names = "default";
25		pinctrl-0 = <&pinctrl_gpio_led>;
26
27		status {
28			label = "status";
29			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
30			default-state = "on";
31		};
32	};
33
34	pcie0_refclk: pcie0-refclk {
35		compatible = "fixed-clock";
36		#clock-cells = <0>;
37		clock-frequency = <100000000>;
38	};
39
40	reg_pcie0: regulator-pcie {
41		compatible = "regulator-fixed";
42		pinctrl-names = "default";
43		pinctrl-0 = <&pinctrl_pcie0_reg>;
44		regulator-name = "MPCIE_3V3";
45		regulator-min-microvolt = <3300000>;
46		regulator-max-microvolt = <3300000>;
47		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
48		enable-active-high;
49	};
50
51	reg_usdhc2_vmmc: regulator-usdhc2 {
52		compatible = "regulator-fixed";
53		pinctrl-names = "default";
54		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
55		regulator-name = "VSD_3V3";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
59		off-on-delay-us = <20000>;
60		enable-active-high;
61	};
62
63	backlight: backlight {
64		compatible = "pwm-backlight";
65		pwms = <&pwm1 0 5000000 0>;
66		brightness-levels = <0 255>;
67		num-interpolated-steps = <255>;
68		default-brightness-level = <250>;
69	};
70
71	ir-receiver {
72		compatible = "gpio-ir-receiver";
73		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
74		pinctrl-names = "default";
75		pinctrl-0 = <&pinctrl_ir>;
76		linux,autosuspend-period = <125>;
77	};
78
79	audio_codec_bt_sco: audio-codec-bt-sco {
80		compatible = "linux,bt-sco";
81		#sound-dai-cells = <1>;
82	};
83
84	wm8524: audio-codec {
85		#sound-dai-cells = <0>;
86		compatible = "wlf,wm8524";
87		pinctrl-names = "default";
88		pinctrl-0 = <&pinctrl_gpio_wlf>;
89		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
90	};
91
92	sound-bt-sco {
93		compatible = "simple-audio-card";
94		simple-audio-card,name = "bt-sco-audio";
95		simple-audio-card,format = "dsp_a";
96		simple-audio-card,bitclock-inversion;
97		simple-audio-card,frame-master = <&btcpu>;
98		simple-audio-card,bitclock-master = <&btcpu>;
99
100		btcpu: simple-audio-card,cpu {
101			sound-dai = <&sai2>;
102			dai-tdm-slot-num = <2>;
103			dai-tdm-slot-width = <16>;
104		};
105
106		simple-audio-card,codec {
107			sound-dai = <&audio_codec_bt_sco 1>;
108		};
109	};
110
111	sound-wm8524 {
112		compatible = "simple-audio-card";
113		simple-audio-card,name = "wm8524-audio";
114		simple-audio-card,format = "i2s";
115		simple-audio-card,frame-master = <&cpudai>;
116		simple-audio-card,bitclock-master = <&cpudai>;
117		simple-audio-card,widgets =
118			"Line", "Left Line Out Jack",
119			"Line", "Right Line Out Jack";
120		simple-audio-card,routing =
121			"Left Line Out Jack", "LINEVOUTL",
122			"Right Line Out Jack", "LINEVOUTR";
123
124		cpudai: simple-audio-card,cpu {
125			sound-dai = <&sai3>;
126			dai-tdm-slot-num = <2>;
127			dai-tdm-slot-width = <32>;
128		};
129
130		simple-audio-card,codec {
131			sound-dai = <&wm8524>;
132			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
133		};
134	};
135};
136
137&A53_0 {
138	cpu-supply = <&buck2_reg>;
139};
140
141&A53_1 {
142	cpu-supply = <&buck2_reg>;
143};
144
145&A53_2 {
146	cpu-supply = <&buck2_reg>;
147};
148
149&A53_3 {
150	cpu-supply = <&buck2_reg>;
151};
152
153&fec1 {
154	pinctrl-names = "default";
155	pinctrl-0 = <&pinctrl_fec1>;
156	phy-mode = "rgmii-id";
157	phy-handle = <&ethphy0>;
158	fsl,magic-packet;
159	status = "okay";
160
161	mdio {
162		#address-cells = <1>;
163		#size-cells = <0>;
164
165		ethphy0: ethernet-phy@0 {
166			compatible = "ethernet-phy-ieee802.3-c22";
167			reg = <0>;
168			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
169			reset-assert-us = <10000>;
170			qca,disable-smarteee;
171			vddio-supply = <&vddio>;
172
173			vddio: vddio-regulator {
174				regulator-min-microvolt = <1800000>;
175				regulator-max-microvolt = <1800000>;
176			};
177		};
178	};
179};
180
181&i2c1 {
182	clock-frequency = <400000>;
183	pinctrl-names = "default";
184	pinctrl-0 = <&pinctrl_i2c1>;
185	status = "okay";
186
187	pmic@4b {
188		compatible = "rohm,bd71847";
189		reg = <0x4b>;
190		pinctrl-names = "default";
191		pinctrl-0 = <&pinctrl_pmic>;
192		interrupt-parent = <&gpio1>;
193		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
194		rohm,reset-snvs-powered;
195
196		#clock-cells = <0>;
197		clocks = <&osc_32k>;
198		clock-output-names = "clk-32k-out";
199
200		regulators {
201			buck1_reg: BUCK1 {
202				regulator-name = "buck1";
203				regulator-min-microvolt = <700000>;
204				regulator-max-microvolt = <1300000>;
205				regulator-boot-on;
206				regulator-always-on;
207				regulator-ramp-delay = <1250>;
208			};
209
210			buck2_reg: BUCK2 {
211				regulator-name = "buck2";
212				regulator-min-microvolt = <700000>;
213				regulator-max-microvolt = <1300000>;
214				regulator-boot-on;
215				regulator-always-on;
216				regulator-ramp-delay = <1250>;
217				rohm,dvs-run-voltage = <1000000>;
218				rohm,dvs-idle-voltage = <900000>;
219			};
220
221			buck3_reg: BUCK3 {
222				// BUCK5 in datasheet
223				regulator-name = "buck3";
224				regulator-min-microvolt = <700000>;
225				regulator-max-microvolt = <1350000>;
226				regulator-boot-on;
227				regulator-always-on;
228			};
229
230			buck4_reg: BUCK4 {
231				// BUCK6 in datasheet
232				regulator-name = "buck4";
233				regulator-min-microvolt = <3000000>;
234				regulator-max-microvolt = <3300000>;
235				regulator-boot-on;
236				regulator-always-on;
237			};
238
239			buck5_reg: BUCK5 {
240				// BUCK7 in datasheet
241				regulator-name = "buck5";
242				regulator-min-microvolt = <1605000>;
243				regulator-max-microvolt = <1995000>;
244				regulator-boot-on;
245				regulator-always-on;
246			};
247
248			buck6_reg: BUCK6 {
249				// BUCK8 in datasheet
250				regulator-name = "buck6";
251				regulator-min-microvolt = <800000>;
252				regulator-max-microvolt = <1400000>;
253				regulator-boot-on;
254				regulator-always-on;
255			};
256
257			ldo1_reg: LDO1 {
258				regulator-name = "ldo1";
259				regulator-min-microvolt = <1600000>;
260				regulator-max-microvolt = <3300000>;
261				regulator-boot-on;
262				regulator-always-on;
263			};
264
265			ldo2_reg: LDO2 {
266				regulator-name = "ldo2";
267				regulator-min-microvolt = <800000>;
268				regulator-max-microvolt = <900000>;
269				regulator-boot-on;
270				regulator-always-on;
271			};
272
273			ldo3_reg: LDO3 {
274				regulator-name = "ldo3";
275				regulator-min-microvolt = <1800000>;
276				regulator-max-microvolt = <3300000>;
277				regulator-boot-on;
278				regulator-always-on;
279			};
280
281			ldo4_reg: LDO4 {
282				regulator-name = "ldo4";
283				regulator-min-microvolt = <900000>;
284				regulator-max-microvolt = <1800000>;
285				regulator-boot-on;
286				regulator-always-on;
287			};
288
289			ldo6_reg: LDO6 {
290				regulator-name = "ldo6";
291				regulator-min-microvolt = <900000>;
292				regulator-max-microvolt = <1800000>;
293				regulator-boot-on;
294				regulator-always-on;
295			};
296		};
297	};
298};
299
300&i2c2 {
301	clock-frequency = <400000>;
302	pinctrl-names = "default";
303	pinctrl-0 = <&pinctrl_i2c2>;
304	status = "okay";
305
306	ptn5110: tcpc@50 {
307		compatible = "nxp,ptn5110";
308		pinctrl-names = "default";
309		pinctrl-0 = <&pinctrl_typec1>;
310		reg = <0x50>;
311		interrupt-parent = <&gpio2>;
312		interrupts = <11 8>;
313		status = "okay";
314
315		port {
316			typec1_dr_sw: endpoint {
317				remote-endpoint = <&usb1_drd_sw>;
318			};
319		};
320
321		typec1_con: connector {
322			compatible = "usb-c-connector";
323			label = "USB-C";
324			power-role = "dual";
325			data-role = "dual";
326			try-power-role = "sink";
327			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
328			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
329				     PDO_VAR(5000, 20000, 3000)>;
330			op-sink-microwatt = <15000000>;
331			self-powered;
332		};
333	};
334};
335
336&i2c3 {
337	clock-frequency = <400000>;
338	pinctrl-names = "default";
339	pinctrl-0 = <&pinctrl_i2c3>;
340	status = "okay";
341
342	pca6416: gpio@20 {
343		compatible = "nxp,pca6416";
344		reg = <0x20>;
345		gpio-controller;
346		#gpio-cells = <2>;
347		vcc-supply = <&buck4_reg>;
348	};
349};
350
351&pcie_phy {
352	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
353	fsl,tx-deemph-gen1 = <0x2d>;
354	fsl,tx-deemph-gen2 = <0xf>;
355	clocks = <&pcie0_refclk>;
356	status = "okay";
357};
358
359&pcie0 {
360	pinctrl-names = "default";
361	pinctrl-0 = <&pinctrl_pcie0>;
362	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
363	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
364		 <&clk IMX8MM_CLK_PCIE1_AUX>;
365	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
366			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
367	assigned-clock-rates = <10000000>, <250000000>;
368	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
369				 <&clk IMX8MM_SYS_PLL2_250M>;
370	vpcie-supply = <&reg_pcie0>;
371	status = "okay";
372};
373
374&sai2 {
375	#sound-dai-cells = <0>;
376	pinctrl-names = "default";
377	pinctrl-0 = <&pinctrl_sai2>;
378	assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
379	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
380	assigned-clock-rates = <24576000>;
381	status = "okay";
382};
383
384&sai3 {
385	pinctrl-names = "default";
386	pinctrl-0 = <&pinctrl_sai3>;
387	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
388	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
389	assigned-clock-rates = <24576000>;
390	status = "okay";
391};
392
393&snvs_pwrkey {
394	status = "okay";
395};
396
397&uart2 { /* console */
398	pinctrl-names = "default";
399	pinctrl-0 = <&pinctrl_uart2>;
400	status = "okay";
401};
402
403&usbphynop1 {
404	wakeup-source;
405};
406
407&usbotg1 {
408	dr_mode = "otg";
409	hnp-disable;
410	srp-disable;
411	adp-disable;
412	usb-role-switch;
413	disable-over-current;
414	samsung,picophy-pre-emp-curr-control = <3>;
415	samsung,picophy-dc-vol-level-adjust = <7>;
416	status = "okay";
417
418	port {
419		usb1_drd_sw: endpoint {
420			remote-endpoint = <&typec1_dr_sw>;
421		};
422	};
423};
424
425&usdhc2 {
426	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
427	assigned-clock-rates = <200000000>;
428	pinctrl-names = "default", "state_100mhz", "state_200mhz";
429	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
430	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
431	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
432	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
433	bus-width = <4>;
434	vmmc-supply = <&reg_usdhc2_vmmc>;
435	status = "okay";
436};
437
438&wdog1 {
439	pinctrl-names = "default";
440	pinctrl-0 = <&pinctrl_wdog>;
441	fsl,ext-reset-output;
442	status = "okay";
443};
444
445&pwm1 {
446	pinctrl-names = "default";
447	pinctrl-0 = <&pinctrl_backlight>;
448	status = "okay";
449};
450
451&iomuxc {
452	pinctrl_fec1: fec1grp {
453		fsl,pins = <
454			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
455			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
456			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
457			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
458			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
459			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
460			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
461			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
462			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
463			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
464			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
465			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
466			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
467			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
468			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
469		>;
470	};
471
472	pinctrl_gpio_led: gpioledgrp {
473		fsl,pins = <
474			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
475		>;
476	};
477
478	pinctrl_ir: irgrp {
479		fsl,pins = <
480			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
481		>;
482	};
483
484	pinctrl_gpio_wlf: gpiowlfgrp {
485		fsl,pins = <
486			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
487		>;
488	};
489
490	pinctrl_i2c1: i2c1grp {
491		fsl,pins = <
492			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
493			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
494		>;
495	};
496
497	pinctrl_i2c2: i2c2grp {
498		fsl,pins = <
499			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
500			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
501		>;
502	};
503
504	pinctrl_i2c3: i2c3grp {
505		fsl,pins = <
506			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
507			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
508		>;
509	};
510
511	pinctrl_pcie0: pcie0grp {
512		fsl,pins = <
513			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61
514			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41
515		>;
516	};
517
518	pinctrl_pcie0_reg: pcie0reggrp {
519		fsl,pins = <
520			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x41
521		>;
522	};
523
524	pinctrl_pmic: pmicirqgrp {
525		fsl,pins = <
526			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141
527		>;
528	};
529
530	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
531		fsl,pins = <
532			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
533		>;
534	};
535
536	pinctrl_sai2: sai2grp {
537		fsl,pins = <
538			MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
539			MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
540			MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
541			MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6
542		>;
543	};
544
545	pinctrl_sai3: sai3grp {
546		fsl,pins = <
547			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
548			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
549			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
550			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
551		>;
552	};
553
554	pinctrl_typec1: typec1grp {
555		fsl,pins = <
556			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
557		>;
558	};
559
560	pinctrl_uart2: uart2grp {
561		fsl,pins = <
562			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
563			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
564		>;
565	};
566
567	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
568		fsl,pins = <
569			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
570		>;
571	};
572
573	pinctrl_usdhc2: usdhc2grp {
574		fsl,pins = <
575			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
576			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
577			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
578			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
579			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
580			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
581			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
582		>;
583	};
584
585	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
586		fsl,pins = <
587			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
588			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
589			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
590			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
591			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
592			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
593			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
594		>;
595	};
596
597	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
598		fsl,pins = <
599			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
600			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
601			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
602			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
603			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
604			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
605			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
606		>;
607	};
608
609	pinctrl_wdog: wdoggrp {
610		fsl,pins = <
611			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
612		>;
613	};
614
615	pinctrl_backlight: backlightgrp {
616		fsl,pins = <
617			MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT	0x06
618		>;
619	};
620};
621