1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/usb/pd.h>
9#include "imx8mm.dtsi"
10
11/ {
12	chosen {
13		stdout-path = &uart2;
14	};
15
16	memory@40000000 {
17		device_type = "memory";
18		reg = <0x0 0x40000000 0 0x80000000>;
19	};
20
21	leds {
22		compatible = "gpio-leds";
23		pinctrl-names = "default";
24		pinctrl-0 = <&pinctrl_gpio_led>;
25
26		status {
27			label = "status";
28			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
29			default-state = "on";
30		};
31	};
32
33	reg_usdhc2_vmmc: regulator-usdhc2 {
34		compatible = "regulator-fixed";
35		pinctrl-names = "default";
36		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
37		regulator-name = "VSD_3V3";
38		regulator-min-microvolt = <3300000>;
39		regulator-max-microvolt = <3300000>;
40		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
41		enable-active-high;
42	};
43
44	wm8524: audio-codec {
45		#sound-dai-cells = <0>;
46		compatible = "wlf,wm8524";
47		pinctrl-names = "default";
48		pinctrl-0 = <&pinctrl_gpio_wlf>;
49		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
50	};
51
52	sound-wm8524 {
53		compatible = "simple-audio-card";
54		simple-audio-card,name = "wm8524-audio";
55		simple-audio-card,format = "i2s";
56		simple-audio-card,frame-master = <&cpudai>;
57		simple-audio-card,bitclock-master = <&cpudai>;
58		simple-audio-card,widgets =
59			"Line", "Left Line Out Jack",
60			"Line", "Right Line Out Jack";
61		simple-audio-card,routing =
62			"Left Line Out Jack", "LINEVOUTL",
63			"Right Line Out Jack", "LINEVOUTR";
64
65		cpudai: simple-audio-card,cpu {
66			sound-dai = <&sai3>;
67			dai-tdm-slot-num = <2>;
68			dai-tdm-slot-width = <32>;
69		};
70
71		simple-audio-card,codec {
72			sound-dai = <&wm8524>;
73			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
74		};
75	};
76};
77
78&A53_0 {
79	cpu-supply = <&buck2_reg>;
80};
81
82&A53_1 {
83	cpu-supply = <&buck2_reg>;
84};
85
86&A53_2 {
87	cpu-supply = <&buck2_reg>;
88};
89
90&A53_3 {
91	cpu-supply = <&buck2_reg>;
92};
93
94&fec1 {
95	pinctrl-names = "default";
96	pinctrl-0 = <&pinctrl_fec1>;
97	phy-mode = "rgmii-id";
98	phy-handle = <&ethphy0>;
99	fsl,magic-packet;
100	status = "okay";
101
102	mdio {
103		#address-cells = <1>;
104		#size-cells = <0>;
105
106		ethphy0: ethernet-phy@0 {
107			compatible = "ethernet-phy-ieee802.3-c22";
108			reg = <0>;
109			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
110			reset-assert-us = <10000>;
111		};
112	};
113};
114
115&i2c1 {
116	clock-frequency = <400000>;
117	pinctrl-names = "default";
118	pinctrl-0 = <&pinctrl_i2c1>;
119	status = "okay";
120
121	pmic@4b {
122		compatible = "rohm,bd71847";
123		reg = <0x4b>;
124		pinctrl-0 = <&pinctrl_pmic>;
125		interrupt-parent = <&gpio1>;
126		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
127		rohm,reset-snvs-powered;
128
129		#clock-cells = <0>;
130		clocks = <&osc_32k 0>;
131		clock-output-names = "clk-32k-out";
132
133		regulators {
134			buck1_reg: BUCK1 {
135				regulator-name = "buck1";
136				regulator-min-microvolt = <700000>;
137				regulator-max-microvolt = <1300000>;
138				regulator-boot-on;
139				regulator-always-on;
140				regulator-ramp-delay = <1250>;
141			};
142
143			buck2_reg: BUCK2 {
144				regulator-name = "buck2";
145				regulator-min-microvolt = <700000>;
146				regulator-max-microvolt = <1300000>;
147				regulator-boot-on;
148				regulator-always-on;
149				regulator-ramp-delay = <1250>;
150				rohm,dvs-run-voltage = <1000000>;
151				rohm,dvs-idle-voltage = <900000>;
152			};
153
154			buck3_reg: BUCK3 {
155				// BUCK5 in datasheet
156				regulator-name = "buck3";
157				regulator-min-microvolt = <700000>;
158				regulator-max-microvolt = <1350000>;
159				regulator-boot-on;
160				regulator-always-on;
161			};
162
163			buck4_reg: BUCK4 {
164				// BUCK6 in datasheet
165				regulator-name = "buck4";
166				regulator-min-microvolt = <3000000>;
167				regulator-max-microvolt = <3300000>;
168				regulator-boot-on;
169				regulator-always-on;
170			};
171
172			buck5_reg: BUCK5 {
173				// BUCK7 in datasheet
174				regulator-name = "buck5";
175				regulator-min-microvolt = <1605000>;
176				regulator-max-microvolt = <1995000>;
177				regulator-boot-on;
178				regulator-always-on;
179			};
180
181			buck6_reg: BUCK6 {
182				// BUCK8 in datasheet
183				regulator-name = "buck6";
184				regulator-min-microvolt = <800000>;
185				regulator-max-microvolt = <1400000>;
186				regulator-boot-on;
187				regulator-always-on;
188			};
189
190			ldo1_reg: LDO1 {
191				regulator-name = "ldo1";
192				regulator-min-microvolt = <1600000>;
193				regulator-max-microvolt = <3300000>;
194				regulator-boot-on;
195				regulator-always-on;
196			};
197
198			ldo2_reg: LDO2 {
199				regulator-name = "ldo2";
200				regulator-min-microvolt = <800000>;
201				regulator-max-microvolt = <900000>;
202				regulator-boot-on;
203				regulator-always-on;
204			};
205
206			ldo3_reg: LDO3 {
207				regulator-name = "ldo3";
208				regulator-min-microvolt = <1800000>;
209				regulator-max-microvolt = <3300000>;
210				regulator-boot-on;
211				regulator-always-on;
212			};
213
214			ldo4_reg: LDO4 {
215				regulator-name = "ldo4";
216				regulator-min-microvolt = <900000>;
217				regulator-max-microvolt = <1800000>;
218				regulator-boot-on;
219				regulator-always-on;
220			};
221
222			ldo6_reg: LDO6 {
223				regulator-name = "ldo6";
224				regulator-min-microvolt = <900000>;
225				regulator-max-microvolt = <1800000>;
226				regulator-boot-on;
227				regulator-always-on;
228			};
229		};
230	};
231};
232
233&i2c2 {
234	clock-frequency = <400000>;
235	pinctrl-names = "default";
236	pinctrl-0 = <&pinctrl_i2c2>;
237	status = "okay";
238
239	ptn5110: tcpc@50 {
240		compatible = "nxp,ptn5110";
241		pinctrl-names = "default";
242		pinctrl-0 = <&pinctrl_typec1>;
243		reg = <0x50>;
244		interrupt-parent = <&gpio2>;
245		interrupts = <11 8>;
246		status = "okay";
247
248		port {
249			typec1_dr_sw: endpoint {
250				remote-endpoint = <&usb1_drd_sw>;
251			};
252		};
253
254		typec1_con: connector {
255			compatible = "usb-c-connector";
256			label = "USB-C";
257			power-role = "dual";
258			data-role = "dual";
259			try-power-role = "sink";
260			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
261			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
262				     PDO_VAR(5000, 20000, 3000)>;
263			op-sink-microwatt = <15000000>;
264			self-powered;
265		};
266	};
267};
268
269&i2c3 {
270	clock-frequency = <400000>;
271	pinctrl-names = "default";
272	pinctrl-0 = <&pinctrl_i2c3>;
273	status = "okay";
274
275	pca6416: gpio@20 {
276		compatible = "ti,tca6416";
277		reg = <0x20>;
278		gpio-controller;
279		#gpio-cells = <2>;
280	};
281};
282
283&sai3 {
284	pinctrl-names = "default";
285	pinctrl-0 = <&pinctrl_sai3>;
286	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
287	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
288	assigned-clock-rates = <24576000>;
289	status = "okay";
290};
291
292&snvs_pwrkey {
293	status = "okay";
294};
295
296&uart2 { /* console */
297	pinctrl-names = "default";
298	pinctrl-0 = <&pinctrl_uart2>;
299	status = "okay";
300};
301
302&usbotg1 {
303	dr_mode = "otg";
304	hnp-disable;
305	srp-disable;
306	adp-disable;
307	usb-role-switch;
308	samsung,picophy-pre-emp-curr-control = <3>;
309	samsung,picophy-dc-vol-level-adjust = <7>;
310	status = "okay";
311
312	port {
313		usb1_drd_sw: endpoint {
314			remote-endpoint = <&typec1_dr_sw>;
315		};
316	};
317};
318
319&usdhc2 {
320	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
321	assigned-clock-rates = <200000000>;
322	pinctrl-names = "default", "state_100mhz", "state_200mhz";
323	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
324	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
325	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
326	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
327	bus-width = <4>;
328	vmmc-supply = <&reg_usdhc2_vmmc>;
329	status = "okay";
330};
331
332&wdog1 {
333	pinctrl-names = "default";
334	pinctrl-0 = <&pinctrl_wdog>;
335	fsl,ext-reset-output;
336	status = "okay";
337};
338
339&iomuxc {
340	pinctrl_fec1: fec1grp {
341		fsl,pins = <
342			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
343			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
344			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
345			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
346			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
347			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
348			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
349			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
350			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
351			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
352			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
353			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
354			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
355			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
356			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
357		>;
358	};
359
360	pinctrl_gpio_led: gpioledgrp {
361		fsl,pins = <
362			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
363		>;
364	};
365
366	pinctrl_gpio_wlf: gpiowlfgrp {
367		fsl,pins = <
368			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
369		>;
370	};
371
372	pinctrl_i2c1: i2c1grp {
373		fsl,pins = <
374			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
375			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
376		>;
377	};
378
379	pinctrl_i2c2: i2c2grp {
380		fsl,pins = <
381			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
382			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
383		>;
384	};
385
386	pinctrl_i2c3: i2c3grp {
387		fsl,pins = <
388			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
389			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
390		>;
391	};
392
393	pinctrl_pmic: pmicirqgrp {
394		fsl,pins = <
395			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141
396		>;
397	};
398
399	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
400		fsl,pins = <
401			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
402		>;
403	};
404
405	pinctrl_sai3: sai3grp {
406		fsl,pins = <
407			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
408			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
409			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
410			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
411		>;
412	};
413
414	pinctrl_typec1: typec1grp {
415		fsl,pins = <
416			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
417		>;
418	};
419
420	pinctrl_uart2: uart2grp {
421		fsl,pins = <
422			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
423			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
424		>;
425	};
426
427	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
428		fsl,pins = <
429			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
430		>;
431	};
432
433	pinctrl_usdhc2: usdhc2grp {
434		fsl,pins = <
435			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
436			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
437			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
438			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
439			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
440			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
441			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
442		>;
443	};
444
445	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
446		fsl,pins = <
447			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
448			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
449			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
450			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
451			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
452			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
453			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
454		>;
455	};
456
457	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
458		fsl,pins = <
459			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
460			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
461			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
462			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
463			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
464			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
465			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
466		>;
467	};
468
469	pinctrl_wdog: wdoggrp {
470		fsl,pins = <
471			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
472		>;
473	};
474};
475