1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/usb/pd.h>
9#include "imx8mm.dtsi"
10
11/ {
12	model = "FSL i.MX8MM EVK board";
13	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
14
15	chosen {
16		stdout-path = &uart2;
17	};
18
19	leds {
20		compatible = "gpio-leds";
21		pinctrl-names = "default";
22		pinctrl-0 = <&pinctrl_gpio_led>;
23
24		status {
25			label = "status";
26			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
27			default-state = "on";
28		};
29	};
30
31	reg_usdhc2_vmmc: regulator-usdhc2 {
32		compatible = "regulator-fixed";
33		pinctrl-names = "default";
34		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
35		regulator-name = "VSD_3V3";
36		regulator-min-microvolt = <3300000>;
37		regulator-max-microvolt = <3300000>;
38		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
39		enable-active-high;
40	};
41
42	wm8524: audio-codec {
43		#sound-dai-cells = <0>;
44		compatible = "wlf,wm8524";
45		pinctrl-names = "default";
46		pinctrl-0 = <&pinctrl_gpio_wlf>;
47		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
48	};
49
50	sound-wm8524 {
51		compatible = "simple-audio-card";
52		simple-audio-card,name = "wm8524-audio";
53		simple-audio-card,format = "i2s";
54		simple-audio-card,frame-master = <&cpudai>;
55		simple-audio-card,bitclock-master = <&cpudai>;
56		simple-audio-card,widgets =
57			"Line", "Left Line Out Jack",
58			"Line", "Right Line Out Jack";
59		simple-audio-card,routing =
60			"Left Line Out Jack", "LINEVOUTL",
61			"Right Line Out Jack", "LINEVOUTR";
62
63		cpudai: simple-audio-card,cpu {
64			sound-dai = <&sai3>;
65		};
66
67		simple-audio-card,codec {
68			sound-dai = <&wm8524>;
69			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
70		};
71	};
72};
73
74&A53_0 {
75	cpu-supply = <&buck2_reg>;
76};
77
78&fec1 {
79	pinctrl-names = "default";
80	pinctrl-0 = <&pinctrl_fec1>;
81	phy-mode = "rgmii-id";
82	phy-handle = <&ethphy0>;
83	fsl,magic-packet;
84	status = "okay";
85
86	mdio {
87		#address-cells = <1>;
88		#size-cells = <0>;
89
90		ethphy0: ethernet-phy@0 {
91			compatible = "ethernet-phy-ieee802.3-c22";
92			reg = <0>;
93			at803x,led-act-blind-workaround;
94			at803x,eee-okay;
95			at803x,vddio-1p8v;
96		};
97	};
98};
99
100&sai3 {
101	pinctrl-names = "default";
102	pinctrl-0 = <&pinctrl_sai3>;
103	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
104	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
105	assigned-clock-rates = <24576000>;
106	status = "okay";
107};
108
109&snvs_pwrkey {
110	status = "okay";
111};
112
113&uart2 { /* console */
114	pinctrl-names = "default";
115	pinctrl-0 = <&pinctrl_uart2>;
116	status = "okay";
117};
118
119&usbotg1 {
120	dr_mode = "otg";
121	hnp-disable;
122	srp-disable;
123	adp-disable;
124	usb-role-switch;
125	status = "okay";
126
127	port {
128		usb1_drd_sw: endpoint {
129			remote-endpoint = <&typec1_dr_sw>;
130		};
131	};
132};
133
134&usdhc2 {
135	pinctrl-names = "default", "state_100mhz", "state_200mhz";
136	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
137	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
138	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
139	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
140	bus-width = <4>;
141	vmmc-supply = <&reg_usdhc2_vmmc>;
142	status = "okay";
143};
144
145&usdhc3 {
146	pinctrl-names = "default", "state_100mhz", "state_200mhz";
147	pinctrl-0 = <&pinctrl_usdhc3>;
148	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
149	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
150	bus-width = <8>;
151	non-removable;
152	status = "okay";
153};
154
155&wdog1 {
156	pinctrl-names = "default";
157	pinctrl-0 = <&pinctrl_wdog>;
158	fsl,ext-reset-output;
159	status = "okay";
160};
161
162&i2c1 {
163	clock-frequency = <400000>;
164	pinctrl-names = "default";
165	pinctrl-0 = <&pinctrl_i2c1>;
166	status = "okay";
167
168	pmic@4b {
169		compatible = "rohm,bd71847";
170		reg = <0x4b>;
171		pinctrl-0 = <&pinctrl_pmic>;
172		interrupt-parent = <&gpio1>;
173		interrupts = <3 GPIO_ACTIVE_LOW>;
174		rohm,reset-snvs-powered;
175
176		regulators {
177			buck1_reg: BUCK1 {
178				regulator-name = "BUCK1";
179				regulator-min-microvolt = <700000>;
180				regulator-max-microvolt = <1300000>;
181				regulator-boot-on;
182				regulator-always-on;
183				regulator-ramp-delay = <1250>;
184			};
185
186			buck2_reg: BUCK2 {
187				regulator-name = "BUCK2";
188				regulator-min-microvolt = <700000>;
189				regulator-max-microvolt = <1300000>;
190				regulator-boot-on;
191				regulator-always-on;
192				regulator-ramp-delay = <1250>;
193				rohm,dvs-run-voltage = <1000000>;
194				rohm,dvs-idle-voltage = <900000>;
195			};
196
197			buck3_reg: BUCK3 {
198				// BUCK5 in datasheet
199				regulator-name = "BUCK3";
200				regulator-min-microvolt = <700000>;
201				regulator-max-microvolt = <1350000>;
202				regulator-boot-on;
203				regulator-always-on;
204			};
205
206			buck4_reg: BUCK4 {
207				// BUCK6 in datasheet
208				regulator-name = "BUCK4";
209				regulator-min-microvolt = <3000000>;
210				regulator-max-microvolt = <3300000>;
211				regulator-boot-on;
212				regulator-always-on;
213			};
214
215			buck5_reg: BUCK5 {
216				// BUCK7 in datasheet
217				regulator-name = "BUCK5";
218				regulator-min-microvolt = <1605000>;
219				regulator-max-microvolt = <1995000>;
220				regulator-boot-on;
221				regulator-always-on;
222			};
223
224			buck6_reg: BUCK6 {
225				// BUCK8 in datasheet
226				regulator-name = "BUCK6";
227				regulator-min-microvolt = <800000>;
228				regulator-max-microvolt = <1400000>;
229				regulator-boot-on;
230				regulator-always-on;
231			};
232
233			ldo1_reg: LDO1 {
234				regulator-name = "LDO1";
235				regulator-min-microvolt = <3000000>;
236				regulator-max-microvolt = <3300000>;
237				regulator-boot-on;
238				regulator-always-on;
239			};
240
241			ldo2_reg: LDO2 {
242				regulator-name = "LDO2";
243				regulator-min-microvolt = <900000>;
244				regulator-max-microvolt = <900000>;
245				regulator-boot-on;
246				regulator-always-on;
247			};
248
249			ldo3_reg: LDO3 {
250				regulator-name = "LDO3";
251				regulator-min-microvolt = <1800000>;
252				regulator-max-microvolt = <3300000>;
253				regulator-boot-on;
254				regulator-always-on;
255			};
256
257			ldo4_reg: LDO4 {
258				regulator-name = "LDO4";
259				regulator-min-microvolt = <900000>;
260				regulator-max-microvolt = <1800000>;
261				regulator-boot-on;
262				regulator-always-on;
263			};
264
265			ldo6_reg: LDO6 {
266				regulator-name = "LDO6";
267				regulator-min-microvolt = <900000>;
268				regulator-max-microvolt = <1800000>;
269				regulator-boot-on;
270				regulator-always-on;
271			};
272		};
273	};
274};
275
276&i2c2 {
277	clock-frequency = <400000>;
278	pinctrl-names = "default";
279	pinctrl-0 = <&pinctrl_i2c2>;
280	status = "okay";
281
282	ptn5110: tcpc@50 {
283		compatible = "nxp,ptn5110";
284		pinctrl-names = "default";
285		pinctrl-0 = <&pinctrl_typec1>;
286		reg = <0x50>;
287		interrupt-parent = <&gpio2>;
288		interrupts = <11 8>;
289		status = "okay";
290
291		port {
292			typec1_dr_sw: endpoint {
293				remote-endpoint = <&usb1_drd_sw>;
294			};
295		};
296
297		typec1_con: connector {
298			compatible = "usb-c-connector";
299			label = "USB-C";
300			power-role = "dual";
301			data-role = "dual";
302			try-power-role = "sink";
303			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
304			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
305				     PDO_VAR(5000, 20000, 3000)>;
306			op-sink-microwatt = <15000000>;
307			self-powered;
308		};
309	};
310};
311
312&iomuxc {
313	pinctrl-names = "default";
314
315	pinctrl_fec1: fec1grp {
316		fsl,pins = <
317			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
318			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
319			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
320			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
321			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
322			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
323			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
324			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
325			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
326			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
327			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
328			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
329			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
330			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
331			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
332		>;
333	};
334
335	pinctrl_gpio_led: gpioledgrp {
336		fsl,pins = <
337			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
338		>;
339	};
340
341	pinctrl_gpio_wlf: gpiowlfgrp {
342		fsl,pins = <
343			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
344		>;
345	};
346
347	pinctrl_i2c1: i2c1grp {
348		fsl,pins = <
349			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
350			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
351		>;
352	};
353
354	pinctrl_i2c2: i2c2grp {
355		fsl,pins = <
356			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
357			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
358		>;
359	};
360
361	pinctrl_pmic: pmicirq {
362		fsl,pins = <
363			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
364		>;
365	};
366
367	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
368		fsl,pins = <
369			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
370		>;
371	};
372
373	pinctrl_sai3: sai3grp {
374		fsl,pins = <
375			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
376			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
377			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
378			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
379		>;
380	};
381
382	pinctrl_typec1: typec1grp {
383		fsl,pins = <
384			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
385		>;
386	};
387
388	pinctrl_uart2: uart2grp {
389		fsl,pins = <
390			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
391			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
392		>;
393	};
394
395	pinctrl_usdhc2_gpio: usdhc2grpgpio {
396		fsl,pins = <
397			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
398		>;
399	};
400
401	pinctrl_usdhc2: usdhc2grp {
402		fsl,pins = <
403			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
404			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
405			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
406			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
407			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
408			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
409			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
410		>;
411	};
412
413	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
414		fsl,pins = <
415			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
416			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
417			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
418			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
419			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
420			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
421			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
422		>;
423	};
424
425	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
426		fsl,pins = <
427			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
428			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
429			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
430			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
431			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
432			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
433			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
434		>;
435	};
436
437	pinctrl_usdhc3: usdhc3grp {
438		fsl,pins = <
439			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
440			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
441			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
442			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
443			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
444			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
445			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
446			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
447			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
448			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
449			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190
450		>;
451	};
452
453	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
454		fsl,pins = <
455			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
456			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
457			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
458			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
459			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
460			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
461			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
462			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
463			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
464			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
465			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194
466		>;
467	};
468
469	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
470		fsl,pins = <
471			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
472			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
473			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
474			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
475			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
476			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
477			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
478			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
479			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
480			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
481			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196
482		>;
483	};
484
485	pinctrl_wdog: wdoggrp {
486		fsl,pins = <
487			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
488		>;
489	};
490};
491